CN1482677A - 电子元件 - Google Patents
电子元件 Download PDFInfo
- Publication number
- CN1482677A CN1482677A CNA031238033A CN03123803A CN1482677A CN 1482677 A CN1482677 A CN 1482677A CN A031238033 A CNA031238033 A CN A031238033A CN 03123803 A CN03123803 A CN 03123803A CN 1482677 A CN1482677 A CN 1482677A
- Authority
- CN
- China
- Prior art keywords
- circuit board
- electronic component
- wired circuit
- semiconductor element
- electrode district
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
配线电路板2被设置成把半导体芯片1包在里面,在配线电路板的外面侧,在其上面、侧面和底面上进行三维配置,并为了与外部进行电连接,安装了与设于配线电路板2的配线图案的电极区连接的多个外部端子8。依据这种结构,能提供即使对于最终产品的多种多样的设计也可自由进行电子装置配置的电子元件的结构和采用该电子元件的电子装置。
Description
技术领域
本发明涉及电子元件,具体涉及具有可三维安装结构的电子元件。
背景技术
如图45所示,传统的电子元件(半导体元件等)200的外部端子适合在印刷电路板210那样的平面(二维)电路板上进行配置,在电子元件200的侧面部成一列配置在同一线上,这种情况很常见。另外,作为外部端子的另一种形状,还有在电子零件的面对印刷电路板的一侧,一种被称为凸起电极的大致为球形的电极在同一个平面上设置的情况。
另外,如图45所示,在电子装置(将半导体元件复合安装的半导体装置等)300中,在把电子元件200装到印刷电路板210情况下,在印刷电路板210的表面上二维配置,利用设置在印刷电路板210的端边上的外部连接端子220与其它电子装置连接。
采用上述电子元件的电子装置的场合,大多使用只能二维利用空间的平板状电路板,而由于最终产品的多种多样的设计上的制约,为了高效配置平板状的电路板,就需要在设计上付出劳力。另外,偶尔,也有要求最终产品作设计变更的情况。
发明内容
本发明的目的为了解决上述课题,提供面对最终产品的多种多样的设计也可以自由地进行电子装置的配置的电子元件的结构,以及采用这种电子元件的电子装置。
为解决上述课题,本发明的电子元件中设有:由电子零件与柔性材料构成、配置成包围所述电子零件,在其外表面上设置预定的配线图案、与所述电子零件的电极区进行电连接的配线电路板;在上述配线电路板的外表面上成三维配置、为与外部进行电连接而连接到上述配线图案的电极区上的多个外部端子。另外,作为上述电子零件,包括:半导体芯片那样的有源元件和电容、电阻等的无源元件。
按照这种结构,由于配线电路板的外表面上设有三维的外部端子,在电子元件的布局设计上,不仅可以作传统的二维配置,也可以实现三维配置。其结果,在设计由多个电子元件组成的电子装置的时候,比起传统的形状来,可以更自由地决定电子装置的形状,可以大幅度提高电子装置的设计自由度。
另外,依据基于本发明的电子装置,可以把上述电子元件的各自选择的外部端子相互间进行连接来构成。根据这种结构,由于电子元件被三维配置,在设计由多个电子元件构成的电子装置的时候,比起传统的形状来,可以更自由地决定电子装置的形状,可以大幅度提高电子装置设计的自由度。再者,也可以使信号的数量飞跃地增加。
附图说明
图1是表示实施例1中的半导体元件的结构的整体透视图。
图2是仅表示实施例1中的半导体元件的内部结构的透视图。
图3是图1中III-III线处的剖面图。
图4是图1中IV-IV线处的剖面图。
图5是表示实施例1中具有其它外部形状的半导体元件的结构的整体透视图。
图6是仅表示图5所示的半导体元件的内部结构的透视图。
图7是表示在实施例1中具有另一外部形状的半导体元件的结构的整体透视图。
图8是仅表示图7所示的半导体元件的内部结构的透视图。
图9是表示实施例1中具有另一外部形状的半导体元件的结构的整体透视图。
图10是仅表示图9所示的半导体元件的内部结构的透视图。
图11是表示实施例2中的半导体元件结构的整体透视图。
图12是仅表示实施例2中的半导体元件的内部结构的透视图。
图13是图11中的XIII-XIII线处的剖面图。
图14是图1 1中的XIV-XIV线处的剖面图。
图15是表示实施例2中具有另一外部形状的半导体元件结构的整体透视图。
图16是仅表示图15所示的半导体元件的内部结构的透视图。
图17是表示实施例2中具有另一外部形状的半导体元件结构的整体透视图。
图18是仅表示图17所示的半导体元件的内部结构的透视图。
图19是表示实施例2中具有另一外部形状的半导体元件的结构的整体透视图。
图20是仅表示图19所示的半导体元件的内部结构的透视图。
图21~图25是表示实施例3至实施例7中的半导体元件的结构的剖面图。
图26是表示实施例8中的电子元件的结构的剖面图。
图27是表示实施例9中的半导体装置的整体结构的剖面结构图。
图28是表示实施例10中的半导体装置的整体结构的剖面结构图。
图29是表示实施例11中的半导体装置的整体结构的剖面结构图。
图30是表示实施例11中的半导体装置的整体结构的透视图。
图31至图37是表示实施例12中的半导体元件的制造方法的从第1至第7工序图。
图38至图44是表示实施例13中的半导体元件的制造方法的从第1至第7工序图。
图45是表示传统电子元件(半导体装置等)的结构的整体透视图。
具体实施方式
下面,参照附图就本发明的电子元件和使用该电子元件的电子装置的结构进行说明。(实施例1)
参看图1至图4,就本实施例中作为电子元件的一例的半导体元件111的结构进行说明。
(半导体元件111的结构)
参看图1~图4,该半导体元件111内部设有作为电子零件的半导体芯片1。在该半导体芯片1上表面的长度方向的两侧设有多个电极区3。
设置由柔性材料构成的、包围半导体芯片1的配线电路板2。作为配线电路板2的材料,例如可以采用聚酰亚胺,环氧玻璃等。
配线电路板2把半导体芯片1包在里面并在与设置半导体芯片的电极区3的一侧的同侧上,设置配线电路板2的端部相互间的对接部2A。
在配线电路板2的外面侧上设置预定的配线图案(省略图示),设置在配线电路板2的外面侧上的电极区2B与设置在半导体芯片1上的电极区3之间用导线电气连接。配线电路板2通过粘结层5、6粘接固定在半导体芯片1上。
形成密封用的密封树脂7,以覆盖电极区2B、3和导线4,同时填埋半导体芯片1与配线电路板2之间的间隙。由于该密封树脂7的作用,防止了电极区2B、3和导线4的外部与其它端子的短路,防止了电极区2B、3和导线4的连接区中的破损,可以提高半导体元件111的可靠性。
在配线电路板2的外面侧,在其上面、侧面和底面作三维配置,为了与外部进行电连接而设有连接到配线图案的电极区的多个外部端子8。该外部端子8由金属材料制成,具有大致为球形的形状。(变形例)
作为由与上述半导体元件111同样的结构构成的、具有其它外部形状的半导体元件,还可以举例出:图5和图6所示的半导体元件112、图7和图8所示的半导体元件113和图9和图10所示的半导体元件114。
图5、图7和图9都是表示半导体元件112、113、114的结构的整体透视图,图6、图8、和图10都是仅表示半导体元件112、113、114的内部结构的透视图。再有,在与上述半导体元件111相同或相当的部分上,带有相同参照号,就不再重复说明。
图5和图6所示的半导体元件112有以下的结构。在半导体芯片1的中央部分横向地设置电极区3。在配线电路板2上,对应于图3,在上面、侧面和底面上设有外部端子8(在图4所示的侧面上没有设置外部端子8)。
另外,图7和图8所示的半导体元件113有以下的结构。在半导体芯片1的对角线上设有电极区3。配线电路板2沿半导体芯片1的四边折叠。在配线电路板2的上面、侧面、底面的所有面上设置外部端子8。
再者,图9和图10所示的半导体元件114有以下的结构。沿半导体芯片1的四边设有电极区3。在配线电路板2上,沿半导体芯片的四边设有4个为了使导线4通过的开口部2C。配线电路板2沿半导体芯片1的四边折叠。在配线电路板2的上面、侧面、底面的所有面上设有外部端子8。
以上,若用由上述结构构成的半导体元件111、112、113、114,则由于在配线电路板2的外表面设有3维外部端子8,因而在半导体元件的配置中,不仅可以作传统的二维配置,也可以实现三维配置。结果,在设计由多个半导体元件构成的电子装置时,比起传统的形状来,可以更自由地决定电子装置的形状,可以大幅度地提高电子装置设计的自由度。
再有,设置外部端子8的位置,如果设置在从上面、底面和任意的侧面中选择性地挑选出的三个面上,通过三维配置外部端子8,就可以得到上述的作用效果。因而,不一定要在所有的面上设置外部端子。在以下所示的实施例中也一样。(实施例2)
下面,参照图11至图14,就作为本实施例中的电子元件的一例的半导体元件121的结构进行说明。另外,在与上述半导体元件111相同或相当部分上附加相同的参照号,不再重复说明。(半导体元件121的结构)
参看图11~图14,与实施例1中的半导体元件111相比,该半导体元件121的不同点在于:在配线电路板2的端部彼此之间的对接部2A被设在半导体芯片1的电极区3的设置侧的对侧。其它的结构与实施例1中的半导体元件111相同。(变形例)
作为由与上述半导体元件121同样结构构成的具有其它外部形状的半导体元件,例如有:图15和图16所示的半导体元件122、图17和图18所示的半导体元件123以及图19和图20所示的半导体元件124。
图15、图17和图19都是表示半导体元件122、123、124的结构的整体透视图,图16、图18和图20都是仅表示半导体元件122、123、124的内部结构的透视图。再有,与上述半导体元件121相同或相当的部分均附有相同的参照号,不再重复说明。
图15和图16所示的半导体元件122中设有横跨半导体芯片1的中央部分的电极区3。并且,配线电路板2上让导线通过的开口部2D,设置在与半导体芯片1的中央部分相对的位置上。除了配线电路板2的端部的对接部2A设在与半导体芯片1的电极区3被设置的一侧的对侧这一点之外,其余的结构与图5所示的半导体元件112相同。
另外,图17和图18所示的半导体元件123及图19和图20所示的半导体元件124是这样,除了配线电路板2的端部的对接部2A设在半导体芯片1的电极区3被设置的一侧的对侧这一点之外,其余均与图7所示的半导体元件113和图9所示的半导体元件114相同。
通过用上述结构的半导体元件121、122、123、124在配线电路板2的外面侧设置三维的外部端子8,在半导体元件的布局设计上,不仅可作传统的二维配置,也可以实现三维配置。其结果,在设计由多个半导体元件构成的电子装置时,比之传统的形状,可以更自由地决定电子装置的形状,可以大幅度地提高电子装置设计的自由度。(实施例3~7)
这里,参照图21~图25说明上述实施例2的图19所示的结构的半导体元件124的变形例。各图所示的剖面结构不仅适用于图9和图19所示的结构,也可以适用于上述的实施例1中的半导体元件111、112、113、114和实施例2中的半导体元件121、122、123、124。(实施例3)
首先,参照图21,就本实施例中的半导体元件131的结构进行说明。该半导体元件131的结构特征是,用直接设置在配线电路板2的外表面上的配线突起部9代替上述各实施例中使用的导线,用该配线突起部9跟设置在半导体芯片1上的电极区3连接。使用这个结构也可以得到与上述各实施例相同的作用效果。(实施例4)
接着,参照图22,就本实施例中的半导体元件141的结构进行说明。该半导体元件141的结构特征在于:与上述半导体元件131相比,除了该半导体元件141仅是配线电路板2的端部的对接部2A设在半导体芯片1的电极区3的设置侧的对侧这一点不同,其它的结构与实施例3中的半导体元件131相同。采用这个结构也可以得到与上述各实施例同样的作用效果。(实施例5)
接着,参照图23,就本实施例中的半导体元件151的结构进行说明。该半导体元件151的结构特征在于:与上述半导体元件131相比,配线电路板2的电极区2B设置在配线电路板2的内侧,该电极区2B与设置在半导体芯片1上的电极区3用导体凸起10连接。用该结构也可以得到与所述各实施例同样的作用效果。(实施例6)
下面,参照图24,就本实施例中的半导体元件161的结构进行说明。该半导体元件161的结构特征在于:与上述半导体元件151相比,该半导体元件161在配线电路板2的端部的对接部2A设在半导体芯片1的电极区3被设置的一侧的对侧这一点上不同。其它的结构与实施例5中的半导体元件151相同。用这个结构也可以得到与上述各实施例相同的作用效果。(实施例7)
首先,参照图25,就本实施例中的半导体元件171的结构进行说明。该半导体元件171的结构特征在于:对于上述各实施例中的结构,为了增加配线电路板2的外表面上的配线总数而设置配线层2E。用这个结构也可以得到与上述各实施例同样的作用效果。另外,即使采用配线电路板2的端部的对接部2A位于半导体芯片1的电极区3被设置的一侧的对侧的结构,也可以得到同样的作用与效果。(实施例8)
上述的实施例1~7是有关使用了所有有源元件的半导体芯片1的半导体元件的结构,而本实施例所涉及的是如图26的剖面图所示那样,把所示的电容、电阻等无源元件11、12用配线电路板2覆盖的电子元件181的结构。其它的结构与把上述实施例1~7的半导体芯片1置换成无源元件11、12后的结构相同。
由于该结构也在配线电路板2的外表面上设置了三维的外部端子8,所以,在无源元件的布局设计上,不仅可以作传统的二维配置,也可以实现三维配置。其结构,在设计由多个无源元件构成的电子装置时,比起传统技术来,可以更自由地决定电子装置的形状,从而可以大幅度提高电子装置的设计自由度。(实施例9~11)
上述实施例1~8全部是有关电子元件结构的内容,而下面示出的实施例9~11涉及采用实施例1~8所示的元件的电子装置的结构。另外,作为示例,就使用实施例7中的半导体元件情况进行说明,但并不受限于该半导体元件171,也可以使用实施例1~6中所示的半导体元件111、112、113、114、121、122、123、124、131、141、151、161以及电子元件181。(实施例9)
关于本实施例中的电子装置201的结构,参照图27进行说明。该电子装置201,让从设置于半导体元件171的外部端子8中所选择的外部端子8相互直接连接,从而形成三维结构。
按照这种结构,由于半导体元件171的三维配置,在设计由多个半导体元件171构成的电子装置201的时候,比起传统的形状来,可以更自由地决定电子装置201的形状,大幅度地提高电子装置201的设计自由度。另外,也使信号的数量得以飞跃增加。(实施例10)
关于本实施例中的电子装置202的结构,参照图28进行说明。该电子装置202与上述电子装置201的结构相比,其特征在于:让导体材料介入外部端子8的连接。作为该导体材料,可以用导体片用无源元件22。在本结构中,也可以得到与上述实施例9的场合同样的作用与效果。(实施例11)
关于本实施例中的电子装置203的结构,参照图29和图30来进行说明。该电子装置203在对预定的位置设有多个外部电极31和多个内部电极32的筒状电路板30的内部,配置多个半导体元件171,使半导体元件171与所设的外部端子8相互间选择性地连接而构成的。本实施例中,图示的是螺旋状配置多个半导体元件171的情况,但并不局限于螺旋状,也可以采用任意的层叠结构构成的三维结构。如图30所示,筒状电路板的内部通过填充树脂33来加以树脂密封。本结构也可以得到与上述实施例9的场合同样的作用效果。(实施例12)
接下来,就上述半导体元件的制造方法,以图7所示的实施例1的半导体元件113作为一例,参照图31至图37来进行说明。首先,如图31所示,准备带状配线电路板2F,在该带状配线电路板2F上,通过冲切加工形成4个预定形状的开口部2H,形成大致为四边形的底面区2a,从底面区2a的四边成放射状延伸的大致为三角形状的折弯区2b、2c、2d、2e。考虑到加工性,底面区2a处于用构架2k与带状配线电路板2F相连的状态。接着,预先在底面区2a和折弯区2b、2c、2d、2e的连接部分的外面侧的预定位置上安装外部端子8。
然后,参看图32,用粘结胶带(粘结层)5把半导体芯片1固定在底面区2a上。另外,在折弯区2b、2c、2d、2e上也预先粘贴各自的粘结胶带(粘结层)6。然后,参看图33,把折弯区2b、2c、2d、2e折弯成包住半导体芯片1,把折弯区2b、2c、2d、2e固定在半导体芯片1的表面一侧。
接着,参看图34,用导线4连接设置在配线电路板2的外表面的电极区2B和设置在半导体芯片1上的电极区3(引线接合)。然后,参看图35和图36,用树脂7注入装置70进行树脂的注入(树脂密封),使其覆盖由导线4连接电极区2B与电极区3的连接区域,同时填充半导体芯片1与配线电路板2之间产生的间隙区域。
接着,参看图37,在底面区2a和折弯区2b、2c、2d、2e的外面侧的预定位置上安装多个外部端子8。然后,通过切断带状配线电路板2F的构架2K,完成半导体元件113。
这样一来,通过利用带状配线电路板2F形成半导体元件1 13,配置包围半导体芯片1那样的配线电路板2,就可以在配线电路板2的外面侧安装外部端子8。另外,由于也可以适用于批量生产线,故可实现生产率的提高。(实施例13)
下面,就上述半导体元件的制造方法,以图9所示的半导体元件114作为一例,参照图38至图44进行说明。首先,如图38所示,准备带状配线电路板2F,在该带状配线电路板2F上,用冲切的方法形成4个预定形状的开口部2H,并形成大致为四边形的底面区2a、从底面区2a的四边放射状延伸的折弯区2b、2c、2d、2e。在折弯区2b、2c、2d、2e上形成各自的开口部2C。另外,为了加工的方便,底面区2a做成为用构架2K连接到带状配线电路板2F上的状态。然后,预先在底面区2a和折弯区2b、2c、2d、2e的连接部分的外面侧的预定位置上安装外部端子8。
接着,参照图39,用粘结胶带(粘结层)把半导体芯片1固定在底面区2a上。另外,在折弯区2b、2c、2d、2e上也预先粘贴各自的粘结胶带(粘结层)6。还有,要注意不要用粘接胶带(粘结层)6覆盖开口部2C。之后,参照图40,把折弯区2b、2c、2d、2e折弯,使其包住半导体芯片1,把折弯区2b、2c、2d、2e固定在半导体芯片1的表面侧。
继之,参照图41,进行导线配线,使导线穿过开口部2c,用导线4连接设置在配线电路板2的外面侧的电极区2B和设置在半导体芯片1上的电极区3(引线接合)。然后,参照图42和图43,用树脂注入装置70进行树脂7的注入(树脂密封),使其覆盖将由导线4连接电极区2B和电极区3的连接区域露出的开口部2c,同时将半导体芯片1与配线电路板2之间产生的间隙区域填埋。
接下来,参照图44,在底面区2a和折弯区2b、2c、2d、2e的外面侧的预定位置上,安装多个外部端子8。然后,通过切断带状配线电路板2F的构架2K,完成半导体元件114。
这样一来,通过利用带状配线电路板2F形成半导体元件114,就可以配置包围半导体芯片1的配线电路板2,在配线电路板2的外面侧安装外部端子8。并且,由于也可以适用于批量生产线,故可以谋求生产率的提高。
另外,上述的实施例12和13示出对于实施例1中所示的半导体元件113和114的制造方法,但是,也可以应用同样的制造方法来制造实施例2至7所示的半导体元件以及实施例8所示的电子元件。
再有,为了在更理想的状态下实现上述电子元件,采用以下所述的实施方式。
例如,上述电子元件中,最好设有用以连接设置在上述电子零件上的电极区与上述配线电路板的预定电极区的连接件,以及设置在上述电子零件与上述配线电路板之间的粘结层,并至少要用树脂密封上述电极区与上述连接件。这样一来,通过树脂密封电极区和连接件,可以防止与外部的其它电气端子的短路,防止电极区与连接件的连接区域中的破损,可以提高电子零件的可靠性。
并且,上述电子元件中,上述配线电路板的预定的电极区,最好设置在上述配线电路板的外面侧或内面侧。
并且,上述电子元件中,最好在与上述电子零件的上述电极区的设置侧相同的面侧上配置上述电路板的端部的对接部,以将上述电子零件包在里面。
并且,上述电子元件中,最好在与上述电子零件的上述电极区的设置侧相对的面侧上配置所属电路板的端部的对接部,以将上述电子零件包在里面。
并且,上述电子元件中,最好在上述电路板与上述外部端子之间设置配线层。
并且,上述电子元件中,最好在上述配线电路板的内面侧设置预定的电极区,将上述电子零件上设置的电极区与上述配线电路板的预定的电极区直接连接,在上述配线电路板的内部,用树脂密封上述电子零件。
并且,上述电子装置中,最好具有这样的特征:各个被选择的上述外部端子相互之间直接连接。
并且,上述电子装置中,最好具有这样的特征:各个被选择的上述外部端子之间夹入导电构件。
并且,上述电子装置最好具有这样的结构:在分别对应于其外表面和内表面设置外部端子和内部电极的的筒状电路板的内部安装上述电子装置,在使上述外部端子连接到预定的上述内部电极的状态下将上述电子装置树脂密封在筒状电路板的内部。
依据基于本发明的电子元件和电子装置,由于配线电路板的外面侧设有三维的外部端子,因而在电子元件的配置中,不仅可以作传统的二维配置,也可实现三维配置。其结果,在设计由多个电子元件构成的电子装置的时候,比起传统的形状来,可以更自由地决定电子装置的形状,可以大幅度地提高电子装置的设计自由度。
Claims (8)
1.一种电子元件,其中设有:
电子零件;
由柔性材料构成的、为包围所述电子零件而配置的、其外面侧设置有预定配线图案并与所述电子零件的电极区作电连接的配线电路板;以及
在所述配线电路板的外面侧三维配置的、为了与外部进行电连接而与所述配线图案的电极区连接的多个外部端子。
2.如权利要求1所述的电子元件,其特征在于:
设有用以将所述电子零件上所设的电极区和所述配线电路板的预定电极区连接的连接件,以及
设在所述电子零件与所述配线电路板之间的粘结层;
至少对所述电极区与所述连接件进行树脂密封。
3.如权利要求2所述的电子元件,其特征在于:所述配线电路板的预定的电极区设置在所述配线电路板的外面侧。
4.如权利要求2所述的电子元件,其特征在于:所述配线电路板的预定的电极区设置在所述配线电路板的内面侧。
5.如权利要求1所述的电子元件,其特征在于:在与所述电子零件的所述电极区的设置侧相同的面侧配置所述配线电路板的端部之间的对接部,以将所述电子零件包入。
6.如权利要求1所述的电子元件,其特征在于:在与所述电子零件的所述电极区的设置侧相对的面侧配置所述配线电路板的端部之间的对接部,以将所述电子零件包入。
7.如权利要求1所述的电子元件,其特征在于:在所述配线电路板与所述外部端子之间设配线层。
8.如权利要求1所述的电子元件,其特征在于:
在所述配线电路板的内面侧设置预定的电极区;
所述电子零件上所设的电极区和所述配线电路板的预定电极区直接连接;
在所述配线电路板的内部,用树脂密封所述电子零件。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP264030/2002 | 2002-09-10 | ||
JP2002264030A JP2004103843A (ja) | 2002-09-10 | 2002-09-10 | 電子素子およびその電子素子を用いた電子装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1482677A true CN1482677A (zh) | 2004-03-17 |
Family
ID=31986485
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA031238033A Pending CN1482677A (zh) | 2002-09-10 | 2003-05-12 | 电子元件 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6730855B2 (zh) |
JP (1) | JP2004103843A (zh) |
KR (1) | KR100628872B1 (zh) |
CN (1) | CN1482677A (zh) |
TW (1) | TW589722B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103997848B (zh) * | 2014-05-30 | 2017-01-11 | 昆山一邦泰汽车零部件制造有限公司 | 一种筒式旋转印刷电路筒 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7115986B2 (en) * | 2001-05-02 | 2006-10-03 | Micron Technology, Inc. | Flexible ball grid array chip scale packages |
SG122743A1 (en) * | 2001-08-21 | 2006-06-29 | Micron Technology Inc | Microelectronic devices and methods of manufacture |
SG104293A1 (en) * | 2002-01-09 | 2004-06-21 | Micron Technology Inc | Elimination of rdl using tape base flip chip on flex for die stacking |
US6975035B2 (en) * | 2002-03-04 | 2005-12-13 | Micron Technology, Inc. | Method and apparatus for dielectric filling of flip chip on interposer assembly |
SG115456A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Semiconductor die packages with recessed interconnecting structures and methods for assembling the same |
SG115455A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Methods for assembly and packaging of flip chip configured dice with interposer |
SG115459A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Flip chip packaging using recessed interposer terminals |
SG111935A1 (en) * | 2002-03-04 | 2005-06-29 | Micron Technology Inc | Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods |
SG121707A1 (en) * | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
US20040036170A1 (en) * | 2002-08-20 | 2004-02-26 | Lee Teck Kheng | Double bumping of flexible substrate for first and second level interconnects |
US7112877B2 (en) * | 2004-06-28 | 2006-09-26 | General Electric Company | High density package with wrap around interconnect |
TWI244177B (en) * | 2004-10-21 | 2005-11-21 | Chipmos Technologies Inc | Method for assembling image sensor and structure of the same |
US8411450B2 (en) | 2006-01-25 | 2013-04-02 | Nec Corporation | Electronic device package, module, and electronic device |
JP2007266240A (ja) * | 2006-03-28 | 2007-10-11 | Fujitsu Ltd | 電子装置及びそれを有する電子機器 |
US7888185B2 (en) * | 2006-08-17 | 2011-02-15 | Micron Technology, Inc. | Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device |
JP2008078205A (ja) * | 2006-09-19 | 2008-04-03 | Fujitsu Ltd | 基板組立体及びその製造方法、電子部品組立体及びその製造方法、電子装置 |
US9023511B1 (en) * | 2012-12-18 | 2015-05-05 | Amazon Technologies, Inc. | Systems and methods for removably attaching a battery to a user device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2570628B2 (ja) * | 1994-09-21 | 1997-01-08 | 日本電気株式会社 | 半導体パッケージおよびその製造方法 |
JP3408375B2 (ja) | 1995-06-20 | 2003-05-19 | 新光電気工業株式会社 | 半導体装置 |
US6225688B1 (en) * | 1997-12-11 | 2001-05-01 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
US6262895B1 (en) * | 2000-01-13 | 2001-07-17 | John A. Forthun | Stackable chip package with flex carrier |
-
2002
- 2002-09-10 JP JP2002264030A patent/JP2004103843A/ja active Pending
-
2003
- 2003-01-17 TW TW092100963A patent/TW589722B/zh not_active IP Right Cessation
- 2003-01-17 US US10/345,995 patent/US6730855B2/en not_active Expired - Fee Related
- 2003-05-09 KR KR1020030029302A patent/KR100628872B1/ko not_active IP Right Cessation
- 2003-05-12 CN CNA031238033A patent/CN1482677A/zh active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103997848B (zh) * | 2014-05-30 | 2017-01-11 | 昆山一邦泰汽车零部件制造有限公司 | 一种筒式旋转印刷电路筒 |
Also Published As
Publication number | Publication date |
---|---|
KR100628872B1 (ko) | 2006-09-27 |
JP2004103843A (ja) | 2004-04-02 |
TW589722B (en) | 2004-06-01 |
TW200404355A (en) | 2004-03-16 |
US6730855B2 (en) | 2004-05-04 |
KR20040023483A (ko) | 2004-03-18 |
US20040047135A1 (en) | 2004-03-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1482677A (zh) | 电子元件 | |
CN1199268C (zh) | 半导体装置及其制造方法 | |
CN1183593C (zh) | 半导体装置 | |
CN1151554C (zh) | 半导体器件、其制造方法以及组合型半导体器件 | |
CN1251354C (zh) | 小型天线 | |
CN1062377C (zh) | 多层穿心式电容器阵列 | |
CN1658345A (zh) | 固态电解电容器、传输线器件、它们的制作方法及采用它们的复合电子元件 | |
CN1551712A (zh) | 电子电路的连接结构及其连接方法 | |
CN1901178A (zh) | 继电板及具有继电板的半导体器件 | |
CN1812082A (zh) | 半导体器件 | |
CN1610971A (zh) | 具有垂直连接电容器的电子装置及其制造方法 | |
CN1744313A (zh) | 具有堆叠的半导体元件的半导体装置 | |
CN1945817A (zh) | 半导体器件及其制造方法 | |
CN1197292A (zh) | 一种半导体器件引线框架及引线接合法 | |
CN1700843A (zh) | 基板接合构件和采用其的三维连接结构体 | |
CN1855477A (zh) | 电路装置 | |
CN1641874A (zh) | 多芯片封装 | |
CN1681374A (zh) | 三维装配结构及其制造方法 | |
CN1331490A (zh) | 基板、显示装置、基板与ic芯片的安装及安装键合方法 | |
CN1890802A (zh) | 电源装置的倒转j型引线封装 | |
CN1670580A (zh) | 半导体芯片和利用其的显示设备 | |
CN1577840A (zh) | 半导体器件的堆叠封装 | |
CN1650426A (zh) | 半导体装置及叠层型半导体装置 | |
CN101039387A (zh) | 接收机装置和接收机系统 | |
CN101048030A (zh) | 印刷线路板,印刷线路板半导体封装及含有印刷电路板的电子装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C12 | Rejection of a patent application after its publication | ||
RJ01 | Rejection of invention patent application after publication |