CN1744313A - 具有堆叠的半导体元件的半导体装置 - Google Patents

具有堆叠的半导体元件的半导体装置 Download PDF

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Publication number
CN1744313A
CN1744313A CNA2005100978087A CN200510097808A CN1744313A CN 1744313 A CN1744313 A CN 1744313A CN A2005100978087 A CNA2005100978087 A CN A2005100978087A CN 200510097808 A CN200510097808 A CN 200510097808A CN 1744313 A CN1744313 A CN 1744313A
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Prior art keywords
rewiring
semiconductor
semiconductor element
semiconductor device
depression
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CNA2005100978087A
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CN100448001C (zh
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哈里·黑德勒
罗兰·伊尔西格勒
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明提供一种半导体装置，其可能在半导体装置中堆叠多个半导体元件10、20。以半导体元件的非活动区域16、26互相面对的方式，将半导体元件布置在半导体装置内。在半导体装置内的重新布线61、62连接第一半导体元件10至第二半导体元件20，使用薄膜和/或厚膜技术产生重新布线成为可能。半导体装置在外部框架区域40处被外部接触连接。

Description

具有堆叠的半导体元件的半导体装置
技术领域
本发明涉及一种具有堆叠的半导体元件的半导体装置。还提供一种用于生产本发明的具有堆叠的半导体元件的半导体装置的方法。
背景技术
尽管原理上可适用于任何期望的集成电路，但本发明和本发明基于的问题将参考集成存储电路被说明。
在存储电路技术中，优先布置存储元件，以使单个元件之间具有非常短的重新布线(rewiring)。为了获得在存储元件之间短的信号传播时间和以这种方式实现短的等待时间和高数据传输率，这是有利的。在重新布线中功率损耗和重新布线的电容也被减少。
随着现代半导体技术的集成密度增加，在一个平面中能够实现越来越紧凑的布局。通过在多个平面中将存储元件一个堆叠在另一个上，可进一步增加集成密度。一个通用的方法是在两面上组装电路板。这使得能够将至少两个半导体元件一个布置在另一个上面。多个这种组装的电路板还可被堆叠且使用电缆或插头连接被垂直接触连接。然而，这导致用于接触连接和安装电路板的高成本。显著降低布线长度和寄生电容是不可能的。
另一种方法用于将存储元件直接放置在另一个的上部。在一种布置中，两个半导体壳体(housing)(TSOP壳体)彼此堆叠在另一个的顶部，且外部接触连接(管脚)被互相焊接在一起。另一个变型用于将两个未封装(unhoused)的半导体元件(芯片die)彼此放置在另一个的顶部，以及用于将两个未封装的半导体元件的各个触点内部连线(焊接)至壳体的相同外部触点。然而，这种堆叠的结构高度对于多数应用都太高，另外，只有少数(两到三个)元件可被堆叠。由于重新布线的长度和大量的接触连接，重新布线还具有太高的电容和电感，以至于这种堆叠不适合用于射频应用。再者，重新布线的阻抗不匹配。
另一装置将半导体元件放置在预先制造的壳体中。这个壳体具有朝向其下侧的外接触点和朝向其顶侧的外接触点，这些接触点被分别互相连接。在该生产方法中，接触点被内部连线(wire)至未封装的半导体元件上。通过堆叠壳体，多个半导体元件可因此被垂直集成。其缺点在于，预先制造的壳体必须依据半导体元件的功能被制造和提供。假定因增加的集成密度和/或被扩展的功能范围而改变半导体元件的尺寸，则需要具有新的内部尺寸的新的壳体形状。此外，对于许多应用，他们的结构高度太高，这就是为什么只有少数装置可被堆叠的原因。内部重新布线还具有太高的电感和电容，而不能被适用于射频的应用。
发明内容
本发明的目的是提供一种半导体装置，该装置使堆叠具有改进的重新布线的半导体元件成为可能。本发明还有一个目是限定一种方法，该方法可被用于生产本发明的半导体装置。
依据本发明，使用在权利要求1中限定的半导体装置和在权利要求15中限定的方法实现上述目的。
本发明的装置的优点具体在于：使用薄膜和/或厚膜技术，半导体装置中的各个半导体元件的内部重新布线(rewiring)可以以具有成本效益的方式被生产。另外，本发明的方法能够实现高度平行装配的生产。
在本发明的半导体装置中，第一半导体元件被布置在第一平面中且第二半导体元件被布置在第二平面中。在这种情况下，以一个半导体元件的各个非活动(inactive)侧朝向另一个半导体元件的方式来定位半导体元件。粘接层被引入半导体元件之间。以这种方式形成的堆叠体至少部分地被框架区域围绕，在所述框架区域中设置有连接第一和第二半导体元件的重新布线装置。
用于生产本发明的半导体装置的方法提供下面的步骤：提供临时衬底，具有上述几何结构且包括第一半导体元件、粘接层和第二半导体元件的至少一个堆叠体被逐渐叠置在该临时衬底上。在以这种方式形成的堆叠体之间的边缘区域填充可固化的灌注混合物，然后，临时衬底被从自支撑结构中去除。在下面的步骤中，重新布线装置在框架区域中形成，并且重新布线装置被连接至接触区域。一旦独立半导体装置被制造后，自支撑结构被分为独立的半导体装置。
依据本发明的优选的改进，在框架区域中的重新布线装置由第一和第二重新布线形成。为此，从两侧向框架区域中引入凹陷，以使两个重新布线接触。另一改进仅从一侧引入凹陷，且另一凹陷被构造为具有堆叠体的总高度。优选的改进使用激光将这些凹陷引入框架中。
为了提高半导体装置的机械性能，另一改进用于在半导体元件之外引入缓冲层。所述粘接层可另外具有中心衬底，该中心衬底具有增强的刚度。
本发明的另一改进来自在一个或两个平面中布置多于一个的半导体元件。
附图说明
本发明的多个典型实施例被在附图中示出，且在下面的说明中被更详细地说明。
在附图中：
图1-14显示在生产方法的过程中一个实施例的连续阶段的图解说明；
图15显示所述实施例的平面图的图解说明；
图16-21显示另外的实施例的图解说明；和
图22显示在印刷电路板上安装一个实施例的堆叠体的图解说明。
具体实施方式
在图中，相同附图标记表示相同或功能相同的元件。在图中，为了清楚起见，没有同时显示所有的附图标记。这样，每个图可与前面的图相比较，并采用类似的附图标记。
图1显示在生产方法中一个实施例的第一阶段的图解说明。显示了具有第一表面901的临时衬底1的一部分。临时衬底1优选是一层膜。细分的装置区域A、B被横向地提供。装置区域A、B的边缘900a、900b规定通过该方法实施例生产的半导体装置的尺寸。在各装置区域A、B中，第一半导体元件10a、10b被放置在表面901上。第一半导体元件10a、10b具有衬底区域11，该衬底区域11具有活动侧(active side)15和非活动侧(inactive side)16。第一半导体元件10a、10b的接触连接区域18a、18b位于活动侧15上，芯片连接区域13位于所述接触连接区域中。除了凹陷(depression)14之外的活动侧15经芯片连接区域13被钝化层12覆盖。第一半导体元件10a、10b被放置，使活动侧15朝向衬底被定位。暂时没有被占用的边缘区域40被定位在装置区域A、B的边缘900a、900b和第一半导体元件10a、10b之间。这个边缘区域40，一方面可围绕每个第一半导体元件10a、10b，或可占据第一半导体元件10a、10b的至少一侧。
在图2中，通过进一步的生产步骤，粘接层30被首先涂敷至半导体元件10a、10b的非活动侧。第二半导体元件20a、20b被叠放至这个粘接层30上。在这个实施例中，第一和第二半导体元件10a、20a具有相同的设计。然而，这一点不应当被认为是限制性的。而是，设想还在一个壳体内集成功能不同的半导体元件。第二半导体元件20a、20b的活动面积26及位于其上的接触区域28a、28b被定向，以使他们不朝向第一半导体元件10a、10b。第一和第二半导体元件10a、10b、20a、20b形成两个堆叠体，第一和第二半导体元件被互相背对(背对背)布置。第二半导体元件20a、20b距离装置区域A、B的边缘900a、900b有一段距离。然而，这个距离不一定如图2所示那样对应于第一半导体元件10a、10b和边缘900a、900b之间的距离。
边缘区域40被填充灌注混合物(关于这一点参见图3)。在这种情况下，除其他因素之外(inter alia)，需要另外的步骤(其尚未实施)以确保灌注混合物与具有第二平表面902的第二半导体元件20a、20b平齐地终止。灌注混合物形成自支撑结构2。在随后的步骤中，临时衬底1可因此被从第一表面901去除。图4说明具有平的第一和第二表面901和902的自支撑结构。
在下面描述的图5-13中说明通过在边缘区域40中的接触通孔(via)生产重新布线装置61a、61b、62a、62b，以及使用重新布线装置61a、61b、62a、62b对第一和第二半导体元件10a、10b、20a、20b的重新布线。在这个例子中，使用重新布线装置61a、61b、62a、62b以获得在第一和第二半导体元件10a、10b、20a、20b之间的重新布线尤其重要。
在第一步骤中，电介质51被叠加于第一表面901上。使用已知技术形成电介质51的图案，例如光刻法，使得第一半导体元件10a、10b的接触连接区域18a、18b不被电介质51覆盖(图5)。电介质51还被在框架区域40上面的开口区域131中去除。第一凹陷101a、101b在暴露的开口区域131之下的框架区域40中的灌注混合物中产生。凹陷101a、101b具有底部区域111和侧壁121。底部区域111优选是平的。例如，这一点可使用强激光来实现。凹陷101a、101b的深度在图6中被示出为堆叠体的高度的一半。然而，这仅仅是一种可能的实施例，对第一凹陷的深度没有限制。
在后面的步骤中(图7)，导电层被沉积在刚刚被图案化的第一表面901上。在这个例子中，导电层被沉积在底部区域111、侧壁121、电介质层51和第一接触区域18a、18b上。以这种方式，底部区域111和第一接触区域18a、18b被电连接。在导电层被叠加之前和/或之后光刻图案的步骤被用于在第一表面901上产生重新布线。导电层优选包括铝或铜。为了保护重新布线，例如保护性漆的覆盖层71被涂敷。然而，其不覆盖凹陷101a、101b(图8)。包括导电材料的插头81被引入凹陷101a、101b(图9)。插头81被用于从外部接触连接包括半导体元件10a、20a的堆叠体。
被类似于电介质51在第一表面上形成图案的电介质52被首先叠加(覆盖)至第二表面902上(图10)。第二凹陷102a、102b通过在框架区域40上面的开口区域132被引入框架区域40。以第二开口区域132和第二凹陷102a、102b与第一凹陷101a、101b相对的方式布置第二开口区域132和第二凹陷102a、102b。以第二凹陷102a、102b的底部触及第一凹陷101a、101b的底部的方式，选择第二凹陷102a、102b的深度。因导电薄膜预先叠加至第一凹陷101a、101b，这个导电薄膜的下侧因第二凹陷102a、102b被暴露(关于这一点参见图11)。
随后将第二导电膜向形成图案的第二表面902的叠加(图12)，一方面实现向第二凹陷102a、102b的底部区域112的第二半导体元件20a、20b的接触区域28a、28b的第二重新布线52。同时，由于两个重新布线51、52在两个底部区域111、112的区域中接触，还实现了在第一和第二半导体元件10a、20a之间的重新布线。
随后的步骤包括使用覆盖层72钝化第二重新布线52，并且将第二插头82引入第二凹陷102a、102b(图13)。
在最后步骤之一，自支撑结构2被分为单独的半导体装置3。沿装置区域A、B的边缘900a、900b实施分割。图14说明一个单独的半导体装置3。因为没有必要区分第一和第二装置区域A、B，所以附图标记被缩短至数字。
图15图解说明沿线910的实施例的平面图。插头81被布置在半导体装置的框架区域40内。因为插头81布置在外部框架区域40中所形成的插头81之间的大的距离有利地便于壳体在电路板上的安装和接触连接。插头81的位置仅由产生凹陷101a、101b的步骤限定。从而其他步骤不受影响。因此，仅仅通过改变这些步骤，壳体可有利地适合于外部重新布线。在这个例子中，假如合适，则第二插头82的位置可以被改变。应当注意，有利地，并非所有的第一和第二凹陷都是一个布置在另一个上面，例如因为并非所有的第一半导体元件10a的管脚(pin)都被用于连接第二半导体元件20a，而是期望外部连接至表面。
在另一实施例(未图解说明)中，以平行于重新布线51、52的平行方式沉积屏蔽区域。所述屏蔽区域在前面的和/或后面的步骤中被叠加。在这个例子中，电介质层被附加地叠加在屏蔽区域和重新布线51、52之间。可借助这些附加层匹配重新布线51、52的阻抗。为此，提供了与重新布线61、62平行的且被设定为固定电位(优选为地电势)的导电接地层或接地线。导电层优选包括铝和/或铜。包括具有规定壁厚的电介质的绝缘层使接地层与重新布线61、62绝缘。选择壁厚，以在重新布线和电介质常数的几何要求下，在半导体元件的信号频率处实现典型的50欧姆的理想阻抗。因此，该堆叠体适用于射频应用。由于重新布线不需要任何另外的连接元件以将第一半导体元件连接至第二半导体元件，所以电感和电容是非常低的。反过来，除其他因素外，这对于射频应用是有利的。
图16图解说明本发明的另一实施例。在这个例子中，穿过第一表面901的凹陷103的深度穿透整个灌注混合物。凹陷103的底部113与第二表面902重合。照例，在第一表面上的重新布线61接触在第二表面上的重新布线62。在这个例子中，有利的是不必穿过第二表面902引入第二凹陷。
图17图解说明本发明的另一实施例。缓冲层90被引入，以使其直接地横向邻接第一和第二半导体元件10、20。缓冲层90是柔软的且有利于降低壳体内的机械应力，除其他因素之外，因在温度改变的情况下壳体和半导体元件10、20的膨胀不同，从而产生该应力。
图18图解说明本发明的另一实施例。在这个例子中，两个第三半导体元件30、40被布置在一个平面中。在两个第三半导体元件之间的重新布线63和具有接触通孔(vias)的重新布线62连接第一和第三半导体元件10、30、40。在第三半导体元件30、40之间的中间空间41被有利地填充以灌注混合物。在两个平面中一个或多个半导体元件的任何期望组合的可能性均是可以设想的。
图19图解说明本发明的另一实施例。焊料沉积凸起84被叠加至插头81、82，以便于外部接触连接。在另一个实施例中，焊料沉积凸起仅被叠加在一个表面上，以便以更简单的方式堆叠壳体。然后，在焊炉中加热多个壳体的堆叠体，得到壳体彼此间的垂直重新布线，以及一个壳体的半导体元件和以其他壳体的其它半导体元件之间的垂直重新布线。
通过根据标准在框架中引入凹陷，来确保与现有壳体标准和/或印刷电路板的惯用接触连接图案的兼容性。然后，依据说明的实施例，将焊料沉积凸起84定位在理想的位置。
图20图解说明本发明的另一实施例。因中心衬底33而获得壳体的较高机械强度。为此，刚性材料被优选用于中心衬底。该中心衬底被集成在粘结层30中。中心衬底33的相对侧被两层粘结材料32、34所覆盖，结果中心衬底被永久连接至第一和第二半导体元件10a、20a。在该说明中，在这个实施例中的中心衬底33是连续的层，并且凹陷也将被引入中心衬底33中。
图21图解说明本发明的另一实施例。在这个例子中，预先制造的框架被使用。后者从支柱91以栅格的形式被构造。在支柱之间的空腔对于半导体元件10、20是足够大的。边缘区域的大部分被框架占用。支柱91和半导体元件10、20之间的间隙被填充以灌注混合物。因此，半导体元件被固定至框架10、20。孔106被钻入支柱91，并且被填充以金属，以获得接触通孔。
图22图解说明在印刷电路板上的实施例的安装。下部半导体装置3利用焊料沉积凸起84接触连接至印刷电路板4的接触区域5。上部半导体装置3被堆叠在下部半导体装置3上，并经焊料沉积凸起84电连接至下部半导体装置3的插头82。在半导体装置3之间的可能的粘接层140确保堆叠体的机械稳定性。堆叠的半导体装置3的数量不受限制。
尽管参考优选的具体实施例描述了本发明，但本发明不限制于此，而是可进行多种改变。
具体地，生产方法不限于从第一表面形成图案开始。各个步骤也不必以说明的方式跟在另一个步骤之后。在这种情况下，明显可能的变型对本领域技术人员是显而易见的。
附图标记列表：
A、B    半导体装置区域
1    临时衬底
2    自支撑结构
3    具有堆叠的半导体元件的半导体装置
4    印刷电路板
5    4的接触区域
10、10a、10b    第一半导体元件
20、20a、20b    第二半导体元件
30、40    第三、第四半导体元件
11、21    第一、第二半导体元件的衬底
12、22    第一、第二半导体元件的绝缘层
13、23    第一、第二半导体元件的芯片连接区域
14、24    凹陷
15、25    第一、第二半导体元件的活动侧
16、26    第一、第二半导体元件的非活动侧
17、27    绝缘层12、22的最上部区域
18、18a、18b    第一半导体元件的第一接触连接区
28、28a、28b    第二半导体元件的第二接触连接区
38、48    第三、第四半导体元件的第三、第四接触连接区
30    粘接层
40    框架区域
51、52    第一、第二电介质层
61、61a、61b    第一重新布线
62、62a、62b    第二重新布线
71、72    第一、第二覆盖层
81、82、83    凹陷的第一、第二、第三填充物
84、85    第一、第二焊料沉积凸起
101、101a、101b    第一凹陷
102、102a、102b    第二凹陷
103    第三凹陷
106    垂直连接
111    101、101a、101b的底部区域
112    102、102a、102b的底部区域
121    101、101a、101b的侧壁
122    102、102a、102b的侧壁
131    101、101a、101b的开口区域
132    102、102a、102b的开口区域
132    103的侧壁
900a、900b    半导体装置区域A、B的边缘
901    2的第一表面
902    2的第二表面

Claims (29)

1、一种具有多个堆叠的半导体元件的半导体装置，该半导体装置具有：
a)堆叠体，所述堆叠体具有：
a1)在第一平面中的至少一个第一半导体元件(10)；
a2)在第二平面中的至少一个第二半导体元件(20)，该第二平面与第一平面垂直隔开一段距离；和
a3)粘接层(30)，该粘接层被引入第一和第二半导体元件(10、20)之间；
堆叠体的半导体元件(10a、20a)被定向，以使得第一半导体元件(10)的具有第一接触区域(18)的第一活动区域(15)不面对第二半导体元件(20)，并且第二半导体元件(20)的具有第二接触区域(28)的第二活动区域(25)不面对第一半导体元件(10)；
b)框架区域(40)，该框架区域(40)在至少一侧上横向邻接半导体元件(10a、20a)；
c)重新布线装置(61、62)，该重新布线装置(61、62)被引入框架区域(40)中，并将第一接触连接区域(18)连接至第二接触连接区域(28)。
2、如权利要求1中要求的半导体装置，其中，重新布线装置(61、62)具有：
c1)通过框架区域(40)的第一表面(901)进入框架区域(40)内的第一凹陷(101)，第一重新布线(61)被叠加至第一底部区域
(111)，所述第一重新布线将底部区域连接至第一接触区域(18)；和
c2)通过框架区域(40)的第二表面(902)进入框架区域(40)内的第二凹陷(102)，该第二表面与第一表面(901)相反，第二凹陷(102)的第二底部区域(121)邻接第一底部区域(111)，第二重新布线(62)被叠加至第二底部区域(112)，所述第二重新布线将第二底部区域(112)连接至第二接触区域(28)并且被连接至底部区域(112)中的第一重新布线(61)。
3、如权利要求1中要求的半导体装置，其中重新布线装置(61、62)具有通过框架区域(40)的第一表面(901)进入框架区域(40)内的第三凹陷(103)，该凹陷(103)一直延伸到框架区域(40)的第二表面(902)，所述第二表面(902)与第一表面(901相反，并且，第一重新布线(61)被叠加至第三底部区域(113)，所述第一重新布线将第三底部区域(113)连接至第一接触区域，第二重新布线(62)被叠加至第二表面(902)，所述第二重新布线在第三底部区域(113)中接触第一重新布线(61)且同时被连接至第二接触区域(28)。
4、如前述权利要求中之一要求的半导体装置，其中，缓冲层(90)以横向邻接半导体元件(10、20)的至少一侧的方式被设置在边缘区域(40)中。
5、如前述权利要求中之一要求的半导体装置，其中，至少两个半导体元件(10、20)被布置在第一和/或第二平面内。
6、如权利要求5中要求的半导体装置，其中，在两个第一半导体元件(10)之间和/或在两个第二半导体元件(20)之间的中间空间中填充灌注混合物。
7、如权利要求6中要求的半导体装置，其中，在两个第一半导体元件(10)之间和/或在两个第二半导体元件(20)之间提供重新布线(53)。
8、如前述权利要求中之一要求的半导体装置，其中，粘接层(30)具有中心衬底(33)，以及包括粘接材料的粘接层(32、34)分别被涂敷至中心衬底(33)的相反表面。
9、如权利要求8中要求的半导体装置，其中，中心衬底(33)具有环氧树脂。
10、如前述权利要求中之一要求的半导体装置，其中，第一、第二和/或第三凹陷(101、102、103)中的至少之一被填充以导电材料。
11、如权利要求10中要求的半导体装置，其中，焊料沉积凸起被叠加至被填充的凹陷(81、82、83)中的至少之一上。
12、如前述权利要求中之一要求的半导体装置，其中，预先制造的支撑框架被引入边缘区域(40)中。
13、如权利要求12中要求的半导体装置，其中，重新布线装置(61、62)被引导人所述预先制造的支撑框架中。
14、如前述权利要求中之一要求的半导体装置，其中，重新布线装置(61、62)被阻抗匹配。
15、一种用于生产如权利要求1中所要求的具有堆叠的半导体元件的半导体装置的方法，所述方法具有步骤：
a)提供临时衬底(1)；
b)在临时衬底(1)上形成至少一个包括第一半导体元件(10a、10b)和第二半导体元件(20b、20b)的堆叠体，所述堆叠体被布置在一个或多个横向半导体装置区域(A、B)内，在该半导体装置区域(A、B)内的半导体元件(10a、10b、20b、20b)因边缘区域(40)而在至少一侧与半导体装置部分(A、B)的边缘(900a、900b)隔开一段距离，该步骤具有步骤：
b1)将在半导体装置区域(A、B)内的第一半导体元件(10a、10b)叠加至临时衬底(1)，第一半导体元件(10a、10b)的具有第一接触连接区域(18a、18b)的第一活动侧(15)面向临时衬底(1)；
b2)将粘接层(30)叠加至第一半导体元件(10a、10b)的第一非活动侧(16)，所述第一非活动侧不面向临时衬底(1)；和
b3)将在半导体装置区域(A、B)内的第二半导体元件(20a、20b)叠加至粘接层(30)，每个第二半导体元件(20a、20b)被定向，以使具有第二接触连接区域(28a、28b)的活动侧(25)不面向第一半导体元件(10a、10b)；
c)使用灌注混合物填充边缘区域(40)，从而形成自支撑组件(2)；
d)从自支撑组件(2)去除临时衬底(1)；
e)在边缘区域(40)中且在自支撑组件(2)的第一表面(901)和第二表面(902)上形成重新布线装置(61、62)，以使第一和第二半导体元件(10a、20a)被电连接；和
f)沿半导体装置区域(A、B)的边缘(900a、900b)分成独立半导体装置。
16、如权利要求15中要求的方法，用于形成重新布线装置(61、62)的步骤e)具有下面的步骤：
e1)形成通过自支撑组件(2)的第一表面(2)进入框架区域(40)内的第一垂直凹陷(101a、101b)；
e2)在已通过步骤e1)形成图案的第一表面(901)和第一底部区域(111)上沉积和形成导电膜图案，使得第一重新布线(61a、61b)被形成在第一凹陷(101a、101b)的第一底部区域(111)和第一接触区域(18a、18b)之间；
e3)形成通过自支撑组件(2)的与第一表面(901)相反的第二表面(902)进入框架区域(40)内的第二垂直凹陷(102a、102b)，使得第二垂直凹陷的第二底部区域(112)暴露出具有重新布线(61a、61b)的第一底部区域(111)；和
e4)在已通过步骤e3)形成图案的第二表面(902)和第二底部区域(112)上沉积和构造第二导电膜，使得第二重新布线(62a、62b)被形成在第二底部区域(112)和第二接触区域(18a、18b)之间。
17、如权利要求15中要求的方法，其中，用于形成重新布线装置(61、62)的步骤e)具有下面的步骤：
e1)形成通过自支撑组件(2)的第一表面(901)进入框架区域(40)内的垂直凹陷(103)，底部区域(113)在第二表面(902)的平面中；
e2)在已形成图案的第一表面(901)和底部区域(113)上沉积和形成导电膜图案，使得重新布线(61a、61b)被形成在凹陷(103)的底部区域(113)和第一接触区域(18a、18b)之间；和
e3)在第二表面(902)上沉积和形成第二导电膜图案，使得重新布线(62a、62b)被形成在底部区域(113)和第二接触区域(18a、18b)之间。
18、如权利要求15-17中之一要求的方法，其中，在激光束的作用下产生凹陷(101、102、103)。
19、如权利要求15-18中之一要求的方法，其中，至少两个第一半导体元件(10a、10b)在步骤b1)中被安置在半导体装置部分(A、B)内，和/或至少两个第二半导体元件(20a、20b)在步骤b3)中被安置在半导体装置部分(A、B)内。
20、如权利要求19中要求的方法，具有另外的步骤：使用灌注混合物填充第一半导体元件(10a、10b)之间的第一中间空间，和/或使用灌注混合物填充第二半导体元件(20a、20b)之间的第二中间空间。
21、如权利要求16-20中至少一个要求的方法，具有另外的步骤：在导电膜已被叠加至将被填充的凹陷(101、102、103)之后，使用导电材料填充至少一个凹陷(101、102、103)。
22、如权利要求21中要求的方法，具有另外的步骤：在至少一个被填充的凹陷(81、82、83)上形成焊料沉积凸起。
23、如权利要求15-22中之一要求的方法，具有另外的步骤：叠加第一覆盖层(71)至重新布线(61a、61b)和接触区域(18a、18b)，在第一表面(901)中的第一凹陷(101a、101b)的第一开口区域(131)不被覆盖，和/或叠加第二覆盖层(72)至第二重新布线(62a、62b)和第二接触区域(28a、28b)，在第二表面(902)中的第二凹陷(102a、102b)的第二开口区域(132)不被覆盖。
24、如权利要求15中要求的方法，具有另外的步骤：在临时衬底(1)上布置栅格形式的预先制造的支撑框架，使得支撑框架的栅格支柱(91)位于框架区域(40)内。
25、如权利要求24中要求的方法，其中，用于形成重新布线装置(61、62)的步骤e)具有下面的步骤：
e1)通过在栅格支柱(91)中形成孔且填充栅格支柱中的孔，形成到栅格支柱(91)的导电垂直连接(106)；
e2)在垂直连接(106)和第一及第二接触区域(18a、28a)之间形成重新布线(61a、62a)。
26、如权利要求15-25中之一要求的方法，其中，缓冲层(90)以横向邻接半导体元件(10a、10b、20a、20b)的至少一侧的方式被引人边缘区域(40)中。
27、如权利要求15-26中之一要求的方法，其中，步骤b2)具有步骤：将包括粘接材料的第一粘接层(32)叠加至第一非活动侧(16)；将刚性中心衬底(33)叠加至第一粘接层(32)；以及将第二粘接层叠加至中心衬底。
28、如权利要求15-27中之一要求的方法，其中，用于在通过步骤e)形成重新布线装置(61、62)之前和/或之后，以电介质绝缘层使导电接地层与重新布线装置(61、62绝缘的顺序，形成阻抗匹配的重新布线装置(61、62)、导电接地层和被沉积的电介质绝缘层。
29、如权利要求1-15中之一要求的方法，其中，第二半导体装置被垂直堆叠在第一半导体装置上，使得接触连接装置(84)连接第一半导体装置的第一重新布线装置(61、62)和第二半导体装置的第二重新布线装置(61、62)。
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