SG11201811721UA - Semiconductor packaging structure and method of forming the same - Google Patents
Semiconductor packaging structure and method of forming the sameInfo
- Publication number
- SG11201811721UA SG11201811721UA SG11201811721UA SG11201811721UA SG11201811721UA SG 11201811721U A SG11201811721U A SG 11201811721UA SG 11201811721U A SG11201811721U A SG 11201811721UA SG 11201811721U A SG11201811721U A SG 11201811721UA SG 11201811721U A SG11201811721U A SG 11201811721UA
- Authority
- SG
- Singapore
- Prior art keywords
- vertical stacked
- stacked arrangement
- forming
- mold portion
- international
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
Abstract
INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property :::` , Organization MD HIM 0 11101 HOE 3E1 0 101110110111111 010 MIMI 1111 MI International Bureau (10) International Publication Number 3 (43) International Publication Date .....•\"\" WO 2018/009146 Al 11 January 2018 (11.01.2018) W I PO I PCT (51) International Patent Classification: (74) Agent: VIERING, JENTSCHURA & PARTNER LLP; H01L 23/50 (2006.01) HOlL 23/52 (2006.01) P.O. Box 1088, Rochor Post Office, Rochor Road, Singa- H01L 21/768 (2006.01) HOlL 21/56 (2006.01) pore 911833 (SG). (21) International Application Number: (81) Designated States (unless otherwise indicated, for every PCT/SG2017/050334 kind of national protection available): AE, AG, AL, AM, (22) International Filing Date: AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, 03 July 2017 (03.07.2017) CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, (25) Filing Language: English HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, (26) Publication Language: English KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, (30) Priority Data: OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, 10201605552U 07 July 2016 (07.07.2016) SG SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (71) Applicant: AGENCY FOR SCIENCE, TECHNOLO- GY AND RESEARCH [SG/SG]; 1 Fusionopolis Way, (84) Designated States (unless otherwise indicated, for every #20-10 Connexis North Tower, Singapore 138632 (SG). kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, (72) Inventors: JUNG, Boo Yang; c/o Industry Development, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, — Institute of Microelectronics, 2 Fusionopolis Way, #08-02 TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, Innovis Tower, Singapore 138634 (SG). AU, Jason; c/o EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, Industry Development, Institute of Microelectronics, 2 Fu- MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, sionopolis Way, #08-02 Innovis Tower, Singapore 138634 TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, (SG). KM, ML, MR, NE, SN, TD, TG). = = Title: SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD OF FORMING THE SAME = (54) (57) : Various embodiments may provide a method of forming a semicon- = FIG. 3 344 ductor packaging structure. The method may include forming a plurality of semi- conductor packages, each semiconductor package including a semiconductor die and a mold encapsulation structure. The method may also include arranging the Form a plurality of semiconductor packages \ plurality of semiconductor packages to form a vertical stacked arrangement with a = _ = 1 302 mold portion including a plurality of mold encapsulation structures, the mold por- - Arrange the plurality of semiconductor packages to form a vertical stacked arrangement with a mold portion comprising a plurality of mold encapsulation structures tion extending from a first side to a second side of the vertical stacked arrangement opposite the first side. The method may additionally include forming a first via on the mold portion at the first side of the vertical stacked arrangement, forming a sec- = = = 1 \ 304 and via on the mold portion at the second side of the vertical stacked arrangement, and forming an electrically conductive filled via extending through the mold portion from the first side to the second side of the vertical stacked arrangement. = Form a first via on the mold portion at the first side of the vertical stacked = arrangement after the vertical stacked arrangement is formed = I \ 306 Form a second via on the mold portion at the second side of the vertical — stacked arrangement after forming the 11 first via I \" 308 Form an electrically conductive filled via extending through the mold portion from 11' the first side of the vertical stacked PSI arrangement to the second side of the vertical stacked arrangement C:r 310 © © ,-.... GC 11 © N O [Continued on next page] WO 2018/009146 Al MIDEDIMOMMIONERIONINIMMIEERMOVOIS Published: — with international search report (Art. 21(3))
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG10201605552U | 2016-07-07 | ||
PCT/SG2017/050334 WO2018009146A1 (en) | 2016-07-07 | 2017-07-03 | Semiconductor packaging structure and method of forming the same |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201811721UA true SG11201811721UA (en) | 2019-01-30 |
Family
ID=60913085
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201811721UA SG11201811721UA (en) | 2016-07-07 | 2017-07-03 | Semiconductor packaging structure and method of forming the same |
Country Status (3)
Country | Link |
---|---|
US (1) | US10727207B2 (en) |
SG (1) | SG11201811721UA (en) |
WO (1) | WO2018009146A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112018007691A5 (en) * | 2018-06-05 | 2021-02-18 | Pac Tech - Packaging Technologies Gmbh | Semiconductor chip stack arrangement and semiconductor chip for producing such a semiconductor chip stack arrangement |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06268101A (en) | 1993-03-17 | 1994-09-22 | Hitachi Ltd | Semiconductor device and its manufacture, electronic device, lead frame, and mounting substrate |
DE102004041889B4 (en) * | 2004-08-30 | 2006-06-29 | Infineon Technologies Ag | Semiconductor device with stacked semiconductor devices and method for their production |
JP4551321B2 (en) * | 2005-07-21 | 2010-09-29 | 新光電気工業株式会社 | Electronic component mounting structure and manufacturing method thereof |
US7667338B2 (en) | 2006-08-08 | 2010-02-23 | Lin Paul T | Package with solder-filled via holes in molding layers |
US20080136004A1 (en) | 2006-12-08 | 2008-06-12 | Advanced Chip Engineering Technology Inc. | Multi-chip package structure and method of forming the same |
KR100914977B1 (en) * | 2007-06-18 | 2009-09-02 | 주식회사 하이닉스반도체 | Method for fabricating stack package |
US9293401B2 (en) * | 2008-12-12 | 2016-03-22 | Stats Chippac, Ltd. | Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP) |
US8194411B2 (en) | 2009-03-31 | 2012-06-05 | Hong Kong Applied Science and Technology Research Institute Co. Ltd | Electronic package with stacked modules with channels passing through metal layers of the modules |
US20110186960A1 (en) * | 2010-02-03 | 2011-08-04 | Albert Wu | Techniques and configurations for recessed semiconductor substrates |
US8895440B2 (en) * | 2010-08-06 | 2014-11-25 | Stats Chippac, Ltd. | Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV |
US8698269B2 (en) * | 2011-02-28 | 2014-04-15 | Ibiden Co., Ltd. | Wiring board with built-in imaging device and method for manufacturing same |
KR20140004343A (en) * | 2012-07-02 | 2014-01-13 | 삼성전자주식회사 | Semiconductor deivces and methods of fabricating the same |
-
2017
- 2017-07-03 WO PCT/SG2017/050334 patent/WO2018009146A1/en active Application Filing
- 2017-07-03 SG SG11201811721UA patent/SG11201811721UA/en unknown
- 2017-07-03 US US16/314,485 patent/US10727207B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US10727207B2 (en) | 2020-07-28 |
WO2018009146A1 (en) | 2018-01-11 |
US20190319010A1 (en) | 2019-10-17 |
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