SG11201901931UA - A method of forming nano-patterns on a substrate - Google Patents

A method of forming nano-patterns on a substrate

Info

Publication number
SG11201901931UA
SG11201901931UA SG11201901931UA SG11201901931UA SG11201901931UA SG 11201901931U A SG11201901931U A SG 11201901931UA SG 11201901931U A SG11201901931U A SG 11201901931UA SG 11201901931U A SG11201901931U A SG 11201901931UA SG 11201901931U A SG11201901931U A SG 11201901931UA
Authority
SG
Singapore
Prior art keywords
substrate
forming
nanostructures
international
innovis
Prior art date
Application number
SG11201901931UA
Inventor
Kwang Wei Joel Yang
Zhaogang Dong
Ramón Paniagua-Dominguez
Arseniy Kuznetsov
Yefeng Yu
Original Assignee
Agency Science Tech & Res
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency Science Tech & Res filed Critical Agency Science Tech & Res
Publication of SG11201901931UA publication Critical patent/SG11201901931UA/en

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B1/00—Optical elements characterised by the material of which they are made; Optical coatings for optical elements
    • G02B1/10—Optical coatings produced by application to, or surface treatment of, optical elements
    • G02B1/11—Anti-reflection coatings
    • G02B1/118—Anti-reflection coatings having sub-optical wavelength surface structures designed to provide an enhanced transmittance, e.g. moth-eye structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00031—Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00388—Etch mask forming
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B1/00—Optical elements characterised by the material of which they are made; Optical coatings for optical elements
    • G02B1/10—Optical coatings produced by application to, or surface treatment of, optical elements
    • G02B1/11—Anti-reflection coatings
    • G02B1/113—Anti-reflection coatings using inorganic layer materials only
    • G02B1/115—Multilayers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0147—Film patterning
    • B81C2201/0149—Forming nanoscale microstructures using auto-arranging or self-assembling material

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property :::` , 1#1110111101110101011111 01101001111111111111111111111111111111111111110111111 Organization International Bureau (10) International Publication Number 03 (43) International Publication Date .......\"' WO 2018/044240 Al 08 March 2018 (08.03.2018) WI P0 I P C T (51) International Patent Classification: 2 Fusionopolis Way, #08-03, Innovis, Singapore 138634 B82Y 40/00 (2011.01) GO2B 1/118 (2015.01) (SG). PANIAGUA-DOMINGUEZ, Ramon; c/o Data Storage Institute, 2 Fusionopolis Way, #08-01, Innovis, Sin- (21) International Application Number: PCT/SG2017/050440 gapore 138634 (SG). KUZNETSOV, Arseniy; c/o Data Storage Institute, 2 Fusionopolis Way, #08-01, Innovis, Sin- (22) International Filing Date: gapore 138634 (SG). YU, Yefeng; c/o Data Storage In- 05 September 2017 (05.09.2017) stitute, 2 Fusionopolis Way, #08-01, Innovis, Singapore 138634 (SG). (25) Filing Language: English (26) Publication Language: English (74) Agent: SPRUSON & FERGUSON (ASIA) PTE LTD; P.O. Box 1531, Robinson Road Post Office, Singapore (30) Priority Data: 903031 (SG). 10201607372X 05 September 2016 (05.09.2016) SG (81) Designated States (unless otherwise indicated, for every (71) Applicant: AGENCY FOR SCIENCE, TECHNOLO- kind of national protection available): AE, AG, AL, AM, GY AND RESEARCH [SG/SG]; 1 Fusionopolis Way, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, #20-10 Connexis North Tower, Singapore 138632 (SG). CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FL GB, GD, GE, GH, GM, GT, HN, (72) Inventors: YANG, Kwang Wei Joel; c/o Institute of Ma-HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, terials Research and Engineering, 2 Fusionopolis Way, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, #08-03, Innovis, Singapore 138634 (SG). DONG, Zhao- MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, gang; c/o Institute of Materials Research and Engineering, Title: A METHOD OF FORMING NANO-PATTERNS ON A SUBSTRATE (54) = [Fig. 1] _ = = 0) 1b) = .f 1. 101 = Step .0 = 1 3 .,„ is i = Step 12 (d) (c) = 1 145 107 107 \ \ = N 107 = St Ria 14 N.1 , - \ = 103 = = : This application relates to a method of forming nano-patterns on a substrate comprising the step of forming a plurality of 1— H ..0 (57) 'IlL ' nanostructures on a dielectric substrate, wherein the nanostructures are dimensioned or spaced apart from each other by a scaling factor 0 of the dielectric substrate with reference to a silicon substrate. There is also provided a method of forming a nano-patterned substrate 71' comprising the step of forming a plurality of nanostructures on a dielectric substrate, wherein said dielectric substrate comprises an ei ii- anti-reflectance layer disposed on a base substrate. There is also provided a method of forming a nano-patterned substrate comprising the 1 steps of forming a plurality of nanostructures on a dielectric substrate, wherein the dielectric substrate comprises an anti-reflectance layer 0 --.... disposed on a base substrate, wherein the nanostructures comprise a dielectric material, and wherein the nanostructures are dimensioned Ot or 1-1 spaced apart from each other by a scaling factor of the dielectric material with reference to a silicon substrate. 0 ei O [Continued on next page] WO 2018/044240 Al MIDIOMMMOIREEMOMMOHEEHOEMEMNIE OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — of inventorship (Rule 4.17(iv)) Published: — with international search report (Art. 21(3))
SG11201901931UA 2016-09-05 2017-09-05 A method of forming nano-patterns on a substrate SG11201901931UA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG10201607372X 2016-09-05
PCT/SG2017/050440 WO2018044240A1 (en) 2016-09-05 2017-09-05 A method of forming nano-patterns on a substrate

Publications (1)

Publication Number Publication Date
SG11201901931UA true SG11201901931UA (en) 2019-04-29

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Country Status (3)

Country Link
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SG (2) SG10202101832YA (en)
WO (1) WO2018044240A1 (en)

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SG10201805438TA (en) * 2018-06-25 2020-01-30 Iia Tech Pte Ltd A diamond having nanostructures on one of its surface to generate structural colours and a method of producing thereof
CN109160483B (en) * 2018-08-01 2021-04-27 中国科学院微电子研究所 Nano-pillar sensor, refractive index detection device and method
CN110632063A (en) * 2019-08-15 2019-12-31 中国科学院微电子研究所 Colorimetric sensor and manufacturing method and test system thereof
CN111399087A (en) * 2020-03-25 2020-07-10 武汉大学 Super surface based on medium nano brick array and method for realizing information multiplexing
GB202009640D0 (en) * 2020-06-24 2020-08-05 Ams Sensors Singapore Pte Ltd Optical detection system calibration

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US7170666B2 (en) * 2004-07-27 2007-01-30 Hewlett-Packard Development Company, L.P. Nanostructure antireflection surfaces
CN101093867B (en) * 2006-06-19 2010-12-08 财团法人工业技术研究院 Substrate of vertical column array of nitride in second group
US8514398B2 (en) * 2009-11-10 2013-08-20 The Regents Of The University Of California Sensing devices and techniques using 3-D arrays based on surface plasmon excitations
EP2375452A1 (en) * 2010-04-06 2011-10-12 FOM Institute for Atomic and Moleculair Physics Nanoparticle antireflection layer
KR20130034778A (en) * 2011-09-29 2013-04-08 주식회사 동진쎄미켐 Method of forming fine pattern of semiconductor device using directed self assembly process
US20150377815A1 (en) * 2013-02-20 2015-12-31 Empire Technology Development Llc Nanotube sensors for conducting solutions
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WO2014205238A1 (en) * 2013-06-19 2014-12-24 The Board Of Trustees Of The Leland Stanford Junior University Novel dielectric nano-structure for light trapping in solar cells
JP6365817B2 (en) * 2014-02-17 2018-08-01 セイコーエプソン株式会社 Analytical device and electronic device
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US9537024B2 (en) * 2015-04-30 2017-01-03 The Board Of Trustees Of The Leland Stanford Junior University Metal-dielectric hybrid surfaces as integrated optoelectronic interfaces

Also Published As

Publication number Publication date
US11287551B2 (en) 2022-03-29
WO2018044240A1 (en) 2018-03-08
SG10202101832YA (en) 2021-04-29
US20190187337A1 (en) 2019-06-20

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