CN101093867B - Substrate of vertical column array of nitride in second group - Google Patents

Substrate of vertical column array of nitride in second group Download PDF

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CN101093867B
CN101093867B CN 200610093762 CN200610093762A CN101093867B CN 101093867 B CN101093867 B CN 101093867B CN 200610093762 CN200610093762 CN 200610093762 CN 200610093762 A CN200610093762 A CN 200610093762A CN 101093867 B CN101093867 B CN 101093867B
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vertical
layer
array
substrate
pole
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CN 200610093762
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CN101093867A (en )
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刘文岳
林弘伟
果尚志
沈昌宏
蔡政达
许荣宗
赖志铭
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财团法人工业技术研究院
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Abstract

The substrate of vertical pole array includes substrate, buffer layer, and layer of vertical pole array. The buffer layer is on the substrate. The vertical pole array is on the buffer layer. The vertical pole array is composed of multiple vertical poles stand on the buffer layer.

Description

三族氮化物垂直柱阵列衬底 III nitride substrate, an array of vertical columns

技术领域 FIELD

[0001] 本发明涉及一种三五族半导体衬底,尤其涉及一种三族氮化物垂直柱阵列(vertical-rod array) Mi^o [0001] The present invention relates to a III-V semiconductor substrate, particularly to a vertical group III nitride pillar array (vertical-rod array) Mi ^ o

背景技术 Background technique

[0002] 近年来发光二极管(LED)和激光器(LD)广泛地被应用在市场上,例如以氮化镓(GaN)制成的蓝光与黄色荧光粉组合可以获得白光,不只是在亮度上或用电量方面皆比之前的传统泡光源亮且省电,可以大幅降低用电量。 [0002] In recent years, a light emitting diode (LED) and a laser (LD) is widely used in the market, for example, blue and yellow phosphor combination of gallium nitride (GaN) made of a white light can be obtained, not only in brightness or both light and power, can significantly reduce the power consumption than traditional light bulbs before consumption aspect. 此外,发光二极管的寿命约在数万小时以上,寿命比传统灯泡长。 Further, the life of the light emitting diode above about tens of thousands of hours, longer lifetime than conventional light bulbs.

[0003] 从红光、绿光、蓝光到紫外光的发光二极管在目前市面上主要的器件大多数的产品是由氮化镓系列的化合物为主,但由于氧化铝衬底(sapphire)本身与氮化镓的晶格常数(lattice constant)、热膨胀系数及化学性质的差异,所以在异质衬底(例如是硅衬底、 碳化硅衬底或是氧化铝衬底)上生长的氮化镓层会有许多的线缺陷、位错,且这些位错会随着生长的氮化镓层的厚度增加而延伸,也就是形成穿透位错。 [0003] From the red, green, blue to ultraviolet light emitting diode in the main device currently on the market is dominated by products of most of gallium nitride-based compound, but because of an alumina substrate (Sapphire) itself GaN lattice constant (lattice constant), the difference in thermal expansion coefficient and chemical properties, so that the foreign substrate (e.g. a silicon substrate, a silicon carbide substrate or an alumina substrate) grown on gallium nitride there will be many layers of line defects, dislocation, and dislocations which extend with increasing thickness of the grown gallium nitride layer, is formed threading dislocations. 而此类缺陷影响紫外光的发光二极管及氮化镓系列的激光器性能和使用寿命。 Such defects affect the ultraviolet light emitting diode and gallium nitride laser performance and service life.

[0004] 为了降低穿透位错,常规发展出多种衬底结构。 [0004] In order to reduce the threading dislocation, the development of a variety of conventional substrate structure. 图1绘示为常规一种三族氮化物衬底的剖面简图。 FIG 1 shows a cross-sectional schematic view of a conventional one kind of group III nitride substrate. 请参照图1,衬底100上有一层GaN缓冲层102,而GaN缓冲层102上配置多个阻障图案104,由阻障图案104之间所裸露的GaN缓冲层上生长半导体层106,也就是GaN外延层,并包覆阻障图案104。 Referring to FIG 1, a substrate 100 with a layer of GaN buffer layer 102, a plurality of barrier patterns 104 disposed on the GaN buffer layer 102, a barrier on the exposed pattern 104 between the GaN buffer layer grown semiconductor layer 106, but also It is GaN epitaxial layer, the barrier pattern 104 and coated. 此种衬底结构是利用阻障图案截断部份位错,以使位于阻障图案之上的部份GaN外延层不会产生穿透位错。 Such substrate structure using the barrier pattern is truncated part dislocations, so that part of the GaN epitaxial layer is disposed on the barrier pattern is not generated threading dislocations. 然而,这样生长的GaN外延层仍具有严重的区域性位错现象,也就是在没有阻障图案104位置上的GaN外延层具有分布较为密集的位错产生。 However, such a GaN epitaxial layer grown still have severe regional dislocation phenomenon, i.e. in the absence of the barrier on the GaN epitaxial layer 104 having a densely distributed pattern positions of dislocation generation.

[0005] 图2绘示为常规另一种三族氮化物衬底的剖面简图。 [0005] FIG. 2 shows a cross-sectional schematic view of another conventional Group III nitride substrate. 请参照图2,在衬底200上形成缓冲层202与晶种层204,之后在衬底200中形成穿透缓冲层202与晶种层204的沟槽206,也就是将缓冲层202与晶种层204图案化成条状结构。 Referring to FIG 2, a buffer layer 202 and the seed layer 204 is formed on the substrate 200, penetrating the buffer layer 202 and the seed layer 204 of the trench 206 in the substrate 200 after forming, i.e. the buffer layer 202 and the crystallization seed layer 204 patterned into a stripe structure. 利用异质结构的选择性侧向生长法,称之为PE (Pendeo-epitaxy),使GaN外延层只在条形晶种层204的侧壁上悬空侧向生长,然后覆盖在条状的晶种层204上,用以阻止部份垂直方向的穿透位错。 Lateral growth method using a selective hetero structure, called PE (Pendeo-epitaxy), a GaN epitaxial layer is grown on only the floating side side wall of the stripe-shaped seed layer 204, and then covering the strip-shaped crystal on the seed layer 204 to prevent part of threading dislocations in the vertical direction. 与图1所述的衬底结构所生长的GaN外延层相似,上述悬空生长的GaN外延层同样具有区域性穿透位错的问题,也就是穿透位错现象密集于某些区域产生。 GaN epitaxial layer and substrate structure 1 similar to FIG grown, growth of GaN epitaxial layer of the same floating culture has a problem of threading dislocations, i.e. the threading dislocation density in certain areas to produce the phenomenon. 而并非是生长出无位错现象的GaN外延层。 But not grown dislocation-free GaN epitaxial layer phenomenon.

[0006] 由于使用上述两衬底结构所生长的三族氮化物外延层中都有穿透位错的问题,因此所生长的三族氮化物外延层的厚度受限于位错现象,都小于20微米。 [0006] Since the two substrate structure using the above-described group-III nitride epitaxial grown layer has threading dislocation problems, the thickness of the group III nitride epitaxial layer to be grown is limited by the phenomenon of dislocations, less than 20 microns.

发明内容 SUMMARY

[0007] 本发明的目的在于提供一种三族氮化物垂直柱阵列衬底,可以提供一个位错均勻的半导体层生长环境。 [0007] The object of the present invention to provide a vertical column array of one kind of group III nitride substrate, may provide a uniform semiconductor layer grown wrong bit environment.

4[0008] 本发明的再一目的是提供一种三族氮化物垂直柱阵列衬底,可提供一结构弱化点,有助于半导体层与衬底相互分离。 4 [0008] A further object of the present invention is to provide a vertical column array of group III nitride substrate, may provide a structural weakening point, contribute to the semiconductor layer and the substrate separated from each other.

[0009] 本发明提出一种三族氮化物垂直柱阵列衬底,此三族氮化物垂直柱阵列衬底包括:衬底、缓冲层、垂直柱阵列层与连续性三族氮化物层。 [0009] The present invention provides a vertical column array of one kind of group III nitride substrate, an array of vertical columns of this group III nitride substrate comprising: a substrate, a buffer layer, an array of vertical columns III nitride layer and a continuous layer. 其中,缓冲层位于衬底上方,且垂直柱阵列层位于缓冲层上,而垂直柱阵列层是由多个分别直接立于缓冲层上的垂直柱组成,并且垂直柱之间露出该缓冲层的表面,该垂直柱垂直生长于该衬底的表面,每一该些垂直柱的截面直径为60〜150纳米,该垂直柱阵列层的厚度为10纳米〜5微米,该垂直柱阵列层中该些垂直柱的分布密度在109/Cm2〜1012/cm2之间,该连续性三族氮化物层层位于该垂直柱阵列层上。 Wherein the buffer layer over the substrate, and the vertical column array layer located on the buffer layer, and an array of vertical columns each layer is composed of a plurality of vertical column stand directly on the buffer layer, and the buffer layer is exposed between the vertical column surface, the vertical growth of the vertical column to the surface of the substrate, each of the cross-sectional diameter of the vertical column 60~150 nm, the thickness of the vertical column array layer is 10 nm ~ 5 microns, the layer of the vertical column array distribution density of these vertical column between 109 / Cm2~1012 / cm2, the continuity of the group III nitride layer disposed on the layer of the vertical column array.

[0010] 依照本发明一实施例的三族氮化物垂直柱阵列衬底所述,其中每一垂直柱的材料包括三族氮化物,例如氮化镓。 [0010] In accordance with the vertical column array III nitride substrate according to an embodiment of the present invention, wherein each vertical column comprises a material group III nitride, such as gallium.

[0011] 依照本发明一实施例的三族氮化物垂直柱阵列衬底所述,其中缓冲层是一复合层。 [0011] In accordance with the vertical column array III nitride substrate according to an embodiment of the present invention, wherein the buffer layer is a composite layer. 而复合层的材料包括氮化硅/三族氮化物。 The composite layer include silicon nitride / III nitride. 又此缓冲层的厚度约为1〜60纳米。 The buffer layer has a thickness of about 1~60 nm.

[0012] 依照本发明一实施例的三族氮化物垂直柱阵列衬底所述,其中缓冲层的材料包括氮化硅。 [0012] In accordance with the material of the vertical column array III nitride substrate according to an embodiment of the present invention, wherein the buffer layer comprises silicon nitride. 而缓冲层的厚度约小于10纳米。 While the thickness of the buffer layer is less than about 10 nanometers.

[0013] 本发明另提出一种三族氮化物垂直柱阵列衬底。 [0013] The present invention further provides a vertical column array of one kind of group III nitride substrate. 此三族氮化物垂直柱阵列衬底包括:衬底、氮化硅缓冲层、垂直柱阵列层与氮化镓半导体层。 This vertical column array of group III nitride substrate comprising: a substrate, a silicon nitride buffer layer, and the layer of the vertical column array of gallium nitride semiconductor layer. 其中,垂直柱阵列层位于衬底上,且垂直柱阵列层是由多个分别直接立于该氮化硅缓冲层上的单晶性垂直柱组成,并且单晶性垂直柱之间露出该氮化硅缓冲层的表面。 Wherein the vertical column array layer located on the substrate, and an array of vertical columns each layer is composed of a plurality of single-crystalline silicon nitride stand directly vertical column on the buffer layer, and the single crystal is exposed between the nitrogen of the vertical column the buffer layer is a silicon surface. 该垂直柱垂直生长于该衬底的表面,每一该些垂直柱的截面直径为60〜150纳米,该垂直柱阵列层的厚度为10纳米〜5微米,该垂直柱阵列层中该些垂直柱的分布密度在107cm2〜1012/cm2之间。 The vertical column perpendicular to the growth surface of the substrate, each of the cross-sectional diameter of the vertical column 60~150 nm, the thickness of the vertical column array layer is 10 nm ~ 5 [mu] m, the vertical column array of the plurality of vertical layers distribution density of the column between 107cm2~1012 / cm2. 又氮化镓半导体层为连续性层,位于垂直柱阵列层上。 And gallium nitride semiconductor layer is a continuous layer on the layer of the vertical column array.

[0014] 氮化硅缓冲层的厚度约小于10纳米。 [0014] The thickness of the silicon nitride of the buffer layer is less than about 10 nanometers. 此外,氮化硅缓冲层与垂直柱阵列层之间还包括次缓冲层。 In addition, the silicon nitride further comprising a buffer layer between the buffer sub-layer and the vertical column array layer. 此次缓冲层的厚度约为1〜50纳米,而次缓冲层的材料包括三族氮化物。 The buffer layer has a thickness of about 1~50 nm, and the secondary material comprises a buffer layer group III nitride.

[0015] 依照本发明一实施例的三族氮化物垂直柱阵列衬底所述,其中每一垂直柱的材料包括三族氮化物,例如氮化镓。 [0015] In accordance with the vertical column array III nitride substrate according to an embodiment of the present invention, wherein each vertical column comprises a material group III nitride, such as gallium.

[0016] 在本发明中,藉由缓冲层的表面提供的晶粒排列,因此在缓冲层上可生长垂直衬底表面的垂直柱,且每一垂直柱具有高单晶性,而其中无位错现象。 [0016] In the present invention, the grain alignment provided by the surface of the buffer layer, so the buffer layer can be grown on a vertical column perpendicular to the substrate surface, and each vertical column having a high crystal property, and wherein no bits wrong phenomenon. 而在之后在垂直柱阵列层上形成半导体层时,由于垂直柱阵列层的表面提供无位错现象的外延环境,因此在垂直柱阵列层上外延形成的半导体层具有极低的位错密度,且所形成的半导体层的厚度较大。 And when, after forming a semiconductor layer in a vertical column array layer, since the surface layer of the vertical column array providing the dislocation-free epitaxial environmental phenomena, so the semiconductor layer in a vertical column array epitaxial layer formed having a low dislocation density, and the thickness of the semiconductor layer to be formed is large. 此外,藉由垂直柱状层作为结构上的弱化点,半导体层可以轻易的经由垂直柱状层与衬底相互剥离。 Further, with the vertical pillar layer as a point of weakness in the structure, the semiconductor layer can be easily peeled off each other via a vertical pillar layer and the substrate.

[0017] 为让本发明的上述和其它目的、特征和优点能更明显易懂,下文特举优选实施例, 并配合附图,作详细说明如下。 [0017] In order to make the above and other objects, features and advantages of the present invention can be more fully understood by reading the following preferred embodiments accompanied with figures are described in detail below.

附图说明 BRIEF DESCRIPTION

[0018] 图1绘示为常规一种三族氮化物衬底的剖面简图。 [0018] FIG. 1 shows a schematic cross-sectional view of a conventional one kind of group III nitride substrate.

[0019] 图2绘示为常规另一种三族氮化物衬底的剖面简图。 [0019] FIG. 2 shows a cross-sectional schematic view of another conventional Group III nitride substrate.

[0020] 图3A绘示为根据本发明一实施例的三族氮化物垂直柱阵列衬底的剖面简图。 [0020] FIG 3A shows a cross-sectional schematic view of a vertical column array substrate according to an embodiment of the group III nitride of the present invention. [0021] 图3B绘示为根据本发明另一实施例的三族氮化物垂直柱阵列衬底的剖面简图。 [0021] FIG 3B illustrates a cross-sectional schematic view of a vertical column array substrate according to another embodiment of the group III nitride of the present invention.

[0022] 图4绘示为根据本发明一实施例的三族氮化物垂直柱阵列衬底中一垂直柱的剖面简图。 [0022] FIG. 4 shows a schematic cross-sectional view according to a vertical column array of group III nitride substrate with an embodiment of the present invention, in a vertical column.

[0023] 简单符号说明 [0023] Simple Description of Symbols

[0024] 100,200,300 :衬底 [0024] 100,200,300: a substrate

[0025] 102、202、302 :缓冲层 [0025] 102, 202: buffer layer

[0026] 104:阻障图案 [0026] 104: barrier pattern

[0027] 204 :晶种层 [0027] 204: seed layer

[0028] 206 :沟槽 [0028] 206: trench

[0029] 106,208,308 :半导体层 [0029] 106,208,308: a semiconductor layer

[0030] 302a :主缓冲层 [0030] 302a: main buffer layer

[0031] 304:次缓冲层 [0031] 304: secondary buffer layer

[0032] 306 :垂直柱阵列层 [0032] 306: vertical column array layer

[0033] 306a :垂直柱 [0033] 306a: vertical column

具体实施方式 detailed description

[0034] 图3A绘示为根据本发明一实施例的三族氮化物垂直柱阵列衬底的剖面简图。 [0034] FIG 3A shows a cross-sectional schematic view of a vertical column array substrate according to an embodiment of the group III nitride of the present invention.

[0035] 请参照图3A,本发明的三族氮化物垂直柱阵列衬底包括衬底300、缓冲层302、垂直柱阵列层306与半导体层308。 [0035] Referring to Figure 3A, a vertical column array of group III nitride substrate according to the present invention includes a substrate 300, a buffer layer 302, the vertical column array layer 306 and the semiconductor layer 308. 其中衬底300的材料例如是硅、碳化硅或是氧化铝。 Wherein the substrate material 300 such as silicon carbide or alumina. 而缓冲层302则位于衬底300上,且缓冲层302的材料包括氮化物,例如是氮化硅或是三族氮化硅,例如铟氮化硅。 And the buffer layer 302 located on the substrate 300, and the buffer material 302 comprises a nitride layer, for example silicon nitride or group-III nitride, such as indium nitride. 缓冲层302的厚度约小于10纳米。 The thickness of the buffer layer 302 is less than about 10 nanometers.

[0036] 另外,缓冲层302也可以具有复合层结构,也就是缓冲层302还可以是以主缓冲层302a与位于主缓冲层302a上的次缓冲层304组成的复合层结构(如图3B所示)。 [0036] Further, the buffer layer 302 may have a multilayer structure, that is, the buffer layer 302 may also be in the main buffer layer 302a and the composite layer structure is located on the secondary buffer layer 304 composed of a main buffer layer 302a (FIG. 3B shown). 请参照图3B,主缓冲层302a的材料包括氮化物,例如是氮化硅或是三族氮化硅,例如铟氮化硅。 Referring to Figure 3B, the main material of the buffer layer 302a comprises a nitride, e.g., silicon nitride or group-III nitride, such as indium nitride. 而次缓冲层304的材料包括三族氮化物。 And the buffer material layer 304 comprises a sub-group III nitride. 其中三族元素包括铝、镓、铟、铊。 Wherein the Group III elements include aluminum, gallium, indium, thallium. 优选地,上述次缓冲层304的材料为氮化铟。 Preferably, the secondary material of the buffer layer 304 is indium nitride. 而缓冲层302a与次缓冲层304可以组合成复合层结构的缓冲层。 And the buffer layer 302a and the secondary buffer layer 304 may be combined into a composite layer structure of the buffer layer. 也就是图3B所绘示的本发明的另一实施例的三族氮化物垂直柱阵列衬底具有复合层结构的缓冲层302时,本发明的此具有复合层结构的缓冲层302可以是氮化硅/三族氮化物复合层。 A vertical column array of group III nitride substrate which is another embodiment of the invention depicted in FIG. 3B illustrates an embodiment of a composite layer structure having a buffer layer 302 of this invention having a buffer layer 302 may be a composite layer structure of nitrogen silicon / III nitride compound layer. 另外,上述图3B中的缓冲层302a的厚度约小于10纳米,且上述次缓冲层304 的厚度约为1〜50纳米。 Further, the thickness of the buffer layer 302a in FIG. 3B above about less than 10 nanometers, and the thickness of the secondary buffer layer 304 of about 1~50 nm. 换句话说,如图3B所示,当缓冲层具有主缓冲层302a与次缓冲层304的复合层结构时,缓冲层302 (复合层结构的缓冲层)的厚度约为1〜60纳米。 In other words, as shown in FIG 3B, when the buffer layer has a composite layer structure of the primary layer 304. The buffer layer 302a with the secondary buffer, the thickness of the buffer layer 302 (buffer layer of the multilayer structure) of about 1~60 nm.

[0037] 再者,上述的垂直柱阵列层306则位于上述的缓冲层302上方,且垂直柱阵列层306是由多个立于衬底300上方的垂直柱306a组成。 [0037] Further, the above-mentioned vertical column array layer 306 positioned above the buffer layer 302, and a vertical column array layer 306 is composed of a plurality of vertical columns 300 remain above the substrate 306a composed. 每一垂直柱的材料例如是三族氮化物。 Each vertical column of material, for example, group III nitride. 而优选地,垂直柱的材料例如是氮化镓。 Preferably the material, for example gallium nitride vertical column. 又,垂直柱阵列层306的厚度约为10纳米〜 5微米。 Further, the thickness of the vertical column array layer 306 of about 10 nanometers to about 5 microns. 值得注意的是,垂直柱阵列层306中垂直柱306a在衬底300上方的分布密度约在109/cm2 〜1012/cm2 之间。 It is noted that the vertical column 306 vertical column array layer 306a over the substrate 300 in the distribution density of between about 109 / cm2 ~1012 / cm2.

[0038] 另外,请参照图4,图4绘示为根据本发明一实施例的三族氮化物垂直柱阵列衬底中一垂直柱的剖面简图,其中单一垂直柱306a的截面直径d约为60〜150纳米。 [0038] Further, referring to FIG 4, FIG. 4 shows a schematic cross-sectional view according to a vertical column array of group III nitride substrate with an embodiment of the present invention, in a vertical column, wherein the cross-sectional diameter d of about a single vertical column 306a is 60~150 nm. 值得注意的是,每一垂直柱306a具有高单晶性,且无位错(dislocation)现象产生。 Notably, each vertical column 306a having high crystal property, and the dislocation-free (dislocations) phenomenon. [0039] 再者,本发明的三族氮化物垂直柱阵列衬底,还包括半导体层308,此半导体层308的厚度约大于20微米。 [0039] Further, the vertical column array of group III nitride substrate according to the present invention further includes a semiconductor layer 308, the thickness of the semiconductor layer 308 of greater than about 20 microns. 半导体层308的材料包括三族氮化物,优选的是氮化镓。 Material of the semiconductor layer 308 includes group III nitride, preferably gallium nitride. 此半导体层308也即是外延层,可作为后续形成三族氮化物器件的基底。 The semiconductor layer 308 is an epitaxial layer, i.e., may be formed as a base subsequent III nitride devices.

[0040] 藉由缓冲层或是复合层结构缓冲层的表面提供的晶粒排列,因此可在缓冲层上形成一根根垂直衬底表面的垂直柱,且每一垂直柱具有高单晶性,而其中无位错现象。 [0040] surface of the buffer layer of grains arranged by multilayer structure or the buffer layer is provided, thus forming a vertical column may be perpendicular to the substrate surface of a root on the buffer layer, and each vertical column having a high crystal property , of which no dislocation phenomenon. 而在之后在垂直柱阵列层上形成半导体层时,由于垂直柱阵列层的表面提供无位错现象的外延环境,因此在垂直柱阵列层上外延形成的半导体层具有分布均勻的位错。 When and after forming a semiconductor layer in a vertical column array layer, since the surface layer of the vertical column array providing the dislocation-free epitaxial environmental phenomena, so the semiconductor layer in a vertical column array epitaxial layer is formed to have a uniform distribution of dislocations.

[0041] 另外,由于本发明的三族氮化物垂直柱阵列衬底,在衬底与半导体层之间具有垂直柱阵列层的结构,因此垂直柱阵列层可以作为异质晶格之间应力释出点,所以在垂直柱状层上所形成的半导体层的厚度较大。 [0041] Further, since the vertical column array of group III nitride substrate according to the present invention, the semiconductor layer between the substrate and the layer having an array of vertical column structure, and therefore the vertical pillar array as a stress release layer may be between heterogeneous lattice point out, the thickness of the semiconductor layer in a vertical pillar layer formed larger. 此外,藉由垂直柱状层作为结构上的弱化点,半导体层可以轻易地经由垂直柱状层与衬底相互剥离。 Further, with the vertical pillar layer as a point of weakness in the structure, the semiconductor layer can be easily peeled off each other via a vertical pillar layer and the substrate.

[0042] 虽然本发明已以优选实施例披露如上,然其并非用以限定本发明,任何本领域的技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视权利要求所界定者为准。 [0042] While the present invention has been described above disclosure of preferred embodiments, they are not intended to limit the present invention, anyone skilled in the art, without departing from the spirit and scope of the present invention, may make various modifications and variations , Therefore, the scope of the invention as defined by the following claims and their equivalents.

Claims (15)

  1. 一种三族氮化物垂直柱阵列衬底,包括:衬底;缓冲层,位于该衬底上方;垂直柱阵列层,位于该缓冲层上,其中该垂直柱阵列层是由多个分别直接立于该缓冲层上的垂直柱组成,并且垂直柱之间露出该缓冲层的表面,该垂直柱垂直生长于该衬底的表面,每一该些垂直柱的截面直径为60~150纳米,该垂直柱阵列层的厚度为10纳米~5微米,该垂直柱阵列层中该些垂直柱的分布密度在109/cm2~1012/cm2之间;以及连续性三族氮化物层,位于该垂直柱阵列层上。 One kind of vertical column array of group III nitride substrate, comprising: a substrate; a buffer layer disposed over the substrate; vertical column array layer disposed on the buffer layer, wherein the layers are each vertical column array directly established by a plurality of in the vertical column on the buffer layer, and the surface of the buffer layer is exposed between the vertical pillars, the vertical growth of the vertical column to the surface of the substrate, each of the cross-sectional diameter of the vertical post 60 to 150 nanometers, the layer thickness of the vertical array of column 10 nanometers to about 5 microns, the density distribution in the vertical column array of these layers between the vertical column 109 / cm2 ~ 1012 / cm2; and continuity III nitride layer on the vertical column layer on the array.
  2. 2.如权利要求1所述的三族氮化物垂直柱阵列衬底,其中每一该些垂直柱的材料包括三族氮化物。 2. The vertical column array of group III nitride substrate according to claim 1, wherein the material of each of the vertical column comprises a group III nitride.
  3. 3.如权利要求1所述的三族氮化物垂直柱阵列衬底,其中每一该些垂直柱的材料包括氮化镓。 Vertical column array of group III nitride substrate according to claim 1, wherein the material of each of the vertical column comprises gallium nitride.
  4. 4.如权利要求1所述的三族氮化物垂直柱阵列衬底,其中该缓冲层是复合层。 4. The vertical column array of group III nitride substrate according to claim 1, wherein the buffer layer is a composite layer.
  5. 5.如权利要求4所述的三族氮化物垂直柱阵列衬底,其中该复合层的材料包括氮化硅/三族氮化物。 5. The vertical column array of group III nitride substrate according to claim 4, wherein the composite material comprises a layer of silicon nitride / III nitride.
  6. 6.如权利要求4所述的三族氮化物垂直柱阵列衬底,其中该缓冲层的厚度为1〜60纳米。 Vertical column array of group III nitride substrate as claimed in claim 4, wherein the buffer layer has a thickness of 1~60 nm.
  7. 7.如权利要求1所述的三族氮化物垂直柱阵列衬底,其中该缓冲层的材料包括氮化娃。 7. The vertical column array of group III nitride substrate according to claim 1, wherein the buffer layer comprises a material baby nitride.
  8. 8.如权利要求7所述的三族氮化物垂直柱阵列衬底,其中该缓冲层的厚度小于10纳米。 III nitride substrate according to the vertical column array as claimed in claim 7, wherein the buffer layer has a thickness less than 10 nanometers.
  9. 9. 一种三族氮化物垂直柱阵列衬底,包括: 衬底;氮化硅缓冲层,位于该衬底上方;垂直柱阵列层,位于该氮化硅缓冲层上,其中该垂直柱阵列层是由多个分别直接立于该氮化硅缓冲层上的单晶性垂直柱组成,并且单晶性垂直柱之间露出该氮化硅缓冲层的表面,该垂直柱垂直生长于该衬底的表面,每一该些垂直柱的截面直径为60〜150纳米,该垂直柱阵列层的厚度为10纳米〜5微米,该垂直柱阵列层中该些垂直柱的分布密度在IO9/ cm2〜1012/cm2之间;以及氮化镓半导体层为连续性层,位于该垂直柱阵列层上。 A vertical column array of group III nitride substrate, comprising: a substrate; a buffer layer of silicon nitride located over the substrate; vertical column array layer disposed on the nitride buffer layer, wherein the vertical column array each layer is a direct stand plurality of vertical column of single crystal silicon nitride on the buffer layer, the surface of the silicon nitride and the buffer layer of single crystal is exposed between the vertical posts, the vertical growth of the vertical column to the liner the bottom surface of the cross-sectional diameter of each of the vertical column of 60~150 nm, the thickness of the vertical column array layer is 10 nm ~ 5 microns, a density distribution in the vertical column array layer in the plurality of vertical posts IO9 / cm2 between ~1012 / cm2; and a gallium nitride semiconductor layer is a continuous layer on the layer of the vertical column array.
  10. 10.如权利要求9所述的三族氮化物垂直柱阵列衬底,其中该氮化硅缓冲层的厚度小于10纳米。 10. The vertical column array of group III nitride substrate according to claim 9, wherein the nitride buffer layer has a thickness less than 10 nanometers.
  11. 11.如权利要求9所述的三族氮化物垂直柱阵列衬底,其中该氮化硅缓冲层与该垂直柱阵列层之间还包括次缓冲层。 11. The vertical column array of group III nitride substrate according to claim 9, wherein the nitride buffer layer between the array of vertical columns and further comprising a sub-layer buffer layer.
  12. 12.如权利要求11所述的三族氮化物垂直柱阵列衬底,其中该次缓冲层的厚度为1〜 50纳米。 12. The vertical column array of group III nitride substrate according to claim 11, wherein the thickness of the secondary buffer layer is 1 ~ 50 nanometers.
  13. 13.如权利要求11所述的三族氮化物垂直柱阵列衬底,其中该次缓冲层的材料包括三族氮化物。 13. The vertical column array of group III nitride substrate according to claim 11, wherein the secondary material comprises a buffer layer group III nitride.
  14. 14.如权利要求9所述的三族氮化物垂直柱阵列衬底,其中每一该些垂直柱的材料包括三族氮化物。 A vertical column array of group III nitride substrate as claimed in claim 9, wherein the material of each of the vertical column comprises a group III nitride.
  15. 15.如权利要求9所述的三族氮化物垂直柱阵列衬底,其中每一该些垂直柱的材料包括氮化镓。 A vertical column array of group III nitride substrate as claimed in claim 9, wherein the material of each of the vertical column comprises gallium nitride.
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