SG11201809883QA - Fan-out wafer-level packaging method and the package produced thereof - Google Patents

Fan-out wafer-level packaging method and the package produced thereof

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Publication number
SG11201809883QA
SG11201809883QA SG11201809883QA SG11201809883QA SG11201809883QA SG 11201809883Q A SG11201809883Q A SG 11201809883QA SG 11201809883Q A SG11201809883Q A SG 11201809883QA SG 11201809883Q A SG11201809883Q A SG 11201809883QA SG 11201809883Q A SG11201809883Q A SG 11201809883QA
Authority
SG
Singapore
Prior art keywords
international
silicon substrate
layer
forming
drains
Prior art date
Application number
SG11201809883QA
Inventor
Masaya Kawano
Ka Fai Chang
Original Assignee
Agency Science Tech & Res
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Agency Science Tech & Res filed Critical Agency Science Tech & Res
Publication of SG11201809883QA publication Critical patent/SG11201809883QA/en

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property - C.-- - .` Organization 1111111111111111111111111111111111111111111111111111111111111111111111111111 International Bureau (10) International Publication Number 03 (43) International Publication Date .../ WO 2017/196257 Al 16 November 2017 (16.11.2017) WIPO I PCT (51) International Patent Classification: (74) Agent: SPRUSON & FERGUSON (ASIA) PTE LTD; HO1L 23/498 (2006.01) HO1L 21/768 (2006.01) P.O. Box 1531, Robinson Road Post Office, Singapore HO1L 23/538 (2006.01) 903031 (SG). (21) International Application Number: (81) Designated States (unless otherwise indicated, for every PCT/SG2017/050229 kind of national protection available): AE, AG, AL, AM, (22) International Filing Date: AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, 27 April 2017 (27.04.2017) CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, (25) Filing Language: English HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, (26) Publication Language: English KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, (30) Priority Data: PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, 10201603724V 10 May 2016 (10.05.2016) SG SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (71) Applicant: AGENCY FOR SCIENCE, TECHNOLO- GY AND RESEARCH [SG/SG]; 1 Fusionopolis Way, (84) Designated States (unless otherwise indicated, for every #20-10 Connexis North Tower, Singapore 138632 (SG). kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, — (72) Inventors: KAWANO, Masaya; c/o Industry Develop- UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, ment, Institute of Microelectronics, 2 Fusionopolis Way, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, #08-02 Innovis Tower, Singapore 138634 (SG). CHANG, EE, ES, FL FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, Ka Fai; c/o Industry Development, Institute Microelec- of MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, - = tronics, 2 Fusionopolis Way, #08-02 Innovis Tower, Singa- TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, pore 138634 (SG). KM, ML, MR, NE, SN, TD, TG). Title: FAN-OUT WAFER-LEVEL PACKAGING METHOD AND THE PACKAGE PRODUCED THEREOF (54) (57) : A fan-out wafer-level packaging method and the package produced thereof are 4 354 r = provided in the present application. The method comprises steps including: providing a silicon 2 substrate layer having a first thickness; forming one or more active/passive devices comprising at 302 356 least sources and drains and one or more diffusion layers adjoining the sources and drains, wherein forming the one or more active/passive devices comprises forming the sources and the drains in a front-end-of-line (FEOL) layer on a first side of the silicon substrate layer while forming the one = or more diffusion layers at locations in the silicon substrate layer adjoining the sources and the =360 drains; forming a redistribution layer (RDL) over the FEOL layer by copper damascene formation =356 _ of multiple metallization layers for connecting the one or more active/passive devices to the one or = 362 more IC dies when the one or more IC dies are mounted on a side of the RDL opposite the FEOL = = layer; thinning the silicon substrate layer to a second thickness to form a thinned silicon substrate, 308 the thinned silicon substrate comprising at least the one or more diffusion layers; and patterning .364 the thinned silicon substrate to form one or more silicon regions, each of the one or more silicon = 310 1 regions comprising the one or more diffusion layers. 366 _ 312 J J 1-1 X 370 IN in ei 314 J __ 372 V::+ ,1 316 - 1 \ ... r . ' Il FIG. 3 © ei O [Continued on next page] WO 2017/196257 Al MIDEDIMOMMIDIRMEMEEMIMMIDENHINVOIMIE Declarations under Rule 4.17: — of inventorship (Rule 4.17(iv)) Published: — with international search report (Art. 21(3))
SG11201809883QA 2016-05-10 2017-04-27 Fan-out wafer-level packaging method and the package produced thereof SG11201809883QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG10201603724V 2016-05-10
PCT/SG2017/050229 WO2017196257A1 (en) 2016-05-10 2017-04-27 Fan-out wafer-level packaging method and the package produced thereof

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Publication Number Publication Date
SG11201809883QA true SG11201809883QA (en) 2018-12-28

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US (1) US10720339B2 (en)
SG (1) SG11201809883QA (en)
WO (1) WO2017196257A1 (en)

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CN109037080A (en) * 2018-06-29 2018-12-18 华进半导体封装先导技术研发中心有限公司 A kind of integrated IPD encapsulating structure and its manufacturing method
CN109671700A (en) * 2018-12-26 2019-04-23 华进半导体封装先导技术研发中心有限公司 A kind of fan-out-type chip-packaging structure and its manufacturing method
US10818651B2 (en) * 2019-01-29 2020-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure
US11049844B2 (en) 2019-07-01 2021-06-29 International Business Machines Corporation Semiconductor wafer having trenches with varied dimensions for multi-chip modules
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