CN1890802A - 电源装置的倒转j型引线封装 - Google Patents

电源装置的倒转j型引线封装 Download PDF

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Publication number
CN1890802A
CN1890802A CNA2004800365819A CN200480036581A CN1890802A CN 1890802 A CN1890802 A CN 1890802A CN A2004800365819 A CNA2004800365819 A CN A2004800365819A CN 200480036581 A CN200480036581 A CN 200480036581A CN 1890802 A CN1890802 A CN 1890802A
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lead
semiconductor packages
source
drain
chip
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CN100442482C (zh
Inventor
罗礼雄
安荷叭剌
雷燮光
何约瑟
张复兴
张晓天
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Chongqing Wanguo Semiconductor Technology Co ltd
Alpha and Omega Semiconductor Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

一半导体封装，包含一导线架，其具有若干条引线以及一导线架平台，该导线架平台具有与其耦接的一芯片，该若干条引线的至少其中之一具有一外部部件，其相对于该封装的底面向上倾斜；金属连接物，用以将芯片连接至该若干条引线；以及一树脂本体，用以封装该芯片、金属连接物以及一部分的导线架。

Description

电源装置的倒转J型引线封装
发明背景
本发明是关于半导体装置，更特别的是本发明是关于半导体装置的封装，并且更特别的是本发明是关于电源装置的倒转J型引线封装。
伴随着印刷电路板技术的进步，电源半导体封装已经从贯穿孔演变到表面安装封装。表面安装封装包含一导线架，在其上安装了一个半导体装置。半导体装置与一部分的导线架是封装于一树脂材料中。在一具有引线的封装结构中，引线端是延伸出树脂本体外部，并且包含用以提供半导体装置与引线端之间的接合线连结的打线平台。
在封装半导体装置时的主要考虑包含高热量散逸、低寄生电感、半导体装置与电路环境之间的低电阻、由热循环以及热震荡/疲劳所代表的良好可靠度，以及电路板空间的最少消耗。
根据说明并参照图1，为一种公知的半导体封装1，其包含一导线架7，其具有耦接至一芯片8的一导线架平台10。一部分的导线架7可塑造于一树脂本体2中。在这个实施例中，芯片8是为一金属氧化物半导体场效晶体管，并且导线架7包含一源极端18、一栅极端26以及一漏极端11。导线架7的源极端18包含若干条在树脂本体2外部的分离源极导线架引线18a以及若干个接合线6所连结的分离内部源极打线区16。漏极端11包含若干条连接至导线架平台10的分离漏极导线架引线11a。栅极端26是连接至内部栅极打线区20，其中该内部栅极打线区20是通过接合线28连接至一栅极平台17。
图2是图例显示另一种公知的半导体封装4，其包含一导线架9。在这个实施例中，如图1所示的若干个分离源极打线区16会被连结起来形成一单一源极打线区30取代由接合线6连结至芯片8。与图1的实施例相似，分离源极导线架引线18a与分离漏极导线架引线11a是为由树脂本体2发散出去的分离狭窄金属条带，并且其适合插入在一印刷电路板上的相同插座位置。
与图1的实施例相似的是，导线架9具有设置于其上的芯片8，并且在芯片8的周围提供了一边界框架(其宽度通常为狭窄)。再者，栅极端26的打线区20是经由接合线28耦接至形成于最邻近角落上的栅极17。在公知技术的实施例中，源极与栅极打线区16，30与27是分别共享芯片8的相同左侧。同样地，源极导线架引线18a与接合线28是由相同的左侧发散出去。
请参见图3，其显示具有一导线架(通常标示为13)的公知双芯片半导体封装(通常标示为7)的上视图。双芯片封装7具有一对芯片50a与50b，其安装在导线架平台52上且塑造于一树脂本体中。一第一源极端18a包含分布于沿着第一芯片50a的左侧上的一第一源极端打线区16a。第一源极端打线区16a是经由接合线6a连接至第一芯片50a。一第一栅极端26a包含一第一栅极打线区20a，其是共享第一芯片50a的左侧并且经由接合线28a连接至第一芯片50a。若干个第一漏极端11a是耦接至导线架平台52。
一第二源极端18b包含沿着第二芯片50b的左侧分布的一第二源极端打线区16b。第二源极端打线区16b是通过接合线6b连接至第二芯片50b。一第二栅极端26b包含一第二栅极打线区20b，其是共享第二芯片50b的左侧并且通过接合线28b连接至第二芯片50b。若干个第二漏极端11b是耦接至导线架平台52。
请参照图4，其是显示如半导体封装1的一公知半导体封装的截面图。如图所示，芯片8具有与接合线6耦接的一上表面22。芯片8是由公知材质12耦接至导线架平台10。如图所示，引线18与11是以公知J型结构来形成。这种结构有需要部分的印刷电路线路区为引线18与11占用的缺点。
一种公知具有引线的封装是公开于美国专利6,291,262号，标题为″表面安装TO-220封装和其制造过程″。其所公开的封装包含在塑造的外壳内部弯曲并且在将外壳塑造于导线架周围前便已经形成的引线。此种弯曲是位于封装本体内部以将封装本体上的机械应力最小化。虽然延伸出封装外部的引线部分得以减少，引线依然会消耗宝贵的线路板空间。
另一种公知的具有引线的封装是公开于美国专利6,211,462号，标题为″集成电路的底感应是数电源封装″。该封装包含一平坦导线架，其具有向上形成而与导线架平台非常接近的内部引线。外部引线平直并且延伸到封装边缘之外，以便达成并检验一印刷电路板的良好焊接连接。
一种用于解决有引线封装的公知方案包含无引线封装。一种此等无引线封装是公开于美国专利4,682,207号，标题为″包括无引线封装的半导体装置以及安装该无引线封装的底盘″。每个无引线封装包含储放于其内的一半导体芯片以及形成于其四侧边及其下表面的若干个电极。无引线封装会具有焊接点的检验难以进行的缺点。
由此可看出，在技术领域中持续存在着一种对于可将电路板空间最小化的半导体封装的需求。较佳者，此种半导体封装亦使得焊接点能够容易检验，同时容许增加芯片尺寸、缩减封装高度以及增强热阻特性。最后，较佳者此种半导体具备较小的导通电阻与电感。
发明内容
根据本发明提供的一种技术方案，一半导体封装包含一导线架，其具有若干条引线以及一导线架平台，该导线架平台包含与其耦接的一芯片，该若干条引线的至少其中之一相对于该封装的一表面形成一锐角；金属连接物，其将芯片耦接至该若干条引线；以及一树脂本体，其是封装该芯片、金属连接物以及至少一部分的导线架。
根据本发明提供的另一种技术方案，一半导体封装包含一导线架，其具有若干条引线以及一对导线架平台，每个导线架平台包含与其耦接的一芯片，该若干条引线的至少其中之一具有相对于该封装的底面向上倾斜的一外部部件；金属连接物，其将每个芯片耦接至该若干条引线；以及一树脂本体，其是封装该芯片、金属连接物以及至少一部分的导线架。
根据本发明提供的又一种技术方案，一半导体封装，用来储纳一电子装置，其包含一导线架，其具有若干条引线以及一导线架平台，该导线架平台包含与其耦接的一电子装置，该若干条引线具有相对于该封装的底面向上倾斜的一外部部件；金属连接物，其将电子装置耦接至该若干条引线；以及一树脂本体，其是封装该电子装置、金属连接物以及至少一部分的导线架。
本发明的这些和其它的特征、封装及优点，将可参照下列的附图、说明书和权利要求书而变得更容易了解。
附图说明
图1是为公知的一种半导体封装的上视图；
图2是为另一种公知的半导体封装的上视图；
图3是为公知双芯片半导体封装的上视图；
图4是为公知半导体封装的截面图；
图5A是为根据本发明的半导体封装的上视图；
图5B是为根据本发明的图5A的半导体封装的截面图；
图5C是为根据本发明的图5A的半导体封装的底面图；
图6A是为根据本发明的一种替代实施例的半导体封装的上视图；
图6B是为根据本发明的图6A的半导体封装的截面图；
图6C是为根据本发明的图6A的半导体封装的底面图；
图7A是为根据本发明的一种替代实施例的半导体封装的上视图；
图7B是为根据本发明的图7A的半导体封装的截面图；
图7C是为根据本发明的图7A的半导体封装的底面图；
图8A是为根据本发明的一种替代实施例的半导体封装的上视图；
图8B是为根据本发明的图8A的半导体封装的截面图；
图8C是为根据本发明的图8A的半导体封装的底面图；
图9A是为根据本发明的一种替代实施例的半导体封装的上视图；
图9B是为根据本发明的图9A的半导体封装的截面图；
图9C是为根据本发明的图9A的半导体封装的底面图；
图10A是为根据本发明的一种替代实施例的半导体封装的上视图；
图10B是为根据本发明的图10A的半导体封装的截面图；
图10C是为根据本发明的图10A的半导体封装的底面图；
图11A是为根据本发明的一种替代实施例的半导体封装的上视图；
图11B是为根据本发明的图11A的半导体封装的截面图；
图11C是为根据本发明的图11A的半导体封装的底面图；
图12A是为根据本发明的一种替代实施例的半导体封装的上视图；
图12B是为根据本发明的图12A的半导体封装的截面图；
图12C是为根据本发明的图12A的半导体封装的底面图；
图13A是为根据本发明的一种替代实施例的半导体封装的上视图；
图13B是为根据本发明的图13A的半导体封装的截面图；
图13C是为根据本发明的图13A的半导体封装的底面图；
图14A是为根据本发明的一种替代实施例的半导体封装的上视图；
图14B是为根据本发明的图14A的半导体封装的上视图；
图14C是为根据本发明的图14A的半导体封装的截面图；
图15A是为根据本发明的一种替代实施例的半导体封装的上视图；
图15B是为根据本发明的图15A的半导体封装的截面图；
图15C是为根据本发明的图15A的半导体封装的底面图；
图16是为根据本发明的一种替代实施例的半导体封装的截面图；
图17是为根据本发明的一种替代实施例的半导体封装的截面图；
图18是为根据本发明的一种替代实施例的半导体封装的截面图；
图19是为根据本发明的一种替代实施例的半导体封装的截面图；
图20是为根据本发明的一种替代实施例的半导体封装的截面图；
图21是为根据本发明的一种替代实施例的半导体封装的截面图；
图22是为根据本发明的一种替代实施例的半导体封装的截面图；
图23是为根据本发明的一种替代实施例的半导体封装的截面图；
图24是为根据本发明的一种替代实施例的半导体封装的上视图；以及
图25是为根据本发明的一种替代实施例的半导体封装的上视图。
具体实施方式
下面的详细说明是为实施本发明的最佳模式。这里的说明并不欲被视为具有限制性的意味，而仅是为了解说本发明的概略原理的目的而提出，其是因为本发明的范围是由权利要求书所定义。
本发明的目的是提供一种可将电路板空间的消耗最小化的半导体封装。本发明将半导体封装的外部引线安排为一种倒转J型引线结构，该半导体封装亦可使得焊接点能够容易检验，同时容许增加芯片尺寸、缩减封装高度以及增强热阻特性，且该半导体封装亦具备较小的导通电阻与电感。
请参照图5A，一半导体封装(通常标示为101)包含一导线架(通常标示为122)，其具有耦接至一芯片100的一导线架平台112。部分的导线架122可塑造于一树脂本体120中。导线架122包含一源极引线118A、一栅极引线118B以及一漏极引线118C。源极引线118可设置树脂本体120的外部并且耦接至一内部源极打线区110，其中该内部源极打线区110可接着由金属连接物116耦接至一装置源极(未显示)。如现有技术所熟知，金属连接物116可包含接合线、迭片与胶带。漏极引线118C可连接至导线架平台112。栅极引线118B可连接至一内部栅极打线区126，其中该内部栅极打线区126可接着经由金属连接物130连接至一栅极平台127。
在倒转J型结构中，源极引线118A、栅极引线118B以及漏极引线118C如图5B与图5C所示可向上弯曲。如图所示，源极引线118A、栅极引线118B以及漏极引线118C是相对于半导体封装101的底面117向上倾斜，而形成与其相对的锐角且探出树脂本体120之外，使得源极引线118A、栅极引线118B以及漏极引线118C的底部部件119A，119B以及119C大体上是分别设置在底面117的平面上。有利的是，焊锡会输送至源极引线118A、栅极引线118B以及漏极引线118C，这样使得焊接点容易检验，并且增加源极引线118A、栅极引线118B以及漏极引线118C的接触面积。
请特别参照图5B，一凹口106可形成于漏极引线118C中使得树脂能够掌握住导线架122。凹口106可适用于减少在封装后漏极引线118C的弯曲过程中导线架平台112的压力。
将会为熟悉该项技术者所明了的是，半导体封装101的结构可由减少由源极引线118A、栅极引线118B以及漏极引线118C所消耗的印刷电路线路区部份，来提供增加的芯片尺寸。再者，又参照图5C，导线架平台112的底部部件114可曝露于半导体封装101之外，由此提供增强的热阻特性给半导体封装101。
半导体封装101另外由缩减打线区110与126的高度并且从而分别缩减金属连接物116与130的长度来提供较小的导通电阻。打线区110与126的高度缩减亦缩减了半导体封装101的整体高度。再者，又参照图5A，源极引线118A可熔接成一体，以方便使用最少数目的金属连接物116，以此减少导通电阻与源极电感。
请参照图6A、图6B以及图6C，其是显示本发明的一第二替代实施例103。一芯片150是连结至一导线架平台158。源极引线118A与栅极引线118B可如图5A、图5B以及图5C的实施例一样设置，并且再加上一条额外的源极引线118C。漏极引线118D是连接至导线架平台112的相对侧边。这个实施例可有利地提供额外的源极金属连接物116以减少导通电阻与源极电感。
本发明的一第三替代实施例105显示于图7A、图7B以及图7C。相对于第二替代实施例103，源极引线118A与118C可由金属连接物168联结于芯片150两端。这个实施例可有利地由减少芯片表面170上的金属延伸电阻来提供较小的导通电阻。
请参照图8A、图8B以及图8C，其是显示本发明的一第四替代实施例202。半导体封装202可实现为一常见的漏极双芯片装置。一对装置200与200A是连结至一导线架平台158。装置200可包含一源极引线118A、一栅极引线118B以及共享的漏极引线118D。装置200A可包含一源极引线118E、一栅极引线118F以及共享的漏极引线118D。
本发明的一第五替代实施例204显示于图9A、图9B以及图9C。半导体封装204可实现为一绝缘双芯片装置。在此提供一对导线架平台208，每个导线架平台是由此连接至装置200与200A。装置200可包含一源极引线118A、一栅极引线118B以及漏极引线118G。装置200A可包含一源极引线118E、一栅极引线118F以及漏极引线118H。
本发明的一第六替代实施例210显示于图10A、图10B以及图10C。半导体封装210包含符合公知具有引线的半导体封装的线路区的一导线架布局，同时提供本发明的倒转J型引线的优点。半导体封装210可包含一导线架212，其包含与一芯片耦接的一导线架平台112。一部分的导线架212可塑造于一树脂本体120中。导线架212可包含若干条源极引线118J、一栅极引线118B以及若干条漏极引线118K。源极引线118J可设置于树脂本体120外部且耦接至内部源极打线区260，其中该内部源极打线区260可接着由金属连接物116耦接至一装置源极(未显示)。漏极引线118K可连接至导线架平台112。栅极引线118B可连接至内部栅极打线区126，其中该内部栅极打线区126可接着由金属连接物130连接至一栅极平台127。如图10A、图10B以及图10C所示，源极引线118J、栅极引线118B以及漏极引线118K在倒转J型结构中是向上弯曲。
请参照图11A、图11B以及图11C，其是显示本发明的一第七替代实施例214。如图5A、图5B以及图5C的实施例一般，半导体封装214包含一导线架216，其包含与一芯片100耦接的一导线架平台308。一部分的导线架216可塑造于一树脂本体120中。导线架216可包含一源极引线118A、一栅极引线118B以及一漏极引线118C。源极引线118A可设置于树脂本体120外部且耦接至内部源极打线区110，其中该内部源极打线区110可接着由金属连接物116耦接至一装置源极(未显示)。漏极引线118C可连接至导线架平台308。栅极引线118B可连接至内部栅极打线区126，其中该内部栅极打线区126可接着由金属连接物130连接至一栅极平台127。源极引线118A、栅极引线118B以及漏极引线118C是以倒转J型结构来排列。
请特别参照图11b与图11C，导线架平台308的底部部件309可封装于树脂本体120内。源极引线118A、栅极引线118B以及漏极引线118C的底部部件119A，119B以及119C大体上是分别设置在封装底面311的平面上。有利的是，由于倒转J型源极引线118A、栅极引线118B以及漏极引线118C的引线尺寸缩减之故，半导体封装214便能够容纳较大的芯片尺寸。此外，半导体封装214使得焊接点能够容易检验。
本发明的一第八替代实施例218是显示于图12A、图12B以及图12C。半导体封装218包含一导线架220，其具有导线架平台360与360A。一第一装置350可连结至导线架平台360而一第二装置350A可连结至导线架平台360A。一部分的导线架220可塑造于一树脂本体120中。导线架220包含一第一源极引线118L、一第一栅极引线118B以及一第一漏极引线118N。第一源极引线118L可设置于树脂本体120外部且耦接至内部源极打线区260，其中该内部源极打线区260可接着由金属连接物116耦接至一装置350的源极(未显示)。第一漏极引线118N可连接至导线架平台360。第一栅极引线118B可连接至内部栅极打线区126，其中该内部栅极打线区126可接着由金属连接物130连接至一栅极平台127。
导线架220可包含一第二源极引线118M、一第二栅极引线118Q以及一第二漏极引线118P。第二源极引线118M可设置于树脂本体120外部且耦接至内部源极打线区260，其中该内部源极打线区260可接着由金属连接物116耦接至一装置350的源极(未显示)。第二漏极引线118P可连接至导线架平台360A。第二栅极引线118Q可连接至内部栅极打线区126A，其中该内部栅极打线区126A可接着由金属连接物130A连接至一栅极平台127A。
如图12B以及图12C所示，第一与第二源极引线118L与118M、第一与第二栅极引线118B与118Q以及第一与第二漏极引线118N与118P在倒转J型结构中是向上弯曲。有利的是，焊锡会输送至第一与第二源极引线118L与118M、第一与第二栅极引线118B与118Q以及第一与第二漏极引线118N与118P，以便以此使得焊接点容易检验，并且增加第一与第二源极引线118L与118M、第一与第二闸极引线118B与118Q以及第一与第二漏极引线118N与118P的接触面积。
请参照图13A、图13B以及图13C，其是显示本发明的一第九替代实施例222。半导体封装222通常包含一导线架224，其具有与一芯片500耦接的一导线架平台512。一部分的导线架224可塑造于一树脂本体520中。导线架224包含一源极端518A、一栅极端518B以及一漏极端518C。导线架224的源极端518A可耦接至金属连接物516所连结的内部源极打线区510。漏极端518C可连接至导线架平台512。栅极端518B可连接至内部栅极打线区526，其中该内部栅极打线区126可接着由金属连接物530连接至一栅极平台528。
请特别参照图13B与图13C，半导体封装222包含具有公知J型引线结构的源极端518A与闸极端518B。漏极端518C包含倒转J型结构。
本发明的第十替代实施例显示于图14A中，其包含一半导体封装226。半导体封装226包含一导线架228，其具有与一芯片600耦接的一导线架平台612。一部分的导线架228可塑造于一树脂本体620中。若干条源极引线618A可耦接至内部源极打线平台660，其中该内部源极打线平台660可接着由金属连接物616耦接至一装置的源极(未显示)。一栅极引线618B可耦接至内部栅极打线平台626，其是由金属连接物630耦接至一栅极平台627。若干条漏极引线618C可耦接至导线架平台612。如图所示，源极引线618A与闸极引线618B是以公知J型引线结构来排列。漏极导线618C是以倒转J型引线结构来排列。
请参照图14B，其是显示本发明的一第十一替代实施例230。半导体封装230包含一导线架232，其具有导线架平台760与760A。一第一装置750可连结至导线架平台760而一第二装置750A可连结至导线架平台760A。一部分的导线架232可塑造于一树脂本体720中。导线架232包含一第一源极引线718A、一第一栅极引线718B以及一第一漏极引线718C。第一源极引线718A可设置于树脂本体120外部且耦接至内部源极打线区761，其中该内部源极打线区761可接着由金属连接物716耦接至一装置750的源极(未显示)。第一漏极引线718C可连接至导线架平台760。第一栅极引线718B可连接至内部栅极打线区726，其中该内部栅极打线区726可接着由金属连接物730连接至一栅极平台727。
导线架232可包含一第二源极引线718D、一第二栅极引线718E以及一第二漏极引线7118F。第二源极引线718D可设置于树脂本体720外部且耦接至内部源极打线区761A，其中该内部源极打线区761A可接着由金属连接物716耦接至一装置750A的源极(未显示)。第二漏极引线718F可连接至导线架平台760A。第二栅极引线718E可连接至内部栅极打线区726A，其中该内部栅极打线区726A可接着由金属连接物730A连接至一栅极平台727A。
请参照图14C，所示的源极引线718A与718D以与门极引线718B与718E是以习知J型引线结构来排列。漏极引线718C与718F是以倒转J型引线结构来排列。
请参照图15A、图15B以及图15C，其是显示本发明的一第十二替代实施例234。半导体封装234可实现为一常见的漏极双芯片装置。一对装置800与800A是连结至一导线架平台858。装置800可包含一源极引线818A、一栅极引线818B以及共享的漏极引线818D。装置800A可包含一源极引线818E、一栅极引线818F以及共享的漏极引线818D。与图8A、图8B以及图8C所示的第四替代实施例相较，第十二替代实施例中的共享漏极引线818D是沿着在半导体封装234上与源极引线818A与818E以与门极引线818B与818F同侧的边缘来设置。
本发明的一第十三实施例900是显示于图16。半导体封装900可包含一导线架平台956，其具有设置于其上的一半导体装置950。一树脂本体920可封装一部分的导线架(未显示)。若干个焊接区911可用来将导线架的引线部908连接至一装置区。在一纵向装置的情况下，该装置区是为一源极区；而在一横向装置的情况下，该装置区是为一漏极区。一引线918A可耦接至引线部908。一栅极引线918B可耦接至一栅极引线平台910，其中该栅极引线平台910接着可由金属连接物916耦接至一装置栅极区。栅极引线918B与引线918A是以倒转J型引线结构来排列。
请参照图17，其是显示本发明的一第十四替代实施例930。半导体封装930可包含一导线架平台958，其具有设置于其上的一半导体装置950。一树脂本体920可封装一部分的导线架(未显示)。焊接区911可用来将导线架的引线部908连接至一装置区。在一纵向装置的情况下，该装置区是为一源极区；而在一横向装置的情况下，该装置区是为一漏极区。一引线918A可耦接至引线部908。一闸极引线918C可耦接至一栅极引线平台910，其中该栅极引线平台910接着可由金属连接物916耦接至一装置栅极区。引线918A是以倒转J型引线结构来排列。栅极引线918C是以习知J型引线结构来排列。
本发明的一第十五实施例940是显示于图18。半导体封装940可包含一导线架平台958，其具有设置于其上的一半导体装置950。一树脂本体920可封装一部分的导线架(未显示)。焊接区910可用来将导线架的引线部908连接至一装置区，以及将引线部922连接至另一个装置区。在一纵向装置的情况下，该装置区是为一源极区；而在一横向装置的情况下，该装置区是为一漏极区。引线918A可耦接至引线部908并且引线918D可耦接至引线部922。引线918A与918D是以倒转J型引线结构来排列。
请参照图19，其是显示本发明的一第十六替代实施例944。半导体封装944可包含一导线架平台958，其具有设置于其上的一半导体装置950。一树脂本体920可封装一部分的导线架(未显示)。焊接区910可用来将导线架的引线部908连接至一装置区，以及将引线部922连接至另一个装置区。在一纵向装置的情况下，该装置区是为一源极区；而在一横向装置的情况下，该装置区是为一漏极区。引线918A可耦接至引线部908并且引线918E可耦接至引线部922。引线918A与918D是以倒转J型引线结构来排列。引线918E是以公知J型引线结构来排列。
本发明的一第十七实施例1000是显示于图20。半导体封装1000可包含一导线架平台958，其具有设置于其上的一半导体装置950。一树脂本体920可封装一部分的导线架(未显示)。焊接区910可用来将导线架的引线部932连接至一装置区。在一纵向装置的情况下，该装置区是为一源极区；而在一横向装置的情况下，该装置区是为一漏极区。引线918F可耦接至引线部932。引线918F是以倒转J型引线结构来排列。
请参照图21，其是显示本发明的一第十八替代实施例1100。半导体封装1100可包含一导线架平台958，其具有设置于其上的一半导体装置950。一树脂本体920可封装一部分的导线架(未显示)。焊接区910可用来将导线架的引线部932连接至一装置区。在一纵向装置的情况下，该装置区是为一源极区；而在一横向装置的情况下，该装置区是为一漏极区。引线918G与918H是耦接至引线部932。引线918H是以倒转J型引线结构来排列。引线918G是以公知的J型引线结构来排列。
本发明的一第十九实施例1200是显示于图22。半导体封装1200可包含一集成电路1004，其所有的端点(未显示)皆设置于一相同的硅表面上。一第一焊接区1012是将一第一集成电路端耦接至一导线架部1024，其中该导线架部1024是接着耦接至一引线1018A。一第二焊接区1010是将一第二集成电路端耦接至一导线架部1022，其中该导线架部1022是接着耦接至一引线1018B。导线架部1024与1022的底面1025与1023是各别经由一树脂本体1020曝露在外。引线1018A与1018B是以倒转J型结构来排列。
请参照图23，其是显示本发明的一第二十替代实施例1210。半导体封装1210可包含一集成电路1004，其所有的端点(未显示)皆设置于一相同的硅表面上。一第一焊接区1012是将一第一集成电路端耦接至一导线架部1024，其中该导线架部1024是接着耦接至一引线1018A。一第二焊接区1010是将一第二集成电路端耦接至一导线架部1022，其中该导线架部1022是接着耦接至一引线1018B。导线架部1024与1022的底面1025与1023是各别封装于树脂本体1020中。引线1018A与1018B是以倒转J型结构来排列。
本发明的一第二十一实施例1300是显示于图24。半导体封装1300包含一导线架1302，其具有一第一导线架平台1312与一第二导线架平台1314。一第一半导体装置1380是安装于第一导线架平台1312上，而一第二半导体装置1380A是安装于第二导线架平台1314上。第一装置1380是耦接至一第一源极引线1318A、一第一栅极引线1318B以及一第一漏极引线1318C。第二装置1380A是耦接至一第二源极引线1318D、一第二栅极引线1318E以及一第二漏极引线1318F。如图所示，第一漏极引线1318C是设置于第一源极引线1318A与第一栅极引线1318B的相对边。如图所示，第二漏极引线1318F是设置于第二源极引线1318D与第二栅极引线1318E的相对边。第一与第二漏极引线1318C与1318F是设置于半导体封装1300的相同侧边。所有引线1318A，1318B，1318C，1318D，1318E以及1318F是以倒转J型引线结构来排列。
请继续参照图24，第一与第二导线架平台1312及1314包含若干个互锁结构1350。互锁结构1350可用来将装置1380与1380A之大型结构在金属连接物1316的连结期间保持原位。
本发明的一第二十二实施例1400是显示于图25。半导体封装1400包含一导线架1402，其具有一第一导线架平台1412与一第二导线架平台1414。一第一半导体装置1480是安装于第一导线架平台1412上，而一第二半导体装置1480A是安装于第二导线架平台1414上。第一装置1480是耦接至一第一源极引线1418A、一第一栅极引线1418B以及一第一漏极引线1418C。第二装置1480A是耦接至一第二源极引线1418E、一第二栅极引线1418F以及一第二漏极引线1418D。如图所示，第一漏极引线1418C是设置于第一源极引线1418A与第一栅极引线1418B的相对边。如图所示，第二漏极引线1418F是设置于第二源极引线1418D与第二栅极引线1418E的相对边。第一与第二漏极引线1418C与1418F是设置于半导体封装1400的相对侧边。所有引线1418A，1418B，1418C，1418D，1418E以及1418F是以倒转J型引线结构来排列。
请继续参照图25，第一与第二导线架平台1412及1414包含若干个互锁结构1450。互锁结构1450可用来将装置1480与1480A之大型结构在金属连接物1416的连结期间保持原位。
当然须了解的是，前述关于本发明的较佳实施例的说明以及修饰，可在不脱离权利要求书所定义之本发明的精神以及范围的情况下达成。

Claims (26)

1.一种半导体封装，其包含：
一导线架，具有若干条引线以及一导线架平台，该导线架平台具有与其耦接的一芯片，该若干条引线的至少其中之一相对于该封装的一平面形成一锐角；
金属连接物，用以将该芯片连接至该若干条引线；
一树脂本体，用以封装该芯片、该金属连接物以及至少一部分的导线架。
2.如权利要求1所述的半导体封装，其特征在于，该导线架平台是由该封装的一底面而曝露在外。
3.如权利要求1所述的半导体封装，其特征在于，该芯片包含一集成电路。
4.如权利要求3所述的半导体封装，其特征在于，该若干条引线的至少其中之一是由一无限焊接连结耦接至一集成电路。
5.如权利要求3所述的半导体封装，其特征在于，该积体电路包含一场效晶体管装置。
6.如权利要求5所述的半导体封装，其特征在于，该若干条引线包含一源极引线、一栅极引线以及一漏极引线，其是分别耦接该场效晶体管装置的源极区、栅极区以及漏极区。
7.如权利要求6所述的半导体封装，其特征在于，该源极引线包含一熔接的实体部分。
8.如权利要求6所述的半导体封装，其特征在于，该源极引线与栅极引线是在半导体封装上位于漏极引线的相对侧边上互相紧邻处设置。
9.如权利要求6所述的半导体封装，其特征在于，该源极引线是耦接至设置于树脂本体内部的一源极打线区，并且该栅极引线是耦接至设置于树脂本体内部的一栅极打线区，该源极打线区与栅极打线区是设置在位于比该场效晶体管装置的一上表面要来的低的一平面上，并且该金属连接物是相当地短且将源极引线连接至源极打线区并将栅极引线连接至栅极打线区。
10.如权利要求6所述的半导体封装，其特征在于，该源极引线、栅极引线以及漏极引线的每一个皆包含一外部部件，其是相对于该封装的底面向上倾斜。
11.如权利要求6所述的半导体封装，其特征在于，该漏极引线包含一外部部件，其是相对于该封装的底面向上倾斜。
12.如权利要求6所述的半导体封装，其特征在于，该漏极引线包含一凹口。
13.如权利要求6所述的半导体封装，还包含耦接至场效晶体管装置的源极区的一第二源极引线，以及耦接至场效晶体管装置的漏极区的一第二漏极引线。
14.如权利要求13所述的半导体封装，其特征在于，该漏极引线是互相相对设置，并且该源极引线是互相相对设置。
15.如权利要求13所述的半导体封装，其特征在于，其中该源极引线是联结至场效晶体管装置的源极区。
16.如权利要求1所述的半导体封装，还包含耦接至该导线架平台的一第二芯片。
17.如权利要求16所述的半导体封装，其特征在于，该芯片包含场效晶体管装置，并且每个场效晶体管装置是共享一条漏极引线。
18.如权利要求17所述的半导体封装，其特征在于，该漏极引线包含一对互相相对设置的漏极引线。
19.如权利要求16所述的半导体封装，其特征在于，该导线架平台是经由该封装的底面而曝露在外。
20.一种半导体封装，其包含：
一导线架，具有若干条引线以及一对导线架平台，每个导线架平台具有与其耦接的一芯片，该若干条引线的至少其中之一具有一外部部件，其相对于该封装的一底面向上倾斜；
金属连接物，用以将该每个芯片连接至该若干条引线；
一树脂本体，用以封装该芯片、该金属连接物以及至少一部分的导线架。
21.如权利要求20所述的半导体封装，其特征在于，每个导线架平台还包含若干个互锁结构。
22.如权利要求20所述的半导体封装，其特征在于，该芯片是为场效晶体管装置，并且每个场效晶体管装置共享一漏极引线。
23.如权利要求22所述的半导体封装，其特征在于，该漏极引线包含两条互相相对设置的引线。
24.如权利要求22所述的半导体封装，其特征在于，该漏极引线包含两条互相邻接设置的引线。
25.如权利要求201所述的半导体封装，其特征在于，该导线架平台是经由该封装的底面而曝露在外。
26.一种用来储放一电子装置的半导体封装，其包含：
一导线架，具有若干条引线以及一导线架平台，该导线架平台具有与其耦接的电子装置，该若干条引线具有一外部部件，其相对于该封装的一底面向上倾斜；
金属连接物，用以将该电子装置连接至该若干条引线；
一树脂本体，用以封装该电子装置、该金属连接物以及至少一部分的导线架。
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Denomination of invention: Inverted J-lead package for power devices

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Granted publication date: 20081210

Pledgee: Chongqing Branch of China Development Bank

Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd.

Registration number: Y2019500000007

PE01 Entry into force of the registration of the contract for pledge of patent right
PC01 Cancellation of the registration of the contract for pledge of patent right

Granted publication date: 20081210

Pledgee: Chongqing Branch of China Development Bank

Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd.

Registration number: Y2019500000007