CN106024731B - 一种用钝化层防止表面溢塑封料的封装件 - Google Patents
一种用钝化层防止表面溢塑封料的封装件 Download PDFInfo
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- CN106024731B CN106024731B CN201610466591.0A CN201610466591A CN106024731B CN 106024731 B CN106024731 B CN 106024731B CN 201610466591 A CN201610466591 A CN 201610466591A CN 106024731 B CN106024731 B CN 106024731B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Laminated Bodies (AREA)
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Abstract
本发明公开了一种用钝化层防止表面溢塑封料的封装件,封装件包括芯片、打线区域、芯片感应区、焊线、塑封体,芯片整体呈方体结构,一面的四个角均为四分之一圆柱空间的打线区域,剩余部分构成类十字结构,在类十字结构中部为一个方形的芯片感应区,芯片感应区的上部有圆型钝化层覆盖,塑封体包裹芯片、钝化层、焊线。该发明具有防止表面溢塑封料的特点。
Description
技术领域
本发明涉及集成电路领域,具体是一种用钝化层防止表面溢塑封料的封装件。
背景技术
现有技术中,芯片整体呈正方体结构,一面的四个角切割至均为四分之一圆柱空间的打线区域,剩余部分构成类十字结构;在类十字结构中部为一个方形的芯片感应区。在制造过程中,film与芯片表面很难做到紧密贴合,类十字结构的四个方向均有可能存在缝隙而导致溢塑封料。
发明内容
为了解决上述现有技术存在的问题,本发明公开了一种用钝化层防止表面溢塑封料的封装件,通过钝化层的建造,可有效防止表面溢塑封料的问题。
一种用钝化层防止表面溢塑封料的封装件,封装件包括芯片、打线区域、芯片感应区、焊线、塑封体,芯片整体呈方体结构,一面的四个角均为四分之一圆柱空间的打线区域,剩余部分构成类十字结构,在类十字结构中部为一个方形的芯片感应区,芯片感应区的上部有圆型钝化层覆盖,塑封体包裹芯片、钝化层、焊线。钝化层有效阻 挡表面溢塑封料。
所述钝化层中间镂空,露出芯片感应区。表面溢塑封料溢入镂空空间。
附图说明
图1为带钝化层封装件主视图;
图2为带钝化层封装件俯视图;
图3为镂空钝化层封装件主视图;
图4为镂空钝化层封装件俯视图。
图中,1为芯片、2为打线区域、3为芯片感应区、4为焊线、5为塑封体、6为钝化层
具体实施方式
一种用钝化层防止表面溢塑封料的封装件,封装件包括芯片1、打线区域2、芯片感应区3、焊线4、塑封体5,芯片1整体呈方体结构,一面的四个角均为四分之一圆柱空间的打线区域2,剩余部分构成类十字结构,在类十字结构中部为一个方形的芯片感应区3,芯片感应区3的上部有圆型钝化层6覆盖,塑封体5包裹芯片1、钝化层6、焊线4。所述钝化层6中间镂空,露出芯片感应区3。
Claims (2)
1.一种用钝化层防止表面溢塑封料的封装件,封装件包括芯片(1)、打线区域(2)、芯片感应区(3)、焊线(4)、塑封体(5),芯片整体呈方体结构,一面的四个角均为四分之一圆柱空间的打线区域(2),剩余部分构成类十字结构,在类十字结构中部为一个方形的芯片感应区(3),其特征在于,芯片感应区(3)的上部有圆型钝化层(6)覆盖,塑封体(5)包裹芯片、钝化层(6)、焊线(4)。
2.根据权利要求1所述的一种用钝化层防止表面溢塑封料的封装件,其特征在于,所述钝化层(6)中间镂空,露出芯片感应区(3)。
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Citations (4)
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CN1890802A (zh) * | 2003-12-09 | 2007-01-03 | 万国半导体股份有限公司 | 电源装置的倒转j型引线封装 |
CN101290892A (zh) * | 2007-04-17 | 2008-10-22 | 矽品精密工业股份有限公司 | 感测式半导体装置及其制法 |
CN102386182A (zh) * | 2010-08-27 | 2012-03-21 | 万国半导体股份有限公司 | 在分立的功率mos场效应管集成传感场效应管的器件及方法 |
CN205810786U (zh) * | 2016-06-23 | 2016-12-14 | 华天科技(西安)有限公司 | 一种用钝化层防止表面溢塑封料的封装件 |
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US7057296B2 (en) * | 2003-10-29 | 2006-06-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bonding pad structure |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1890802A (zh) * | 2003-12-09 | 2007-01-03 | 万国半导体股份有限公司 | 电源装置的倒转j型引线封装 |
CN101290892A (zh) * | 2007-04-17 | 2008-10-22 | 矽品精密工业股份有限公司 | 感测式半导体装置及其制法 |
CN102386182A (zh) * | 2010-08-27 | 2012-03-21 | 万国半导体股份有限公司 | 在分立的功率mos场效应管集成传感场效应管的器件及方法 |
CN205810786U (zh) * | 2016-06-23 | 2016-12-14 | 华天科技(西安)有限公司 | 一种用钝化层防止表面溢塑封料的封装件 |
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