TWI654729B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法Info
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- TWI654729B TWI654729B TW104107735A TW104107735A TWI654729B TW I654729 B TWI654729 B TW I654729B TW 104107735 A TW104107735 A TW 104107735A TW 104107735 A TW104107735 A TW 104107735A TW I654729 B TWI654729 B TW I654729B
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- lead
- inner lead
- semiconductor device
- sealing resin
- island
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000011347 resin Substances 0.000 claims abstract description 43
- 229920005989 resin Polymers 0.000 claims abstract description 43
- 238000007789 sealing Methods 0.000 claims abstract description 40
- 239000000725 suspension Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000007747 plating Methods 0.000 claims abstract description 19
- 238000005520 cutting process Methods 0.000 claims description 13
- 238000007689 inspection Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 15
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 240000004050 Pentaglottis sempervirens Species 0.000 description 8
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 8
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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Abstract
本發明係一種半導體裝置及其製造方法,其課題為提供:與基板的接合堅固,且信賴性高的半導體裝置。
解決手段為由外引線(5)則藉由內引線而與內引線吊引線(3)加以電性連接者,亦對於外引線切斷面(11)加以形成電鍍皮膜,容易於從封閉樹脂(10)延伸出之外引線全表面,形成焊錫層。另外,對於內引線吊引線(3)係加以設置第1節流部(12a),可抑制內引線吊引線之切斷時的損傷。
Description
本發明係有關使用引線架之半導體裝置及其製造方法。
伴隨著近年來的攜帶電子機器之小型化,對於所使用之半導體封裝,亦必須作為小型化,薄型化,然而且確保安裝強度之半導體封裝。作為將半導體封裝作為小型化之對策,知道有將外部端子,對於基板安裝面而言平行地取出,表面安裝型封裝。作為此形式之封裝係有著SON(Small Outline Non-Lead Package)、QFN(Quad Flat Non-Lead Package)等。此等之封裝係與DIP(Dual Inline Package)或SOP(Small Outline Package)做比較時,安裝於基板時之外部電極為小之故,而有基板安裝後之焊錫圓角形成少而安裝強度弱的特徵。另外,此等封裝的製造係使用金屬沖壓,或經由蝕刻之加工所作成之引線架之情況為多。對於引線架之材料係一般使用194alloy材或銅合金。
在使用此引線架的半導體裝置之製造中,於引線架上搭載半導體晶片,以導線電性地連接半導體晶片與引線架而進行樹脂封閉加工,而在進行毛邊去除處理之後,對於銅面而言進行外裝電鍍處理。在外裝電鍍處理後,以特定的尺寸,從引線架切離半導體裝置。如此,在外裝電鍍處理後,從引線架切離半導體裝置之故,對於外引線切斷面係未加以形成外裝電鍍皮膜。因此,在安裝半導體裝置於基板時,有著焊錫潤濕性差的問題。為了使以此等條件所作成之半導體封裝之安裝強度提升,而提案有變更外引線前端部之平面形狀或剖面形狀而使基板安裝後之焊錫潤濕性提升之故,而容易形成焊錫圓角而提升安裝強度之形狀。(例如,參照專利文獻1,2)
[專利文獻1]日本特開2006-19465號公報
[專利文獻2]日本特開平7-45769號公報
但在進行半導體裝置之小型化,薄型化之中,要求有半導體裝置之基板安裝強度的更加提升。本發明係提供:提高對於半導體裝置之基板的焊錫接著強度之半導體裝置及其製造方法者。
為了解決上述課題,而使用以下的手段。
首先,一種半導體裝置,係由被覆加以載置於引線架的島狀區上的半導體晶片之封閉樹脂,和從前述封閉樹脂延伸出於側面的外引線所成之半導體裝置,其特徵為由與前述外引線加以連接之內引線,和連接於前述內引線,從前述封閉樹脂延伸出之內引線吊引線,和加以設置於前述外引線全表面之電鍍皮膜所成;而前述內引線吊引線係具有平面視與前述封閉樹脂的外形重疊之第1節流部者。
另外,前述內引線吊引線係做成平面視,於前述封閉樹脂內具有第2節流部者為特徵的半導體裝置。
另外,做成對於前述第1節流部係加以設置有V缺口者為特徵之半導體裝置。
另外,做成對於前述第1節流部與前述第2節流部之間係加以設置有貫穿孔者為特徵的半導體裝置。
更且,一種半導體裝置之製造方法,係由被覆加以載置於引線架的島狀區上的半導體晶片之封閉樹脂,和從前述封閉樹脂延伸出於側面的外引線所成之半導體裝置之製造方法,其特徵為具備前述島狀區,和與前述島狀區接近之內引線,和加以連接於前述內引線之內引線吊引線及前述外引線,和加以連接於前述島狀區之島狀區吊引線;對於前述內引線吊引線係準備具有第1節流部之引線架的工程,和將前述半導體晶片,進行晶粒接合與打線接合與樹脂封閉之工程,和切斷前述外引線之前端的工程,和由電
解電鍍而形成電鍍皮膜於前述外引線之切斷面之工程,和以前述第1節流部切斷前述內引線吊引線之工程,和切斷前述島狀區吊引線之工程所成者。
另外,如申請專利範圍第5項之半導體裝置之製造方法,其中,於前述內引線吊引線之切斷與島狀區吊引線之切斷之間,具有電性檢查工程者。
如根據本發明,對於將半導體裝置進行基板安裝時,對於從外引線之封閉樹脂露出的面所有,形成厚膜焊錫層之故,成為可堅固接合於與基板之間。另外,可抑制從引線架切離半導體裝置時,對於內引線加上壓力之損傷,可謀求確實地加以保持和與半導體元件加以電性連接之導線之與內引線的連接之可靠性之提升者。
1‧‧‧引線架
2‧‧‧內引線
3‧‧‧內引線吊引線
4‧‧‧島狀區吊引線
5‧‧‧外引線
5a‧‧‧電鍍皮膜
6‧‧‧島狀區
7‧‧‧導線
8‧‧‧電糊劑
9‧‧‧半導體晶片
10‧‧‧封閉樹脂
11‧‧‧外引線切斷面
12a‧‧‧第1吊引線節流部
12b‧‧‧第2吊引線節流部
12c‧‧‧吊引線節流V缺口形狀
12d‧‧‧吊引線部貫穿孔形狀
圖1係顯示本發明之半導體裝置之實施例的鳥瞰圖。(將外引線作為上方而圖示)
圖2係從本發明之半導體裝置之圖1的A方向而視之側面圖。(將外引線作為下方而圖示)
圖3係從本發明之半導體裝置之圖1的A方向而視之外引線擴大圖。
圖4係從本發明之半導體裝置之圖1的B方向而視之側面圖。
圖5係從本發明之半導體裝置之圖1的B方向而視之外引線擴大圖。
圖6係說明本發明之半導體裝置之發明的製造方法的圖。
圖7係顯示使用於本發明之光半導體裝置之引線架之實施例的平面圖。
圖8係顯示本發明之半導體裝置之實施例的剖面圖。
以下,依據圖面而加以說明本發明。
圖1係顯示本發明之半導體裝置之第1實施例之鳥瞰圖。在此係將外引線5作為上側而圖示。外引線5係具有其上面(安裝面),側面(外引線切斷面),與安裝面對向之相反面,並且,與各安裝面相反面和外引線切斷面構成直角的面,從封閉樹脂10延伸出。另外,對於略長方體之半導體裝置之側面,係加以切斷之內引線吊引線3與島狀區吊引線4之剖面則從封閉樹脂10露出。
圖2係從在圖1之A方向而視之側面圖。在此,將外引線5作為下側而圖示,而安裝於基板情況之安裝面係成為本圖之下面。對於外引線5周圍係加以設置有電鍍皮膜5a,而基板安裝側下面,相反側的上面,側面及外引線切斷面11之所有則由電鍍皮膜5a所被覆。
圖3係從在圖1之A方向而視之外引線擴大圖。外引線之周圍所有則由電鍍皮膜5a所被覆,而加以形成於基
板安裝側下面的電鍍皮膜5a之下面係位置於較封閉樹脂主體下面為下方。
圖4係從在圖1之B方向而視之側面圖。在此,將外引線5作為下面而圖示,而安裝於基板情況之安裝面係為本圖之下面。外引線5之基板安裝面側下面,相反側的上面及外引線切斷面11則從封閉樹脂露出,外引線之露出面所有則由電鍍皮膜5a加以被覆。
圖5係從在圖1之B方向而視之外引線擴大圖。
外引線係顯示從封閉樹脂10之側面延伸出,對於其切斷面(紙面上,右端)亦被著有電鍍皮膜5a。
接著,對於本發明之半導體裝置之製造方法加以說明。
圖6係顯示本發明之半導體裝置之第1實施例的製造方法之鳥瞰圖。
圖6(a)係顯示本實施例之引線架1之鳥瞰圖。引線架1係具有之後載置半導體晶片之島狀區6,和與島狀區6隔離加以配置之內引線2,和與內引線2連結之外引線5。並且,內引線2係經由內引線吊引線3,而島狀區6係經由島狀區吊引線4而加以連接於引線架框。
對於內引線吊引線3係加以形成有第1節流部12a。另外,內引線2與外引線5之間係有階差部,外引線下面則作為呈成為較內引線下面為低。然而,內引線下面係作為呈與島狀區下面相同高度。對於內引線吊引線3與島狀區吊引線4係有折彎部,對於與內引線2連接部分之內引
線吊引線3的下面而言,與周圍之引線架框連接部分之內引線吊引線3的下面係成為相對為低。
對於島狀區吊引線4亦同樣地,對於與島狀區6連接部分之島狀區吊引線4的下面而言,與周圍之引線架框連接部分之島狀區吊引線4的下面係成為相對為低。即,本實施例之引線架係倒轉島狀區及內引線之引線架。如此之引線架1係可經由特定厚度之194alloy材或銅合金所成的板材之模型沖壓與模壓而形成。即,為了決定島狀區6,內引線2,外引線5,內引線吊引線3,島狀區吊引線4之平面形狀而進行板材之沖壓。
接著,島狀區6,內引線3,並且,內引線吊引線3及島狀區吊引線4之一部分則對於其他部分而言呈成為相對為高地,從下方至上方進行模壓。此時,成為對於內引線2與外引線5之間加以形成有階差者。同時,成為對於內引線吊引線3及島狀區吊引線4亦加以形成有折彎部。
圖6(b)係打線接合工程後的鳥瞰圖。於所形成之引線架1的島狀區6上,藉由電糊劑8而晶粒接合半導體晶片9,接著,藉由導線7而電性連接半導體晶片表面的電極墊片與內引線2。
圖6(c)係樹脂封閉工程後的鳥瞰圖。呈被覆半導體晶片9,導線7,內引線2地,以封閉樹脂10而加以封閉。雖未加以圖示,但島狀區6之下面亦經由封閉樹脂10而加以被覆。外引線5與內引線吊引線3與島狀區吊引線4之一部分則從封閉樹脂10露出,與引線架框連
結。此時,內引線吊引線3與島狀區吊引線4之折彎部亦突出於封閉樹脂10外。對於經由封閉樹脂10而被覆內引線吊引線3之部分與露出的部份之邊界,係位置有第1節流部12a。
圖6(d)係外引線切斷工程後的鳥瞰圖。加以切斷自封閉樹脂10之側面露出之外引線5的前端部,與引線架框加以切離,形成切斷面11。此時,對於封閉樹脂10之不同的側面,係內引線吊引線3與島狀區吊引線4之一部分則從封閉樹脂10露出,但為與引線架框連結之狀態。因此,引線架框與外引線切斷面11係保持電性連接之狀態,在此狀態施以外裝電解電鍍時,不僅外引線5之上面,底面,側面,而對於切斷面11,亦成為加以形成有電鍍皮膜者。
圖6(e)係歷經外裝電鍍工程,切斷內引線吊引線3之後的鳥瞰圖。對於外引線5之表面係加以形成有電鍍皮膜5a,而成為不需要之內引線吊引線3係由第1節流部而加以切斷,與引線架框加以切離。第1節流部係比較於內引線吊引線3而為細(剖面積為小)之故,切斷時之負載為小,傳達至封閉於封閉樹脂內之內引線的損傷亦小。經由此,成為可迴避從內引線而導線脫離之問題者。
島狀區吊引線4係因與引線架框連結之故,複數個之半導體裝置係加以搭載於1片之引線架的狀態。由在此狀態進行電性特性檢查(帶測試)者,成為可進行有效率的檢查。之後,切離島狀區吊引線4而個片化半導體裝置而
得到圖6(f)所示之形狀。
由歷經如以上的製造方法者,於外引線全面加以形成有電鍍皮膜,不僅與基板的連接成為堅固,而可得到可保持內引線與導線之良好的接合之半導體裝置者。
圖7係顯示本發明之半導體裝置之引線架之實施例的平面圖。
圖7(a)係使用於在圖6所說明之半導體裝置之引線架,具有第1節流部12a之引線架的平面圖。封閉樹脂10之外形與引線架之第1節流部12a重疊情況則為本實施例的特徵。經由第1節流部12a的存在,成為可減小切斷內引線吊引線時之損傷者。
圖7(b)係加上於圖7(a)之第1節流部12a,具有第2節流部12b之引線架的平面圖。加上於封閉樹脂10之外形與引線架之第1節流部12a重疊的情況,於封閉樹脂10內具有第2節流部12b之構成。經由第1節流部12a之存在,成為可減小切斷內引線吊引線時之損傷者,且經由第2節流部12b的存在,可緩和來自外部之損傷傳播至內引線者。
圖7(c)則與圖7(b)不同的點係於第1節流部12a更施以V缺口,作成節流V缺口形狀12c。V缺口係如圖8所示之剖面圖,之後於切斷內引線吊引線部分配置V缺口的形狀。經由此,切斷內引線吊引線時之負載變更小,傳達至封閉於封閉樹脂內之內引線的損傷亦變更小。
圖7(d)則與圖7(b)不同的點係於內引線吊引線
之第1節流部12a與第2節流部12b之間,設置貫穿孔12d者。對於貫穿孔12d之中加以充填封閉樹脂,有著不易傳達內引線吊引線之切斷時之損傷於內部的效果。貫穿孔12d之存在係不僅經由所充填之封閉樹脂的吊引線之固定,而為了縮小第1節流部12a與第2節流部12b之間的貫穿孔12d周圍之引線的剖面積而具有如上述之效果。
Claims (6)
- 一種半導體裝置,係由被覆載置於引線架的島狀區上之半導體晶片之封閉樹脂,和從前述封閉樹脂延伸出於底面及第1側面之外引線所成之半導體裝置,其特徵為具備:與前述外引線連接之內引線,和連接於前述內引線,從前述封閉樹脂之與前述第1側面不同之第2側面延伸出之內引線吊引線,和設置於前述外引線全表面之電鍍皮膜;前述內引線吊引線係具有平面視與前述封閉樹脂的外形重疊之第1節流部,於前述第1節流部中,前述內引線之剖面積則變小。
- 如申請專利範圍第1項記載之半導體裝置,其中,前述內引線吊引線係具有於平面視,於前述封閉樹脂內具有第2節流部者。
- 如申請專利範圍第1項記載之半導體裝置,其中,對於前述第1節流部係加以設置有V缺口者。
- 一種半導體裝置,由被覆載置於引線架的島狀區上之半導體晶片之封閉樹脂,和從前述封閉樹脂延伸出於側面之外引線所成之半導體裝置,其特徵係具備與前述外引線連接之內引線,和連接於前述內引線,從前述封閉樹脂延伸出於內引線吊引線,和設置於前述外引線全表面之電鍍皮膜;前述內引線吊引線係具有平面視與前述封閉樹脂之外形重疊之第1節流部,對於前述第1節流部與前述第2節流部之間係加以設置有貫穿孔者。
- 一種半導體裝置之製造方法,其特徵為具備島狀區,和與前述島狀區接近之內引線,和連接於前述內引線之內引線吊引線及外引線;對於前述內引線吊引線係準備具有前述內引線之剖面積變小之第1節流部之引線架的工程,和將半導體晶片,於前述島狀區進行晶粒接合之後打線接合之工程,和前述半導體晶片,前述內引線,及前述島狀區之露出部分,經由封閉樹脂被覆,前述外引線從前述封閉樹脂之底面及第1側面延伸而出,前述內引線吊引線從與前述封閉樹脂之前述第1側面不同之第2側面延伸而出之樹脂封閉工程,和切斷前述外引線之前端的工程,和由電解電鍍而形成電鍍皮膜於前述外引線之切斷面之工程,和以前述第1節流部切斷前述內引線吊引線之工程所成者。
- 如申請專利範圍第5項記載之半導體裝置之製造方法,其中,於前述內引線吊引線之切斷與前述島狀區吊引線之切斷之間,具有電性檢查工程者。
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Families Citing this family (10)
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JP6332251B2 (ja) | 2015-12-09 | 2018-05-30 | 日亜化学工業株式会社 | パッケージの製造方法及び発光装置の製造方法、並びにパッケージ及び発光装置 |
JP6840466B2 (ja) * | 2016-03-08 | 2021-03-10 | 株式会社アムコー・テクノロジー・ジャパン | 半導体パッケージ及び半導体パッケージの製造方法 |
CN106048679A (zh) * | 2016-05-30 | 2016-10-26 | 北京首钢微电子有限公司 | 一种集成电路的电镀方法 |
US10896869B2 (en) * | 2018-01-12 | 2021-01-19 | Amkor Technology Singapore Holding Pte. Ltd. | Method of manufacturing a semiconductor device |
JP7156673B2 (ja) * | 2018-08-08 | 2022-10-19 | 日清紡マイクロデバイス株式会社 | 半導体装置 |
US11145574B2 (en) | 2018-10-30 | 2021-10-12 | Microchip Technology Incorporated | Semiconductor device packages with electrical routing improvements and related methods |
US11222790B2 (en) * | 2019-12-26 | 2022-01-11 | Nxp Usa, Inc. | Tie bar removal for semiconductor device packaging |
US20210305136A1 (en) * | 2020-03-27 | 2021-09-30 | Integrated Silicon Solution Inc. | Package structure |
NL2027540B1 (en) | 2021-02-11 | 2022-09-12 | Sencio B V | Semiconductor Lead-on-Chip Assembly |
US11611170B2 (en) | 2021-03-23 | 2023-03-21 | Amkor Technology Singapore Holding Pte. Ltd | Semiconductor devices having exposed clip top sides and methods of manufacturing semiconductor devices |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5929035U (ja) * | 1982-08-17 | 1984-02-23 | 日本電気ホームエレクトロニクス株式会社 | リ−ドフレ−ム |
JPS59147448A (ja) * | 1983-02-12 | 1984-08-23 | Fujitsu Ltd | 半導体素子搭載用リ−ドフレ−ムおよびこれを用いて製造される半導体装置とその製造方法 |
JPS59178756A (ja) * | 1983-03-29 | 1984-10-11 | Toshiba Corp | 半導体装置 |
JPH0233959A (ja) * | 1988-07-22 | 1990-02-05 | Nec Kyushu Ltd | 半導体装置用リードフレーム |
JPH05190748A (ja) * | 1992-01-14 | 1993-07-30 | Toshiba Corp | 電子部品の実装パッケージ製造方法 |
KR0145768B1 (ko) * | 1994-08-16 | 1998-08-01 | 김광호 | 리드 프레임과 그를 이용한 반도체 패키지 제조방법 |
JPH1074882A (ja) * | 1996-08-29 | 1998-03-17 | Nec Kansai Ltd | リードフレーム及びタイバ切断装置 |
JP2933036B2 (ja) * | 1996-11-29 | 1999-08-09 | 日本電気株式会社 | 中空パッケージ |
JPH11145365A (ja) * | 1997-11-11 | 1999-05-28 | Toppan Printing Co Ltd | Ic用リードフレーム |
JPH11354705A (ja) * | 1998-06-04 | 1999-12-24 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2000294718A (ja) * | 1999-04-05 | 2000-10-20 | Sony Corp | 半導体装置及びその製造方法 |
JP2001077279A (ja) * | 1999-09-01 | 2001-03-23 | Matsushita Electronics Industry Corp | リードフレームとそれを用いた樹脂封止型半導体装置の製造方法 |
JP3895570B2 (ja) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
JP3537417B2 (ja) * | 2001-12-25 | 2004-06-14 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP4011076B2 (ja) * | 2004-06-28 | 2007-11-21 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2006019465A (ja) | 2004-07-01 | 2006-01-19 | Mitsui Chemicals Inc | 半導体パッケージおよびその製造方法 |
JP2006332275A (ja) * | 2005-05-25 | 2006-12-07 | Mitsumi Electric Co Ltd | 半導体装置の製造方法及び半導体装置 |
JP2008270302A (ja) * | 2007-04-16 | 2008-11-06 | Sanyo Electric Co Ltd | 半導体装置 |
JP5634033B2 (ja) * | 2008-08-29 | 2014-12-03 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 樹脂封止型半導体装置とその製造方法 |
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US20150270197A1 (en) | 2015-09-24 |
CN104934404A (zh) | 2015-09-23 |
US20170229355A1 (en) | 2017-08-10 |
TW201546987A (zh) | 2015-12-16 |
US10043721B2 (en) | 2018-08-07 |
JP2015179737A (ja) | 2015-10-08 |
KR102330403B1 (ko) | 2021-11-23 |
US9698064B2 (en) | 2017-07-04 |
CN104934404B (zh) | 2019-12-06 |
KR20150109284A (ko) | 2015-10-01 |
JP6370071B2 (ja) | 2018-08-08 |
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