JP7156673B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP7156673B2 JP7156673B2 JP2018149581A JP2018149581A JP7156673B2 JP 7156673 B2 JP7156673 B2 JP 7156673B2 JP 2018149581 A JP2018149581 A JP 2018149581A JP 2018149581 A JP2018149581 A JP 2018149581A JP 7156673 B2 JP7156673 B2 JP 7156673B2
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- Prior art keywords
- lead
- lead terminals
- row
- terminals
- semiconductor device
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Lead Frames For Integrated Circuits (AREA)
Description
Claims (1)
- ダイパッドにチップを搭載し、前記ダイパッドを囲んで配置したリード端子の一部を露出するように封止樹脂により封止した半導体装置において、
前記リード端子は、前記ダイパッドを挟んで対向して配置した複数のリード端子からなる第1のリード列と第2のリード列と、前記第1のリード列および前記第2のリード列のリード端子の延出方向と直交する方向に延出するように配置した複数のリード端子からなる第3のリード列と第4のリード列とを備え、
前記第1のリード列のリード端子および前記第2のリード列のリード端子は、前記封止樹脂により封止された封止部から前記リード端子の一部が延出するとともに、該延出するリード端子間に前記封止樹脂が充填されていることと、
前記第3のリード列のリード端子および前記第4のリード列のリード端子は、前記封止部の裏面に一部が露出するとともに前記封止部の側面から切断部が露出していることと、
前記第1のリード列、前記第2のリード列、前記第3のリード列および前記第4のリード列のリード端子は、各リード列の両端のリード端子が、該両端のリード端子間に配置する他のリード端子より幅が広いことと、
前記第1のリード列あるいは前記第2のリード列の前記幅が広いリード端子の幅は、前記第3のリード列および前記第4のリード列の前記幅が広いリード端子の幅より広いことを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018149581A JP7156673B2 (ja) | 2018-08-08 | 2018-08-08 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018149581A JP7156673B2 (ja) | 2018-08-08 | 2018-08-08 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020025049A JP2020025049A (ja) | 2020-02-13 |
JP7156673B2 true JP7156673B2 (ja) | 2022-10-19 |
Family
ID=69619039
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2018149581A Active JP7156673B2 (ja) | 2018-08-08 | 2018-08-08 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP7156673B2 (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000150725A (ja) | 1998-11-05 | 2000-05-30 | Sony Corp | 半導体装置およびその製造方法 |
JP2000299400A (ja) | 1999-04-14 | 2000-10-24 | Sony Corp | ノンリード・フラットパッケージ型半導体装置 |
JP2015179737A (ja) | 2014-03-19 | 2015-10-08 | セイコーインスツル株式会社 | 半導体装置及びその製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04184968A (ja) * | 1990-11-19 | 1992-07-01 | Hitachi Ltd | 電子部品およびその製造に用いるリードフレームならびに電子部品の実装方法 |
JPH11214606A (ja) * | 1998-01-29 | 1999-08-06 | Matsushita Electron Corp | 樹脂封止型半導体装置及びリードフレーム |
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2018
- 2018-08-08 JP JP2018149581A patent/JP7156673B2/ja active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000150725A (ja) | 1998-11-05 | 2000-05-30 | Sony Corp | 半導体装置およびその製造方法 |
JP2000299400A (ja) | 1999-04-14 | 2000-10-24 | Sony Corp | ノンリード・フラットパッケージ型半導体装置 |
JP2015179737A (ja) | 2014-03-19 | 2015-10-08 | セイコーインスツル株式会社 | 半導体装置及びその製造方法 |
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JP2020025049A (ja) | 2020-02-13 |
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