JP2015179737A - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
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- 239000000725 suspension Substances 0.000 claims abstract description 64
- 239000011347 resin Substances 0.000 claims abstract description 38
- 229920005989 resin Polymers 0.000 claims abstract description 38
- 238000007747 plating Methods 0.000 claims abstract description 20
- 238000007789 sealing Methods 0.000 claims description 39
- 238000005520 cutting process Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 7
- 238000007689 inspection Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 15
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 abstract 1
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 8
- 240000004050 Pentaglottis sempervirens Species 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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Abstract
【解決手段】アウターリード5がインナーリードを介してインナーリード吊りリード3と電気的に接続されることで、アウターリード切断面11にもメッキ皮膜が形成され、封止樹脂10から延出するアウターリード全表面に半田層が形成しやすくなる。また、インナーリード吊りリード3には第1の絞り部12aが設けられ、インナーリード吊りリードの切断時のダメージを抑制できる。
【選択図】図6
Description
まず、リードフレームのアイランド上に載置された半導体チップを覆う封止樹脂と、前記封止樹脂から側面に延出するアウターリードとからなる半導体装置であって、前記アウターリードと接続されたインナーリードと、前記インナーリードに接続し、前記封止樹脂から延出するインナーリード吊りリードと、前記アウターリード全表面に設けられたメッキ皮膜とからなり、前記インナー吊りリードは、平面視的に前記封止樹脂の外形と重畳する第1の絞り部を有することを特徴とする半導体装置とした。
また、前記第1の絞り部にはVノッチが設けられることを特徴とする半導体装置とした。
また、前記第1の絞り部と前記第2の絞り部の間にはスルーホールが設けられることを特徴とする半導体装置とした。
また、前記インナーリード吊りリードの切断とアイランド吊りリードの切断との間に電気特性検査工程を有することを特徴とする請求項5記載の半導体装置の製造方法とした。
図1は、本発明の半導体装置の第1の実施例を示す鳥瞰図である。ここではアウターリード5を上側にして図示している。アウターリード5は、その上面(実装面)、側面(アウターリード切断面)、実装面と向い合う反対面、そして、実装面と反対面とアウターリード切断面のそれぞれと直角をなす面を有し、封止樹脂10から延出している。また、ほぼ直方体の半導体装置の側面には、切断されたインナーリード吊りリード3とアイランド吊りリード4の断面が封止樹脂10から露出している。
アウターリードは、封止樹脂10の側面から延出しており、その切断面(紙面上、右端)にもメッキ皮膜5aが被着していることを示している。
図6は、本発明の半導体装置の第1の実施例の製造方法を示す鳥瞰図である。
図6(a)は、本実施例のリードフレーム1を示す鳥瞰図である。リードフレーム1は、のちに半導体チップを載置するアイランド6と、アイランド6と離れて配置されたインナーリード2と、インナーリード2とつながるアウターリード5、そして、インナーリード2はインナーリード吊りリード3、アイランド6はアイランド吊りリード4によってリードフレーム枠に接続されている。
図7(a)は、図6で説明した半導体装置に用いるリードフレームであって、第1の絞り部12aを有するリードフレームの平面図である。封止樹脂10の外形とリードフレームの第1の絞り部12aが重なり合うことが本実施例の特徴である。第1の絞り部12aの存在によって、インナーリード吊りリードを切断した時のダメージを小さくすることが可能となる。
2 インナーリード
3 インナーリード吊りリード
4 アイランド吊りリード
5 アウターリード
5a メッキ皮膜
6 アイランド
7 ワイヤ
8 ペースト剤
9 半導体チップ
10 封止樹脂
11 アウターリード切断面
12a 第1の吊りリード絞り部
12b 第2の吊りリード絞り部
12c 吊りリード絞りVノッチ形状
12d 吊りリード部スルーホール形状
Claims (6)
- リードフレームのアイランド上に載置された半導体チップを覆う封止樹脂と、前記封止樹脂から側面に延出するアウターリードとからなる半導体装置であって、
前記アウターリードと接続されたインナーリードと、
前記インナーリードに接続し、前記封止樹脂から延出するインナーリード吊りリードと、
前記アウターリード全表面に設けられたメッキ皮膜とを備え、
前記インナーリード吊りリードは、平面視的に前記封止樹脂の外形と重畳する第1の絞り部を有することを特徴とする半導体装置。 - 前記インナーリード吊りリード部は、平面視的に前記封止樹脂内に第2の絞り部を有することを特徴とする請求項1記載の半導体装置。
- 前記第1の絞り部にはVノッチが設けられることを特徴とする請求項2記載の半導体装置。
- 前記第1の絞り部と前記第2の絞り部の間にはスルーホールが設けられることを特徴とする請求項2記載の半導体装置。
- アイランドと、前記アイランドと近接するインナーリードと、前記インナーリードに接続されたインナーリード吊りリードおよびアウターリードと、前記アイランドに接続されたアイランド吊りリードと、を備え、前記インナーリード吊りリードには第1の絞り部を有するリードフレームを準備する工程と、
半導体チップをダイボンディングとワイヤーボンディングと樹脂封止する工程と、
前記アウターリードの先端を切断する工程と、
電解メッキにて前記アウターリードの切断面にメッキ皮膜を形成する工程と、
前記インナーリード吊りリードおよび前記アイランド吊りリードを前記第1の絞り部で切断する工程と、
からなることを特徴とする半導体装置の製造方法。 - 前記インナーリード吊りリードの切断と前記アイランド吊りリードの切断の間に電気特性検査工程を有することを特徴とする請求項5記載の半導体装置の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014056450A JP6370071B2 (ja) | 2014-03-19 | 2014-03-19 | 半導体装置及びその製造方法 |
TW104107735A TWI654729B (zh) | 2014-03-19 | 2015-03-11 | 半導體裝置及其製造方法 |
US14/644,249 US9698064B2 (en) | 2014-03-19 | 2015-03-11 | Semiconductor device having semiconductor chip mounted on lead frame |
KR1020150037418A KR102330403B1 (ko) | 2014-03-19 | 2015-03-18 | 반도체 장치 및 그 제조 방법 |
CN201510121149.XA CN104934404B (zh) | 2014-03-19 | 2015-03-19 | 半导体装置及其制造方法 |
US15/495,058 US10043721B2 (en) | 2014-03-19 | 2017-04-24 | Method of manufacturing semiconductor device having semiconductor chip mounted on lead frame |
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Cited By (2)
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US10177282B2 (en) | 2015-12-09 | 2019-01-08 | Nichia Corporation | Method for manufacturing package, method for manufacturing light emitting device, package, and light emitting device |
JP2020025049A (ja) * | 2018-08-08 | 2020-02-13 | 新日本無線株式会社 | 半導体装置 |
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US10896869B2 (en) * | 2018-01-12 | 2021-01-19 | Amkor Technology Singapore Holding Pte. Ltd. | Method of manufacturing a semiconductor device |
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US11222790B2 (en) * | 2019-12-26 | 2022-01-11 | Nxp Usa, Inc. | Tie bar removal for semiconductor device packaging |
US20210305136A1 (en) * | 2020-03-27 | 2021-09-30 | Integrated Silicon Solution Inc. | Package structure |
NL2027540B1 (en) | 2021-02-11 | 2022-09-12 | Sencio B V | Semiconductor Lead-on-Chip Assembly |
US11611170B2 (en) | 2021-03-23 | 2023-03-21 | Amkor Technology Singapore Holding Pte. Ltd | Semiconductor devices having exposed clip top sides and methods of manufacturing semiconductor devices |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5929035U (ja) * | 1982-08-17 | 1984-02-23 | 日本電気ホームエレクトロニクス株式会社 | リ−ドフレ−ム |
JPS59147448A (ja) * | 1983-02-12 | 1984-08-23 | Fujitsu Ltd | 半導体素子搭載用リ−ドフレ−ムおよびこれを用いて製造される半導体装置とその製造方法 |
JPS59178756A (ja) * | 1983-03-29 | 1984-10-11 | Toshiba Corp | 半導体装置 |
JPH0233959A (ja) * | 1988-07-22 | 1990-02-05 | Nec Kyushu Ltd | 半導体装置用リードフレーム |
JPH05190748A (ja) * | 1992-01-14 | 1993-07-30 | Toshiba Corp | 電子部品の実装パッケージ製造方法 |
JPH0870084A (ja) * | 1994-08-16 | 1996-03-12 | Samsung Electron Co Ltd | 半導体パッケージおよびその製造方法 |
JPH1074882A (ja) * | 1996-08-29 | 1998-03-17 | Nec Kansai Ltd | リードフレーム及びタイバ切断装置 |
JPH11145365A (ja) * | 1997-11-11 | 1999-05-28 | Toppan Printing Co Ltd | Ic用リードフレーム |
JP2000294718A (ja) * | 1999-04-05 | 2000-10-20 | Sony Corp | 半導体装置及びその製造方法 |
JP2001077279A (ja) * | 1999-09-01 | 2001-03-23 | Matsushita Electronics Industry Corp | リードフレームとそれを用いた樹脂封止型半導体装置の製造方法 |
JP2006332275A (ja) * | 2005-05-25 | 2006-12-07 | Mitsumi Electric Co Ltd | 半導体装置の製造方法及び半導体装置 |
JP2010080914A (ja) * | 2008-08-29 | 2010-04-08 | Sanyo Electric Co Ltd | 樹脂封止型半導体装置とその製造方法、リードフレーム |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2933036B2 (ja) * | 1996-11-29 | 1999-08-09 | 日本電気株式会社 | 中空パッケージ |
JPH11354705A (ja) * | 1998-06-04 | 1999-12-24 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP3895570B2 (ja) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
JP3537417B2 (ja) * | 2001-12-25 | 2004-06-14 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP4011076B2 (ja) * | 2004-06-28 | 2007-11-21 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2006019465A (ja) | 2004-07-01 | 2006-01-19 | Mitsui Chemicals Inc | 半導体パッケージおよびその製造方法 |
JP2008270302A (ja) * | 2007-04-16 | 2008-11-06 | Sanyo Electric Co Ltd | 半導体装置 |
-
2014
- 2014-03-19 JP JP2014056450A patent/JP6370071B2/ja not_active Expired - Fee Related
-
2015
- 2015-03-11 TW TW104107735A patent/TWI654729B/zh not_active IP Right Cessation
- 2015-03-11 US US14/644,249 patent/US9698064B2/en active Active
- 2015-03-18 KR KR1020150037418A patent/KR102330403B1/ko active IP Right Grant
- 2015-03-19 CN CN201510121149.XA patent/CN104934404B/zh not_active Expired - Fee Related
-
2017
- 2017-04-24 US US15/495,058 patent/US10043721B2/en not_active Expired - Fee Related
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5929035U (ja) * | 1982-08-17 | 1984-02-23 | 日本電気ホームエレクトロニクス株式会社 | リ−ドフレ−ム |
JPS59147448A (ja) * | 1983-02-12 | 1984-08-23 | Fujitsu Ltd | 半導体素子搭載用リ−ドフレ−ムおよびこれを用いて製造される半導体装置とその製造方法 |
JPS59178756A (ja) * | 1983-03-29 | 1984-10-11 | Toshiba Corp | 半導体装置 |
JPH0233959A (ja) * | 1988-07-22 | 1990-02-05 | Nec Kyushu Ltd | 半導体装置用リードフレーム |
JPH05190748A (ja) * | 1992-01-14 | 1993-07-30 | Toshiba Corp | 電子部品の実装パッケージ製造方法 |
JPH0870084A (ja) * | 1994-08-16 | 1996-03-12 | Samsung Electron Co Ltd | 半導体パッケージおよびその製造方法 |
JPH1074882A (ja) * | 1996-08-29 | 1998-03-17 | Nec Kansai Ltd | リードフレーム及びタイバ切断装置 |
JPH11145365A (ja) * | 1997-11-11 | 1999-05-28 | Toppan Printing Co Ltd | Ic用リードフレーム |
JP2000294718A (ja) * | 1999-04-05 | 2000-10-20 | Sony Corp | 半導体装置及びその製造方法 |
JP2001077279A (ja) * | 1999-09-01 | 2001-03-23 | Matsushita Electronics Industry Corp | リードフレームとそれを用いた樹脂封止型半導体装置の製造方法 |
JP2006332275A (ja) * | 2005-05-25 | 2006-12-07 | Mitsumi Electric Co Ltd | 半導体装置の製造方法及び半導体装置 |
JP2010080914A (ja) * | 2008-08-29 | 2010-04-08 | Sanyo Electric Co Ltd | 樹脂封止型半導体装置とその製造方法、リードフレーム |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10177282B2 (en) | 2015-12-09 | 2019-01-08 | Nichia Corporation | Method for manufacturing package, method for manufacturing light emitting device, package, and light emitting device |
US10847683B2 (en) | 2015-12-09 | 2020-11-24 | Nichia Corporation | Package and light emitting device |
JP2020025049A (ja) * | 2018-08-08 | 2020-02-13 | 新日本無線株式会社 | 半導体装置 |
JP7156673B2 (ja) | 2018-08-08 | 2022-10-19 | 日清紡マイクロデバイス株式会社 | 半導体装置 |
Also Published As
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JP6370071B2 (ja) | 2018-08-08 |
TWI654729B (zh) | 2019-03-21 |
US20170229355A1 (en) | 2017-08-10 |
US10043721B2 (en) | 2018-08-07 |
KR20150109284A (ko) | 2015-10-01 |
CN104934404B (zh) | 2019-12-06 |
TW201546987A (zh) | 2015-12-16 |
US20150270197A1 (en) | 2015-09-24 |
CN104934404A (zh) | 2015-09-23 |
US9698064B2 (en) | 2017-07-04 |
KR102330403B1 (ko) | 2021-11-23 |
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