CN104934404A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
- Publication number
- CN104934404A CN104934404A CN201510121149.XA CN201510121149A CN104934404A CN 104934404 A CN104934404 A CN 104934404A CN 201510121149 A CN201510121149 A CN 201510121149A CN 104934404 A CN104934404 A CN 104934404A
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- Prior art keywords
- lead
- messenger wire
- inner lead
- semiconductor device
- island portion
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000011347 resin Substances 0.000 claims abstract description 39
- 229920005989 resin Polymers 0.000 claims abstract description 39
- 230000008602 contraction Effects 0.000 claims description 34
- 238000007789 sealing Methods 0.000 claims description 33
- 238000000576 coating method Methods 0.000 claims description 20
- 239000011248 coating agent Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- 238000005868 electrolysis reaction Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 16
- 239000000725 suspension Substances 0.000 abstract 3
- 229910000679 solder Inorganic materials 0.000 abstract 1
- 238000009434 installation Methods 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000003447 ipsilateral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (6)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014056450A JP6370071B2 (ja) | 2014-03-19 | 2014-03-19 | 半導体装置及びその製造方法 |
JP2014-056450 | 2014-03-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104934404A true CN104934404A (zh) | 2015-09-23 |
CN104934404B CN104934404B (zh) | 2019-12-06 |
Family
ID=54121501
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510121149.XA Expired - Fee Related CN104934404B (zh) | 2014-03-19 | 2015-03-19 | 半导体装置及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US9698064B2 (zh) |
JP (1) | JP6370071B2 (zh) |
KR (1) | KR102330403B1 (zh) |
CN (1) | CN104934404B (zh) |
TW (1) | TWI654729B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106048679A (zh) * | 2016-05-30 | 2016-10-26 | 北京首钢微电子有限公司 | 一种集成电路的电镀方法 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6332251B2 (ja) | 2015-12-09 | 2018-05-30 | 日亜化学工業株式会社 | パッケージの製造方法及び発光装置の製造方法、並びにパッケージ及び発光装置 |
JP6840466B2 (ja) | 2016-03-08 | 2021-03-10 | 株式会社アムコー・テクノロジー・ジャパン | 半導体パッケージ及び半導体パッケージの製造方法 |
US10896869B2 (en) * | 2018-01-12 | 2021-01-19 | Amkor Technology Singapore Holding Pte. Ltd. | Method of manufacturing a semiconductor device |
JP7156673B2 (ja) * | 2018-08-08 | 2022-10-19 | 日清紡マイクロデバイス株式会社 | 半導体装置 |
US11145574B2 (en) | 2018-10-30 | 2021-10-12 | Microchip Technology Incorporated | Semiconductor device packages with electrical routing improvements and related methods |
US11222790B2 (en) | 2019-12-26 | 2022-01-11 | Nxp Usa, Inc. | Tie bar removal for semiconductor device packaging |
US20210305136A1 (en) * | 2020-03-27 | 2021-09-30 | Integrated Silicon Solution Inc. | Package structure |
NL2027540B1 (en) | 2021-02-11 | 2022-09-12 | Sencio B V | Semiconductor Lead-on-Chip Assembly |
US11611170B2 (en) | 2021-03-23 | 2023-03-21 | Amkor Technology Singapore Holding Pte. Ltd | Semiconductor devices having exposed clip top sides and methods of manufacturing semiconductor devices |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5710064A (en) * | 1994-08-16 | 1998-01-20 | Samsung Electronics Co., Ltd. | Method for manufacturing a semiconductor package |
US20010052643A1 (en) * | 1998-06-04 | 2001-12-20 | Koichi Sugihara | Semiconductor device and method for manufacturing same |
CN1146989C (zh) * | 1996-11-29 | 2004-04-21 | 日本电气株式会社 | 电子元件 |
US20050285240A1 (en) * | 2004-06-28 | 2005-12-29 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
CN101290920A (zh) * | 2007-04-16 | 2008-10-22 | 三洋电机株式会社 | 半导体装置 |
US20120007225A1 (en) * | 2000-12-28 | 2012-01-12 | Hitachi Hokkai Semiconductor Ltd. | Semiconductor device |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5929035U (ja) * | 1982-08-17 | 1984-02-23 | 日本電気ホームエレクトロニクス株式会社 | リ−ドフレ−ム |
JPS59147448A (ja) * | 1983-02-12 | 1984-08-23 | Fujitsu Ltd | 半導体素子搭載用リ−ドフレ−ムおよびこれを用いて製造される半導体装置とその製造方法 |
JPS59178756A (ja) * | 1983-03-29 | 1984-10-11 | Toshiba Corp | 半導体装置 |
JPH0233959A (ja) * | 1988-07-22 | 1990-02-05 | Nec Kyushu Ltd | 半導体装置用リードフレーム |
JPH05190748A (ja) * | 1992-01-14 | 1993-07-30 | Toshiba Corp | 電子部品の実装パッケージ製造方法 |
JPH1074882A (ja) * | 1996-08-29 | 1998-03-17 | Nec Kansai Ltd | リードフレーム及びタイバ切断装置 |
JPH11145365A (ja) * | 1997-11-11 | 1999-05-28 | Toppan Printing Co Ltd | Ic用リードフレーム |
JP2000294718A (ja) * | 1999-04-05 | 2000-10-20 | Sony Corp | 半導体装置及びその製造方法 |
JP2001077279A (ja) * | 1999-09-01 | 2001-03-23 | Matsushita Electronics Industry Corp | リードフレームとそれを用いた樹脂封止型半導体装置の製造方法 |
JP3537417B2 (ja) * | 2001-12-25 | 2004-06-14 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP2006019465A (ja) | 2004-07-01 | 2006-01-19 | Mitsui Chemicals Inc | 半導体パッケージおよびその製造方法 |
JP2006332275A (ja) * | 2005-05-25 | 2006-12-07 | Mitsumi Electric Co Ltd | 半導体装置の製造方法及び半導体装置 |
JP5634033B2 (ja) * | 2008-08-29 | 2014-12-03 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 樹脂封止型半導体装置とその製造方法 |
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2014
- 2014-03-19 JP JP2014056450A patent/JP6370071B2/ja not_active Expired - Fee Related
-
2015
- 2015-03-11 TW TW104107735A patent/TWI654729B/zh not_active IP Right Cessation
- 2015-03-11 US US14/644,249 patent/US9698064B2/en active Active
- 2015-03-18 KR KR1020150037418A patent/KR102330403B1/ko active IP Right Grant
- 2015-03-19 CN CN201510121149.XA patent/CN104934404B/zh not_active Expired - Fee Related
-
2017
- 2017-04-24 US US15/495,058 patent/US10043721B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5710064A (en) * | 1994-08-16 | 1998-01-20 | Samsung Electronics Co., Ltd. | Method for manufacturing a semiconductor package |
CN1146989C (zh) * | 1996-11-29 | 2004-04-21 | 日本电气株式会社 | 电子元件 |
US20010052643A1 (en) * | 1998-06-04 | 2001-12-20 | Koichi Sugihara | Semiconductor device and method for manufacturing same |
US20120007225A1 (en) * | 2000-12-28 | 2012-01-12 | Hitachi Hokkai Semiconductor Ltd. | Semiconductor device |
US20050285240A1 (en) * | 2004-06-28 | 2005-12-29 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
CN101290920A (zh) * | 2007-04-16 | 2008-10-22 | 三洋电机株式会社 | 半导体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106048679A (zh) * | 2016-05-30 | 2016-10-26 | 北京首钢微电子有限公司 | 一种集成电路的电镀方法 |
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US9698064B2 (en) | 2017-07-04 |
JP6370071B2 (ja) | 2018-08-08 |
CN104934404B (zh) | 2019-12-06 |
US20150270197A1 (en) | 2015-09-24 |
KR20150109284A (ko) | 2015-10-01 |
TW201546987A (zh) | 2015-12-16 |
US20170229355A1 (en) | 2017-08-10 |
US10043721B2 (en) | 2018-08-07 |
KR102330403B1 (ko) | 2021-11-23 |
TWI654729B (zh) | 2019-03-21 |
JP2015179737A (ja) | 2015-10-08 |
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