JP5006640B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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Description
本発明は、上記課題を解決すべくなされたものであり、その目的とするところは、共通の回路基板を用いることができ、コストの低減化が図れる半導体装置の製造方法を提供するにある。
すなわち、1種類のASICチップと、該ASICチップ用の複数の異なるメモリチップのそれぞれとを回路基板に搭載する半導体装置の製造方法において、前記ASICチップが搭載可能な共通の回路基板を用意し、前記複数の異なるメモリチップがそれぞれ搭載可能で、該各メモリチップの端子との間がワイヤで接続可能なメモリチップ用端子と、前記回路基板上の端子との間がワイヤで接続可能な外部接続端子とを有する配線パターンが形成された各メモリチップごとの台座ターミナルチップを用意し、前記ASICチップと前記異なるメモリチップの組ごとに、前記共通の回路基板上に、前記ASICチップをフリップチップ接続して搭載し、搭載される前記メモリチップに対応する前記台座ターミナルチップを選択して、該台座ターミナルチップを前記ASICチップ上に固定し、該台座ターミナルチップ上に、該台座ターミナルチップに対応する前記メモリチップを搭載し、該メモリチップの端子と対応する台座ターミナルチップのメモリチップ用端子とをワイヤにて電気的に接続し、前記台座ターミナルチップの外部接続端子と前記各回路基板の端子とをワイヤで電気的に接続することを特徴とする。
また、1種類のASICチップに対して、複数のメモリチップが存在し、該複数のメモリチップを前記台座ターミナルチップ上に併設して搭載することを特徴とする。
図1〜図3は第1の実施の形態を示す。
本実施の形態は、一種類のASICチップ20に対して、3種類のメモリチップ21、22、23をそれぞれ搭載する場合の例である。各メモリチップ21、22、23はその端子21a、22a、23aの位置にずれがある。すなわち、本例では、メモリチップ22の端子22aの位置に対して、メモリチップ21の端子21aは相対的に左側に、またメモリチップ23の端子23aは相対的に右側にずれている。
しかし、本実施の形態では、端子25aの位置を共通にした共通の回路基板25を用いる(図4)。
そして、本実施の形態では、図1(b)、図2(b)、図3(b)に示すように、異なるメモリチップ21、22、23がそれぞれ搭載可能で、該各メモリチップ21、22、23の端子21a、22a、23aとの間がワイヤで接続可能なメモリチップ用端子26a、27a、28aと、回路基板25上の端子25aとの間がワイヤで接続可能な外部接続端子26b、27b、28bとを有する配線パターン26、27、28が形成された各メモリチップごとの台座ターミナルチップ29、30、31を用意する。
各台座ターミナルチップ29、30、31は、各端子を備える配線パターン26、27、28を形成するのみであるから、その設計も製造も容易で、かつ安価に行える。すなわち、各台座ターミナルチップ29、30、31は、多層の回路基板25をそれぞれ個別に形成するのと比して、設計も製造も容易で、かつ極めて安価に製造できる。この台座ターミナルチップ29、30、31はシリコンウェーハを用いて作製することができる。
そして、ASICチップ20と異なるメモリチップ21、22、23の組ごとに、共通の回路基板25を用いて、それぞれ回路基板25上に、ASICチップ20をフリップチップ接続して搭載し、このASICチップ20上に、それぞれ台座ターミナルチップ29、30、31を接着剤を用いて固定し、台座ターミナルチップ29、30、31上に、それぞれ対応するメモリチップ21、22、23を接着剤を用いて固定する。
本実施の形態は、ASICチップ20に比して小型の複数、例えば4個までのメモリチップを搭載する場合の例である。従来は、メモリチップを1個、2個、3個、あるいは4個搭載する場合、それぞれ1個用、2個用、3個用、4個用の回路基板を別途設計、製造していた。
本例では、4個までのメモリチップ40、41、42、43(図5)に対応できる回路基板25とした。なお、メモリチップ40〜43は、同一のものでも異なるものでもよい。
例えば、図7のエリアA、B、C、Dはメモリチップ40、41、42、43がそれぞれ搭載されるエリアであり、その周りに、メモリチップ40、41、42、43の端子40a、41a、42a、43aとワイヤ33にてそれぞれ接続可能なメモリチップ用端子46aが所要の配列で形成されている。
外部接続用端子46bは、ワイヤ35により回路基板25の端子25aと接続可能な配列となっている。
まず回路基板25上にASICチップ20をフリップチップ接続して搭載する。
ASICチップ20上に接着剤により台座ターミナルチップ45を固定する。
そして、台座ターミナルチップ上に、所要数のメモリチップ(図示の例では4個)を所用の位置に接着剤を用いて固定し、メモリチップの端子と台座ターミナルチップ45のメモリチップ用端子46aとをワイヤ33で電気的に接続し、台座ターミナルチップ45の外部接続用端子46bと回路基板25の端子25aとをワイヤ35で電気的に接続し、半導体装置37に完成する(図8:平面図、図9:正面図)。なお、ASICチップ20、メモリチップ、ワイヤ33、35は封止樹脂(図示せず)にて封止するとよい。
本実施の形態は、1種類のASICチップ20に対して、同一のメモリチップ50(図10)を複数搭載する場合の例である。同一のメモリチップ50であるから、その端子50aの位置、機能も全て同一である。本例では2個までのメモリチップ50を搭載する場合で説明する。
この場合の端子25aの配列は、1つのメモリチップ50を搭載する場合と同一の配列でよい。
また、本実施の形態でも、複数個までのメモリチップを搭載できる、共通の台座ターミナルチップ52を用意し、この台座ターミナルチップ52上に複数のメモリチップ50をスペーサ51を介在させて積層して搭載するようにしている。
まず回路基板25上にASICチップ20をフリップチップ接続して搭載する。
ASICチップ20上に接着剤により台座ターミナルチップ52を固定する。
そして、台座ターミナルチップ52上に、1段めのメモリチップ50を接着剤を用いて固定し、メモリチップ50の端子50aと台座ターミナルチップ52のメモリチップ用端子54aとをワイヤ33で電気的に接続する。
次いで、台座ターミナルチップ52の外部接続用端子54bと回路基板25の端子25aとをワイヤ35で電気的に接続し、半導体装置37に完成する(図13:平面図、図14:正面図)。なお、ASICチップ20、メモリチップ、ワイヤ33、35は封止樹脂(図示せず)にて封止するとよい。
メモリチップ50が1個の場合には、もちろん1段目のメモリチップ50を搭載するだけとなる。
なお、必ずしも同一のメモリチップを重ねて搭載するのでなく、複数の異なるメモリチップを重ねて搭載するようにすることもできる。この場合、台座ターミナルチップ52には、当該複数のメモリチップを全部搭載可能な配線パターン(図示せず)を形成しておくことはもちろんである。
21〜23 メモリチップ
21a〜23a 端子
25 回路基板
25a 端子
26〜28 配線パターン
26a〜28a メモリチップ用端子
26b〜28b 外部接続用端子
29〜31 台座ターミナルチップ
33、35 ワイヤ
37 半導体装置
40〜43 メモリチップ
40a〜43a 端子
45 台座ターミナルチップ
46 配線パターン
46a メモリチップ用端子
46b 外部接続用端子
50 メモリチップ
50a 端子
52 台座ターミナルチップ
54 配線パターン
54a メモリチップ用端子
54b 外部接続用端子
Claims (4)
- 1種類のASICチップと、該ASICチップ用の複数の異なるメモリチップのそれぞれとを回路基板に搭載する半導体装置の製造方法において、
前記ASICチップが搭載可能な共通の回路基板を用意し、
前記複数の異なるメモリチップがそれぞれ搭載可能で、該各メモリチップの端子との間がワイヤで接続可能なメモリチップ用端子と、前記回路基板上の端子との間がワイヤで接続可能な外部接続端子とを有する配線パターンが形成された各メモリチップごとの台座ターミナルチップを用意し、
前記ASICチップと前記異なるメモリチップの組ごとに、
前記共通の回路基板上に、前記ASICチップをフリップチップ接続して搭載し、
搭載される前記メモリチップに対応する前記台座ターミナルチップを選択して、該台座ターミナルチップを前記ASICチップ上に固定し、
該台座ターミナルチップ上に、該台座ターミナルチップに対応する前記メモリチップを搭載し、
該メモリチップの端子と対応する台座ターミナルチップのメモリチップ用端子とをワイヤにて電気的に接続し、
前記台座ターミナルチップの外部接続端子と前記各回路基板の端子とをワイヤで電気的に接続することを特徴とする半導体装置の製造方法。 - 1種類のASICチップと、該ASICチップ用の複数の同一のもしくは異なるメモリチップとを回路基板に搭載する半導体装置の製造方法において、
前記ASICチップが搭載可能な共通の回路基板を用意し、
前記複数のメモリチップのうちの任意の数のメモリチップが搭載可能で、該各メモリチップの端子との間がワイヤで接続可能なメモリチップ用端子と、前記回路基板上の端子との間がワイヤで接続可能な外部接続端子とを有する配線パターンが形成された共通の台座ターミナルチップを用意し、
前記共通の回路基板上に、前記ASICチップをフリップチップ接続して搭載し、
該ASICチップ上に前記台座ターミナルチップを固定し、
該台座ターミナルチップ上に、任意の数の前記メモリチップを搭載し、
該メモリチップの端子と対応する台座ターミナルチップのメモリチップ用端子とをワイヤにて電気的に接続し、
前記台座ターミナルチップの外部接続端子と前記各回路基板の端子とをワイヤで電気的に接続することを特徴とする半導体装置の製造方法。 - 1種類のASICチップに対して、複数のメモリチップが存在し、該複数のメモリチップを前記台座ターミナルチップ上にスペーサを介在させて積層して搭載することを特徴とする請求項2記載の半導体装置の製造方法。
- 1種類のASICチップに対して、複数のメモリチップが存在し、該複数のメモリチップを前記台座ターミナルチップ上に併設して搭載することを特徴とする請求項2記載の半導体装置の製造方法。
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