CN1897241A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1897241A
CN1897241A CNA2006101014420A CN200610101442A CN1897241A CN 1897241 A CN1897241 A CN 1897241A CN A2006101014420 A CNA2006101014420 A CN A2006101014420A CN 200610101442 A CN200610101442 A CN 200610101442A CN 1897241 A CN1897241 A CN 1897241A
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China
Prior art keywords
wiring
semiconductor device
pad
wiring substrate
type surface
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Pending
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CNA2006101014420A
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English (en)
Inventor
菊池卓
金本光一
杉山道昭
川洼浩
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Renesas Technology Corp
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Renesas Technology Corp
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Publication of CN1897241A publication Critical patent/CN1897241A/zh
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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Abstract

本发明公开了一种制造半导体器件的方法。通过准备具有多个NSMD结构焊盘和连接到每个焊盘并且相互间以180°对称的位置而布置的引出布线和虚布线的封装衬底，以及在封装装配之后通过印制方法将焊剂印制到焊盘上，可以减少焊盘之间焊剂涂层的高度差异，以及可以改进LGA(半导体器件)的可安装性。

Description

半导体器件及其制造方法
对相关申请的交叉引用
本申请要求2005年7月14日申请的日本专利申请No.2005-205027的优先权，在此通过引用将其内容并入本申请。
技术领域
本发明涉及半导体制造技术，以及具体地，本发明涉及一种应用来改进半导体器件的可安装性的有效技术。
背景技术
印制电路板具有电路图形和绝缘衬底，其中该绝缘衬底具有与电路图形连接并且用于结合焊球和阻焊层的焊盘，在阻焊层中形成用于暴露该焊盘一部分的焊球连接的连接孔。在该焊盘的特定直径方向上，该焊盘的两端形成有在它们与连接孔的壁表面之间的间隔部分(例如，请参考专利参考文件1)。
半导体集成电路元件和布线衬底的连接结构是焊盘(pad)结构，其中该焊盘具有由抗蚀剂覆盖并且由印制电路板表面上外边缘中的非导电空间包围的引出图形，以及增加了它与印制电路板之间的连接面积(例如，请参考专利参考文件2)。
[专利参考文件1]日本未审专利公开No.Hei 9-232736(图1)
[专利参考文件2]日本未审专利公开No.Hei2000-31630(图1)
例如，内置到诸如SD(安全数字卡)卡(具有SD卡联合会标准化的标准)和记忆棒卡的存储卡中的半导体器件要求薄的形状。存在一些存储卡，其中具有控制器芯片的半导体器件和具有存储芯片的半导体器件内置在这些存储卡中。因为在这种情况下存储器需要增加容量，所以可以按照许多层级来层叠存储芯片，但是封装厚度也由此变厚。
因此，作为内置到存储卡中的半导体器件的形式，LGA(焊盘栅格阵列封装)是较有效的，其中LGA的厚度比BGA(球栅格阵列封装)和包括等效尺寸(主要是芯片尺寸)的CSP(芯片级封装)薄。通过使用形成在焊盘上的球电极作为外部端子，将BGA和CSP安装到母板上。从焊盘正表面到通过球供应方法形成的焊剂涂层的峰端的高度大于100μm，并且满足BGA型封装或者CSP型封装的JEDEC(美国电子工程设计发展联合协会)标准。另一方面，因为使用焊盘作为外部端子来将LGA安装在母板上，所以可以通过没有使用球电极的部分使半导体器件的厚度变薄。但是，因为外部端子是焊盘，LGA的安装强度是低的。存在这样一种半导体器件，即该半导体器件通过预先将焊剂涂层制作在每个焊盘上来作为改进LGA安装强度的措施而进行运送。
已经知道被称为NSMD(非阻焊层限定)的技术作为改进衬底焊盘和焊剂的结合强度的焊盘结构技术。在NSMD中，因为焊盘的正表面和侧面暴露到抗蚀剂的开口，因此，焊剂也形成到焊盘的侧面，可以提高焊盘和焊剂的结合强度。
因此，在LGA中，为了改进可安装性，优选地，焊剂涂层形成到焊盘上并且采用NSMD作为焊盘结构。
较期望的是，在包括在存储卡中的LGA中，不是采用球供应方法而是印制方法来执行在焊盘上形成焊剂涂层。因此，在小焊球(例如，焊球直径小于100μm)的情况下，因为它很轻，所以很容易受静电影响，并且因为它很难从模具(jig)分离，附着到模具上，所以很难处理。
但是，与球供应方法相比，印制方法具有很少的焊剂供应量。当存在多的焊剂供应量时，即使会发生一些焊剂高度差异，也可以在焊剂高度形成得较低的焊盘中制作能够确保与母板的安装强度的等级的焊剂量涂层。另一方面，当存在太少的焊剂供应量并且发生焊剂高度差异时，在焊剂高度形成得较低的焊盘中不能制作能够确保与母板的安装强度的等级的焊剂量涂层。换句话说，因为对于使用来改进安装强度的焊剂供应量，优选地，制作仅仅具有可以确保安装强度的等级量的涂层，因为在半导体器件内置到存储卡的情况下想尽量使得半导体器件的厚度更薄，所以即使稍微的高度差异发生，它也会降低安装可靠性。
在采用NSMD结构的LGA中，虽然用于引出的布线连接到每个焊盘，但是当在用于引出的这些布线的数目上对于每个焊盘混合使用(intermingle)比如1或者2的不同数目时，对于每个焊盘，湿的并且扩展的焊剂面积将是不同的，并且因此会产生焊剂高度发生差异的问题。
会引起焊剂被推到焊盘上的引出布线侧以及焊剂涂层的峰端位置从焊盘中心附近移位的问题。当焊剂峰端的位置根据布线引出方向移位时，在半导体器件(LGA)的筛选步骤中进行测试时会引起与插座端子的接触故障问题。
在专利参考文件1(日本未审专利公开No.Hei9-232736)和专利参考文件2(日本未审专利公开No.2000-31630)中，没有发现有意识地对薄状半导体器件的描述和关于LGA的描述。
发明内容
本发明的目的是提供一种可以改进半导体器件的可安装性的技术。
通过在此的说明以及附图，本发明的上述和其他目的以及新颖性特征将变得显而易见。
接下来，将简要概述本申请所公开的本发明中的典型发明。
即，本发明包括以下步骤：准备布线衬底，该布线衬底具有相对于主表面的背表面、形成在背表面上方的绝缘膜、形成在背表面上方并且边缘部分暴露到绝缘膜的开口的多个焊盘、以及连接到每个焊盘并且相互间以180°对称的位置布置的第一布线和第二布线；将半导体芯片安装到布线衬底的主表面上方；以及通过印制方法将焊剂印制到焊盘上。
另外，本发明包括以下步骤：准备布线衬底，该布线衬底具有相对于主表面的背表面、形成在背表面上方的绝缘膜、形成在背表面上方并且边缘部分暴露到绝缘膜的开口的多个焊盘、以及连接到每个焊盘并且布置为使得相互间布置角度为360°/连接布线数目的多条布线；将半导体芯片安装到布线衬底的主表面上方；以及通过印制方法将焊剂印制到焊盘上。
此外，本发明包括：布线衬底，该布线衬底具有相对于主表面的背表面、形成在背表面上方的绝缘膜、形成在背表面上方并且边缘部分暴露到绝缘膜的开口的多个焊盘、以及连接到每个焊盘的多个布线；安装在布线衬底的主表面上方的半导体芯片；以及电连接布线衬底和半导体芯片的导电部件；其中所述布线被布置为使得相互间布置角度为360°/连接布线数目。
下面将简要说明本申请所公开的发明的一些最典型方面所实现的优点。
通过准备布线衬底，其中该布线衬底具有边缘部分暴露到绝缘膜的开口的多个焊盘以及连接到多个焊盘的每一个并且相互间以180°对称的位置布置的第一和第二布线，以及在装配之后利用印制方法将焊剂印制到多个焊盘，可以减少焊盘之间焊剂涂层的高度差异，以及可以改进半导体器件的可安装性。
附图说明
图1是透过密封体的平面图，它显示了在本发明实施例的半导体器件结构中芯片和焊盘之间的布置关系的例子；
图2是显示图1所示的半导体器件的结构的例子的横截面图；
图3是显示图2所示的半导体器件的结构的例子的放大局部截面图；
图4是显示图1所示的半导体器件的焊盘的结构的例子的局部平面图；
图5是显示沿图4的A-A线截开的结构的横截面图；
图6是透过密封体的平面图，它显示了在本发明实施例的改型的半导体器件结构中芯片和焊盘之间的布置关系；
图7是显示图6所示的改型的半导体器件的结构的横截面图；
图8是显示图7所示的半导体器件的结构的例子的放大局部截面图；
图9是显示用于图6所示的改型的半导体器件的布线衬底的布线图形的例子的平面图；
图10是显示图9所示的截面A的结构的放大局部平面图；
图11是显示包括有图1所示的半导体器件的卡状电子器件的内部结构的例子的透视图；
图12是显示图11所示的卡状电子器件的结构的例子的横截面图；
图13是显示图1所示的半导体器件的装配中的焊剂印制过程的例子的印制处理流程图；
图14是透过密封体的平面图，它显示本发明实施例的改型的半导体器件中芯片和焊盘之间的布置关系；
图15是显示图14所示的改型的半导体器件的结构的横截面图；
图16是显示图14所示的截面A的结构的放大局部平面图；
图17是透过密封体的平面图，它显示本发明实施例的改型的半导体器件中芯片和焊盘之间的布置关系；
图18是显示图17所示的改型的半导体器件的结构的横截面图；
图19是显示在用于本发明实施例的改型的半导体器件的布线衬底的角部分的一个管脚处形成虚布线时的结构的平面图；
图20是显示使用图19所示的布线衬底的改型的半导体器件的结构的横截面图；
图21是显示在用于本发明实施例的改型的半导体器件的布线衬底的角部分的三个管脚处形成虚布线时的结构的平面图；以及
图22是显示在用于本发明实施例的改型的半导体器件的布线衬底中制作三条引出布线时的焊盘结构的局部平面图。
具体实施方式
在下面的实施例中，除非特定要求时，原则上不重复相同或者相似部分的解释。
此外，在下述实施例中，为了方便起见，如果必要，在分成多个截面之后或者在多个实施例中进行说明。这些多个截面或者实施例并不是彼此独立的，而是存在使得一个是另一个的一部分或者整体的修改例子、细节或者补充说明的某种联系，除非特别指出。
在下述实施例中，当参考元素数目(包括数目、数值、数量和范围)时，数目并不局限于特定的数目，而是可以等于或者大于或者小于特定的数目，除非特别指出或者原理上明显是数目局限于特定的数目。
之后，根据附图，详细解释本发明的实施例。在所有用于说明实施例的附图中，相同功能的部件由相同的参考数字标识，并且将省略重复的说明。
(实施例)
图1是透过密封体的平面图，它显示了在本发明实施例的半导体器件结构中芯片和焊盘之间的布置关系的例子；图2是显示图1所示的半导体器件的结构的例子的横截面图；图3是显示图2所示的半导体器件的结构的例子的放大局部截面图；图4是显示图1所示的半导体器件的焊盘的结构的例子的局部平面图；图5是显示沿图4的A-A线截开的结构的横截面图；图6是透过密封体的平面图，它显示了在本发明实施例的改型的半导体器件结构中芯片和焊盘之间的布置关系；图7是显示图6所示的改型的半导体器件的结构的横截面图；图8是显示图7所示的半导体器件的结构的例子的放大局部截面图；图9是显示用于图6所示的改型的半导体器件的布线衬底的布线图形的例子的平面图；以及图10是显示图9所示的截面A的结构的放大局部平面图。
另外，图11是显示包括有图1所示的半导体器件的卡状电子器件的内部结构的例子的透视图；图12是显示图11所示的卡状电子器件的结构的例子的横截面图；以及图13是显示图1所示的半导体器件的装配中的焊剂印制过程的例子的印制处理流程图。
此外，图14是透过密封体的平面图，它显示本发明实施例的改型的半导体器件中芯片和焊盘之间的布置关系；图15是显示图14所示的改型的半导体器件的结构的横截面图；图16是显示图14所示的截面A的结构的放大局部平面图；图17是透过密封体的平面图，它显示本发明实施例的改型的半导体器件中芯片和焊盘之间的布置关系；以及图18是显示图17所示的改型的半导体器件的结构的横截面图。
此外，图19是显示在用于本发明实施例的改型的半导体器件的布线衬底的角部分的一个管脚处形成虚布线时的结构的平面；图20是显示使用图19的布线衬底的改型的半导体器件的结构的横截面图；图21是显示在用于本发明实施例的改型的半导体器件的布线衬底的角部分的三个管脚处形成虚布线时的结构的平面；以及图22是显示在用于本发明实施例的改型的半导体器件的布线衬底中制作三条引出布线时的焊盘结构的局部平面图。
图1到图3所示的本实施例的半导体器件是树脂模制型半导体封装，其中在布线衬底上安装有半导体芯片1。半导体器件内置到诸如SD卡的如图11所示的存储卡(卡状电子器件)8中，因此要求厚度减少。这样，本实施例采用LGA 7作为半导体器件的例子并对其进行解释，与BGA等相比，LGA 7可以形成得更薄。
解释LGA 7的结构。包括具有主表面3a、与主表面3a相对的背表面3b、形成在背表面3b上的多个焊盘3d以及连接到每个焊盘3d的多条布线的封装衬底、安装在封装衬底3的主表面3a上的半导体芯片1、电连接封装衬底3和半导体芯片1的多条线(导电部件)4、以及对半导体芯片1进行树脂密封的密封体6。
因为LGA 7作为存储器件并入在存储卡8中，所以根据作为提供有存储电路的存储芯片时所需要的容量，将内置在LGA 7中的半导体芯片1层叠为多个层级。图1到图3所示的LGA 7是这样一种结构，其中两个半导体芯片1层叠为两个层级，并且例如，经由诸如粘合薄片的小片键合材料2来连接每个半导体芯片1。
即，如图2和图3所示，第一层级的半导体芯片1经由小片键合材料2粘合到封装衬底3的主表面3a上，进一步，第二层级的半导体芯片1经由小片键合材料2安装在第一层级的半导体芯片1的主表面1a上，以及通过小片键合材料2来粘合第一层级的半导体芯片1的主表面1a和第二层级的半导体芯片1的背表面1b。
如图3所示，作为绝缘膜的抗蚀层3f形成在封装衬底3处的芯材3c的背表面和正表面上。在主表面3a侧处的抗蚀层3f的开口3g中形成用于键合连接到线4的多个电极3h，以及进一步在背表面3b侧处的抗蚀层3f的开口3g中形成多个焊盘3d。
正如图4所示，每个焊盘3d形成为使得边缘部分可以暴露到抗蚀层3f的开口3g。即，形成在本实施例的LGA 7的封装衬底3中的焊盘3d是一起的NSMD结构的焊盘3d，以及包括每个焊盘3d的侧面的边缘部分已经暴露在抗蚀层3f的开口3g中。因此，在抗蚀层3f的开口3g中，封装衬底3的芯材3c暴露到焊盘3d的周围。在图4中，阴影线部分是抗蚀层3f覆盖的区域(对于图10、图16和图22中所述的那些是一样的)。
图1显示了透过封装衬底3的主表面侧3a所看到的形成在封装衬底3的背表面3b上的多个焊盘3d的布置。
正如图1所示，在本实施例的LGA 7中，相互间以180°对称的位置布置的第一布线和第二布线连接到形成在封装衬底3的背表面3b上的所有焊盘3d。
即，正如图4和图5所示，相互间以180°对称的位置布置的第一布线和第二布线连接到每个焊盘3d。例如，第一布线为引出布线3i以及第二布线为虚布线3j(但是，第一布线可以是虚布线3j，以及第二布线可以是引出布线3i)。
对于连接到每个焊盘3d的多个布线的空间关系，将它们布置为使得相互间布线的布置角度为360°/连接布线数目。因为在本实施例的情况中连接到每个焊盘3d的布线数目为两个，所以它为360°/2＝180°，并且相互间以180°对称的位置将引出布线3i和3j布置在所有焊盘3d中。
例如，引出布线3i是与信号系统的布线、GND(接地端)或者电源连接的布线。另一方面，虚布线3j是非连接布线或者与相邻焊盘3d连接的布线。
在LGA 7中，连接到形成在封装衬底3的背表面3b上的所有焊盘3d的每一个的布线数目是相同的数目。即，在所有焊盘3d中，连接的布线为两个，引出布线3i和虚布线3j，以及在封装衬底3处，一致化每个焊盘3d的引出布线的数目。
在本实施例的LGA 7中，如图3所示，通过焊剂印制形成的焊剂涂层(焊剂)5布置在封装衬底3的背表面3b的多个焊盘3d的每一个处，并且在这种情况中，焊剂涂层5的高度(T)小于或者等于100μm(T≤100μm)。即，在由焊剂印制形成的焊剂涂层5中，从焊盘3d的表面到峰端的高度为100μm或者更小，以及满足LGA型封装的JEDEC(美国电子工程设计发展联合协会)标准。
例如，封装衬底3的每个焊盘3d以及连接到其上的引出布线3i、虚布线3j等等的布线包括铜合金。
例如，半导体芯片1由硅等形成，以及集成电路形成在主表面1a中。例如，电连接半导体芯片1和用于键合封装衬底3的电极3h的线4是金线。
例如，进行半导体芯片1和多条线4的树脂密封的密封体6由热固环氧树脂等形成。
接下来，图6和图7所示的半导体器件是本实施例的改型的LGA 16，以及为了增加存储设备的存储器，它将作为存储芯片的半导体芯片1层叠为四个层级。已经相互间以180°对称的位置布置的引出布线3i和虚布线3j连接到如同LGA 7的每个焊盘3d。
这里，图6显示了透过封装衬底3的主表面3a侧所看到的形成在封装衬底3的背表面3b上的多个焊盘3d的布置。
图9显示了LGA 16的封装衬底3的布线图形，以及如图10所示，引出布线3i的一部分经由主布线3k连接到通孔3e。
正如图8所示，同样在LGA 16中，在封装衬底3的背表面3b的多个焊盘3d的每一个处布置由焊剂印制形成的焊剂涂层5。在这种情况中，焊剂涂层5的高度(T)是100μm或者更小(T≤100μm)。
接下来，图11和图12显示了存储卡8的结构，其是安装有LGA 7的卡状电子器件的例子。两个LGA 7安装在用于卡的衬底9的正表面侧，以及另一方面，在背表面侧上安装作为用于控制的封装的CSP(芯片级封装)10。这里，因为在本实施例中解释的LGA 7是层叠半导体芯片1的结构，所以半导体器件的厚度变得高于安装在用于存储卡8的卡的衬底9的背表面侧上的CSP 10。因此，优选地，采用LGA型封装作为层叠有用于存储器的半导体芯片1的半导体器件。由正表面侧的壳体11和背表面侧的壳体11分别覆盖正表面侧的两个LGA 7和背表面侧的CSP10。正如图12所示，在用于卡的衬底9的背表面侧上形成的多个外部端子12暴露到背表面侧的壳体11的开口11a。
接下来，解释本实施例的LGA 7的制造方法。
首先，准备具有多个焊盘3d的封装衬底3，其中相互间以180°对称的位置布置的引出布线3i和虚布线3j连接到所述多个焊盘3d，并且所述多个焊盘3d是在背表面处的NSMD结构。
然后，经由小片键合材料2，将第一层级的半导体芯片1安装到封装衬底3的主表面3a上。然后，经由小片键合材料2，将第二层级的半导体芯片1安装到第一层级的半导体芯片1上。
然后，利用线4电连接第一层级的半导体芯片1和用于键合封装衬底3的电极3h，以及进一步利用线4电连接第二层级的半导体芯片1和用于键合封装衬底3的电极3h。
然后，执行树脂密封，并且形成密封体6。即，它被考虑作为进行半导体芯片1和多个线4的树脂密封的模制完成，并且如13所示，以及形成密封体6。
然后，执行用于将焊剂印制到每个焊盘3d的图13的焊剂印制。即，通过利用焊剂印制方法进行印制，在封装衬底3的背表面3b的每个焊盘3d上形成焊剂。在这种情况中，首先在封装衬底3的主表面3b上布置印制掩模。同时，匹配和布置印制掩模13的开口13a和焊盘3d的位置。
然后，通过在印制掩模13上的橡皮滚子(squeegee)14，将焊剂15施加到焊盘3d上。即，通过橡皮滚子14将焊剂15置入印制掩模13的开口13a中，来将焊剂15施加到每个焊盘3d上。
如图13所示，这实现了焊剂印制完成。
然后，执行图13所示的热处理，以及在每个焊盘3d上形成焊剂涂层5。
根据本实施例的LGA 7的制造方法，在LGA装配之后，通过利用印制方法将焊剂印制到每个焊盘3d，以及使用具有多个NSMD结构的焊盘3d的封装衬底3和连接到每个焊盘3d并且相互间以180°对称的位置布置的引出布线3i和虚布线3j，而使得焊盘之间的焊剂的湿宽度(wetting breadth)面积变得相同，因为来自焊盘3d的引出布线的数目被一致化为两个。
由此，可以减少焊盘之间的焊剂涂层5的高度差异。
因此，可以改进LGA(半导体器件)7的可安装性。
即，在用于存储卡8的安装的LGA(半导体器件)7中，改进了可安装性，这通过将每个焊盘3d做成MSMD结构同时通过使形成在多个焊盘3d上的焊剂涂层5的高度为100μm或者更小来抑制封装高度，而提高焊剂的连接强度。
因为在几乎一致地对应于引出布线3i和虚布线3j的方向的相对两个方向伸展(pull)焊盘3上的焊剂，其中通过布置相互间以180°对称的位置连接到每个焊盘3d的引出布线3i和虚布线3j来以180°对称的位置布置引出布线3i和虚布线3j，所以可以将焊剂峰端的位置设置到差不多焊盘3的中心部分。由此，可以减少焊盘之间焊剂涂层5的位置偏移。
因此，可以防止在筛选步骤中进行测试时产生LGA 7的焊剂涂层5和插座端子的接触故障，并且可以改进LGA 7的可安装性。
通过布置相互间以180°对称的位置连接到焊盘3d的引出布线3i和虚布线3j，可以分散和减少在将LGA 7安装到安装衬底之后与焊盘3d中的布线的引出部分相关的应力。
因此，可以防止在焊盘3d的布线的引出部分中产生中断，并且可以提高LGA 7的可安装性。
接下来，解释图14到图22所示的本实施例的改型。
图14到图21所示的改型不是将引出布线3i和虚布线3j连接到所有焊盘3d，而是将引出布线3i和虚布线3j仅仅连接到一部分焊盘3d。
图14、图17、图19和图21显示了透过封装衬底3的主表面3a所看到的形成在封装衬底3的背表面3b上的多个焊盘3d的布置。
首先，在图14到图18所示的改型中，引出布线3i和虚布线3j连接到已经在与半导体芯片1的主表面1a的边缘部分对应的位置处布置的多个焊盘3d的每一个。即，引出布线3i和虚布线3j仅仅连接到布置在半导体芯片1的端部(边缘部分)的相邻部分正下方位置的焊盘3d。
其中，在图14和图15所示的改型的LGA 17中，当半导体芯片1的端部(边缘部分)与焊盘3d的位置重叠时，如图16所示，引出布线3i和虚布线3j连接到这些焊盘3d。
在图17和图18所示的改型的LGA 18中，当半导体芯片1的端部(边缘部分)布置在焊盘之间时，引出布线3i和虚布线3j连接到布置在该芯片端部两侧处的两排焊盘3d。
正如以上所示，因为分别利用不同的材料形成半导体芯片1和封装衬底3，所以在这些热膨胀系数上也产生不同。但是，通过将引出布线3i和虚布线3j连接到在对应于半导体芯片1的主表面1a的边缘部分的位置中布置的多个焊盘3d，当在热循环测试等中将由于半导体芯片1与密封树脂和衬底的热膨胀系数不同而产生的芯片端部应力提供给焊盘3d时，可以分散和减少施加到焊盘3d的应力。
因此，可以防止在该焊盘3d中的布线的引出部分中产生中断。
在图19到图21所示的改型中，引出布线3i和虚布线3j连接到在距封装衬底3的平面方向的中心部分距离最长的位置处布置的焊盘3d。即，引出布线3i和虚布线3j仅仅连接到在焊盘布置的最外周的角部分附近布置的焊盘3d。
其中，在图19和图20所示的改型的LGA 19中，引出布线3i和虚布线3j连接到焊盘布置得最外周的角部分的仅仅一个管脚的焊盘3d。
在图21所示的改型的LGA 20中，引出布线3i和虚布线3j连接到焊盘布置得最外周的角部分的三个管脚的焊盘3d的每一个。
因为它与封装衬底3的中心分开(远端位置)，所以当封装衬底3由于热收缩等变形(翘曲)时所产生的应力变高。但是，通过将引出布线3i和虚布线3j仅仅连接到在焊盘布置的最外周的角部分附近布置的焊盘3d，可以分散和减少施加到在封装衬底3的焊盘布置的最外周的角部分附近的焊盘3d的应力。
因此，可以防止在该焊盘3d的布线的引出部分产生中断。
接下来，图22的改型显示了在连接到焊盘3d的布线是三条的情况下的布线引出布置。
即，因为在本实施例的半导体器件中执行布置，使得关于连接到焊盘3d的多条布线的空间关系，相互间布线的布置角度为360°/连接布线的数目，所以必须在焊盘3d的120°的角度处形成虚布线3j，当连接到焊盘3d的布线数目为三个时，它变成360°/3＝120°。
这样，即使当以120°的角度形成虚布线3j时，也可以获得与在180°对称的位置处形成的情况相同的效果。
在前述中，根据上述实施例具体地解释了本发明人完成的本发明，但是本发明并不局限于上述实施例，而是在不偏离本发明的精神的限制下当然可以按照多种方式做出变化和改型。
例如，在本实施例中，在LGA(半导体器件)中，虽然采用并且作为例子解释了半导体芯片1的层叠数目是两个层级和四个层级的情况，但是，半导体芯片1可以是一个安装层级，或者可以是除了两个层级和四个层级之外的两个或者更多层叠层级。
连接到焊盘3d的布线的数目应该仅仅是两个或者更多，在这种情况中，没有必要包括虚布线3j，例如连接到焊盘3d的所有布线可以都是引出布线3i。
本发明适合于执行焊剂涂覆的半导体器件以及制造技术。

Claims (15)

1、一种制造半导体器件的方法，包括以下步骤：
(a)准备布线衬底，所述布线衬底具有主表面、与所述主表面相对的背表面、形成在所述背表面上方的绝缘膜、形成在所述背表面上方并且其边缘部分暴露到所述绝缘膜的开口的多个焊盘、连接到每个所述焊盘并且相互间以180°对称的位置布置的第一布线和第二布线；
(b)将半导体芯片安装到所述布线衬底的所述主表面上方；
(c)电连接所述半导体芯片和所述布线衬底；
(d)密封所述半导体芯片；以及
(e)通过印制方法将焊剂印制到所述焊盘上。
2、根据权利要求1的制造半导体器件的方法，其中：
所述第一布线和所述第二布线连接到形成在所述布线衬底的所述背表面上方的所有焊盘的每一个上。
3、根据权利要求1的制造半导体器件的方法，其中：
所述第一布线和所述第二布线连接到在与所述半导体芯片的主表面的边缘部分对应的位置处布置的所述焊盘的每一个上。
4、根据权利要求1的制造半导体器件的方法，其中：
所述第一布线和所述第二布线连接到在距所述布线衬底的平面方向的中心部分的距离最长的位置处布置的焊盘上。
5、根据权利要求1的制造半导体器件的方法，其中：
所述半导体器件是LGA。
6、根据权利要求1的制造半导体器件的方法，其中：
在步骤(b)，将多个所述半导体芯片层叠在所述布线衬底的所述主表面上方。
7、根据权利要求1的制造半导体器件的方法，其中：
所述第一布线和所述第二布线之间的任意一个是虚布线。
8、一种制造半导体器件的方法，包括以下步骤：
(a)准备布线衬底，所述布线衬底具有主表面、与所述主表面相对的背表面、形成在所述背表面上方的绝缘膜、形成在所述背表面上方并且其边缘部分暴露到所述绝缘膜的开口的多个焊盘、连接到每个所述焊盘并且布置为使得相互间布置角度为360°/连接布线数目的多条布线；
(b)将半导体芯片安装到所述布线衬底的所述主表面上方；
(c)电连接所述半导体芯片和所述布线衬底；
(d)密封所述半导体芯片；以及
(e)通过印制方法将焊剂印制到所述焊盘上。
9、根据权利要求8的制造半导体器件的方法，其中：
所述半导体器件是LGA。
10、根据权利要求8的制造半导体器件的方法，其中：
在步骤(b)，将多个所述半导体芯片层叠在所述布线衬底的所述主表面上方。
11、根据权利要求8的制造半导体器件的方法，其中：
任意一个所述布线是虚布线。
12、一种半导体器件，包括：
布线衬底，所述布线衬底具有主表面、与所述主表面相对的背表面、形成在所述背表面上方的绝缘膜、形成在所述背表面上方并且其边缘部分暴露到所述绝缘膜的开口的多个焊盘、连接到每个所述焊盘的多个布线；
安装在所述布线衬底的所述主表面上方的半导体芯片；以及
电连接所述布线衬底和所述半导体芯片的导电部件；
其中所述布线被布置为使得相互间布置角度为360°/连接布线数目。
13、根据权利要求12的半导体器件，其中：
焊剂连接到每个所述焊盘，以及所述焊剂的高度小于或者等于100μm。
14、根据权利要求12的半导体器件，其中：
连接到所述布线衬底的所述背表面上方形成的所有焊盘的每一个的布线的数目是相同的数目。
15、根据权利要求12的半导体器件，其中：
所述半导体器件内置到卡状电子器件中。
CNA2006101014420A 2005-07-14 2006-07-13 半导体器件及其制造方法 Pending CN1897241A (zh)

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