JP5501562B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5501562B2 JP5501562B2 JP2007321751A JP2007321751A JP5501562B2 JP 5501562 B2 JP5501562 B2 JP 5501562B2 JP 2007321751 A JP2007321751 A JP 2007321751A JP 2007321751 A JP2007321751 A JP 2007321751A JP 5501562 B2 JP5501562 B2 JP 5501562B2
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- land
- semiconductor device
- wiring
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- 239000004065 semiconductor Substances 0.000 title claims description 86
- 229910000679 solder Inorganic materials 0.000 claims description 63
- 239000000758 substrate Substances 0.000 claims description 25
- 230000002093 peripheral effect Effects 0.000 claims 2
- 238000000034 method Methods 0.000 description 26
- 238000007789 sealing Methods 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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Description
このようなBGA型半導体装置は、携帯電話等の小型電子機器に搭載されているため、配線基板とチップの熱膨張係数の差による応力や、電子機器の落下等による機械的な衝撃にも耐えることが必要になっている。
[1]本発明の半導体装置は、一面に接続パッドを有し、他面に前記接続パッドと電気的に接続された複数のランドを有する配線基板と、
前記配線基板の一面に搭載されて、前記接続パッドと電気的に接続される半導体チップと、
前記配線基板の他面に積層されるとともに、前記ランドを露出させる開口部を有するソルダーレジストと、
前記開口部を介して前記ランドに接続された外部端子と、を有し、
前記開口部を前記ランドに対してシフトして配置すると共に、前記開口部周縁において、前記ランドと対向する領域に、当該開口部内の前記ランドと対向する領域で前記ランドと分離されたダミー配線が配置されていることを特徴とする。
[2]また、本発明の半導体装置は、前記ランドと対向する領域の前記開口部周縁における前記ソルダーレジストの厚さが、前記ランド側の前記ソルダーレジストの厚さより薄いことが好ましい。
[3]また、本発明の半導体装置は、前記配線基板のコーナー部および外縁に向かって、前記ソルダーレジストの開口部がシフトしていることが好ましい。
[4]また、本発明の半導体装置は、前記ダミー配線は、前記開口部の複数箇所に設けられていることが好ましい。
[5]また、本発明の半導体装置は、前記ダミー配線は、先端に幅広部が形成されていることが好ましい。
[6]また、本発明の半導体装置は、前記ダミー配線の他端が、当該前記ランドの配線に接続されていることが好ましい。
また、本発明の半導体装置は、前記配線基板のコーナー部および外縁に向かって、前記ソルダーレジストの開口部がシフトしていることで、クラックの耐性をより向上させることができる。
また、本発明の半導体装置は、前記ダミー配線は、前記開口部の複数箇所に設けられていることで、クラックの耐性をより向上させることができる。
また、本発明の半導体装置は、前記ダミー配線は、先端に幅広部が形成されていることで、クラックの耐性をより向上させることができる。
また、本発明の半導体装置は、前記ダミー配線の他端が、当該前記ランドの配線に接続されていることで、クラックの耐性をより向上させることができる。
(第1実施形態)
図1は、第1実施形態であるBGA型の半導体装置を示す図であり、図1(a)は外部端子構造を示す平面図、図1(b)は、図1(a)のA−A’線における断面図である。図2は、第1実施形態である半導体装置のランド構造を示す図であり、図2(a)は平面図、図2(b)は図2(a)のB−B’線における断面図である。
そして、半導体チップ9の電極パッド11は、配線基板2のそれぞれ対応する接続パッド3と導電性のワイヤ12により結線されることで、電気的に接続されている。ワイヤ12は、例えばAu、Cu、Al等からなる。
更に、配線基板2の一面2aは、半導体チップ9及びワイヤ12を覆うように封止体13で覆われている。封止体13は、例えばエポキシ樹脂等の熱硬化性樹脂からなる。
その結果、クラックや衝撃に対する耐性が高まり、パッケージ全体としての信頼性を高めることが可能となる。
本実施形態の半導体装置の製造方法は、配線母基板の製品形成領域に半導体チップを設置するダイボンディング工程と、半導体チップ上の電極パッドと配線基板の接続パッドとをワイヤにより結線するワイヤボンディング工程と、複数の製品形成領域を一括的に覆う封止部を形成するモールド工程と、配線母基板の他面に半田ボールを搭載して外部端子を形成するボールマウント工程と、配線母基板のダイシングラインを回転研削することで個々の製品形成領域毎に切断・分離する基板ダイシング工程と、から概略構成されている。
図4(a)に示すように、本実施形態の半導体装置の製造方法に用いる配線母基板15は、ガラスエポキシ基材などからなる基板であり、複数の製品形成領域16を有している。製品形成領域16はマトリックス配置し、それぞれの製品形成領域16間にはダイシングライン17を形成し、ダイシングライン17で切断することにより、半導体装置1の配線基板2となる部位である。製品形成領域16は、前述した半導体装置1の配線基板2と同様の構造であり、一面15aの半導体チップ9を搭載する部位の周囲には、複数の接続パッド3を形成し、他面2b側には格子状に配置した複数のランド4を形成する。前述したように、ランド4を配置するソルダーレジスト6の開口部6aは、ランド4に対して、応力の集中する方向、例えば配線基板2のコーナー或いは外縁に向かう方向にシフトして配置する。また、開口部6aのランド4と対向する位置には、ダミー配線7を形成する。
次に、ダイボンディング工程に移行する。図4(a)に示すように、配線母基板15には、それぞれの製品形成領域16の中央領域に半導体チップ9が搭載される。半導体チップ9は、図示しないダイボンディング装置により、例えば絶縁性の接着剤を介して製品形成領域16に固着される。
次に、ワイヤボンディング工程に移行する。図4(b)に示すように、半導体チップ9上の電極パッド11と、それに対応する配線基板2の接続パッド3とを、例えばAu等からなる導電性のワイヤ12により結線する。ワイヤボンディングは、図示しないワイヤボンディング装置により、溶融され先端にボールが形成されたワイヤ12を電極パッド11に超音波熱圧着し、その後、所定のループ形状を描きながら後端を配線基板2の接続パッド3上に超音波熱圧着により接続することで行われる。全ての電極パッド11と接続パッド3とをワイヤ12にて結線する。
次に、ワイヤボンディングの完了した配線母基板15を、モールド工程に移行する。モールド工程では、図示しないトランスファモールド装置の上型と下型により、配線母基板15を型閉めした状態で、溶融された封止樹脂、例えば熱硬化性のエポキシ樹脂等を充填させ、充填させた状態でキュアすることで、封止樹脂が熱硬化し、図4(c)に示すように複数の製品形成領域16を一括的に覆う封止部18が形成される。一括モールドを用いたことにより、効率よく封止部18を形成することができる。
次に、封止部18の形成された配線母基板15を、ボールマウント工程に移行する。ボールマウント工程では、図4(d)に示すように、配線母基板15の他面15bのランド4上に半田ボール8を搭載することで、外部端子が形成される。このボールマウント工程は、例えばボールマウンターのマウントツールMにより半田ボール8を真空吸着し、フラックスを介して半田ボール8を配線基板2のランド4上に搭載する。その後、配線母基板15をリフローすることで、図4(d)に示すように、半田ボール8をランド4上に接続する。尚、本実施形態では、開口部6をランド4に対して応力の集中する方向にシフトして配置し、開口部6にランド4から離間配置したダミー配線7を設けているため、半田ボール8は、ランド4とダミー配線7に跨るように配置される。これにより、応力の集中する方向に外部端子が厚くなるように構成することができる。
次に、半田ボール8の搭載された配線母基板15を、基板ダイシング工程に移行する。基板ダイシング工程では、図4(e)に示すように、封止部18をダイシングテープ19に貼着固定し、高速回転のダイシングブレードDにより、配線母基板15のダイシングライン17を回転研削することで、個々の製品形成領域16毎に切断・分離する。その後、ダイシングテープ19からピックアップすることで、図1に示すような半導体装置1が得られる。
図5は、本発明の第2実施形態である半導体装置1Aのランド構造を示す断面図である。図5に示すように、配線基板2A、実装基板14Aのダメージが集中する部分について、さらに信頼性を向上する為、ランド4A周辺のソルダーレジスト6Aの厚さを任意に変えて、例えば応力の集中する方向のソルダーレジスト6Aの厚さが薄くなるように構成する。その結果、ソルダーレジスト6Bの厚い部分と薄い部分の差により、半田ボール8Aがシフトして実装され、任意にダメージの集中する部分の半田厚を厚くする事が可能となる。その結果、クラックに対する耐性が高まり、パッケージ全体としての信頼性を高めることが可能となる。なお、高さ調整には、ソルダーレジスト6Aのフラット加工時の治具に凹凸を付けて実現する。
図6は、本発明の第3実施形態である半導体装置1Bのランド構造を示す平面図である。図6に示すようにダミー配線7Bを複数箇所に設け、さらに配線基板2Bと半田ボールとの接着面積を大きくするように構成してもよい。
図7は、本発明の第4実施形態である半導体装置1Cのランド構造を示す平面図である。図7に示すように、ダミー配線7Cの端部を幅広にしてさらに接続面積を増やしてもよい。
図8は、本発明の第5実施形態である半導体装置1Dのランド構造を示す平面図である。図8に示すように、ダミー配線7Dを、当該ランド4Dの配線5Dと接続させることにより、予備配線として半田ボール8Dとランド4D(配線)間の信頼性を向上させてもよい。これによりランド4Dのネック部分が切れた場合にも電気的に接続が確保できる。
Claims (6)
- 一面に複数の接続パッドを有し、他面に対応する前記接続パッドと電気的に接続された複数のランドを有する配線基板と、
前記配線基板の一面に搭載されて、前記接続パッドと電気的に接続される半導体チップと、
前記配線基板の他面に積層されるとともに、前記ランドをそれぞれ露出させる複数の開口部を有し、各々の前記開口部は対応する前記ランドに対してシフトして配置されているソルダーレジストと、
前記開口部を介して前記ランドにそれぞれ接続された複数の外部端子と、
対応する前記ランドと分離し、前記開口部内に一部が露出して配置されたダミー配線とを備え、対応する前記外部端子は対応する前記ランドおよび前記ダミー配線に接続している、半導体装置。 - 前記開口部の前記ダミー配線側の周縁部におけるソルダーレジストの厚みは、対応する前記開口部の前記ランド側の周縁部におけるソルダーレジストの厚みよりも小さい、請求項1に記載の半導体装置。
- 前記配線基板のコーナー部および外縁に向かって、前記ソルダーレジストの各々の開口部が、対応する前記ランドに対してシフトしている、請求項1または2に記載の半導体装置。
- 対応する前記ランドと分離し、対応する前記開口部内に一部が露出する複数の前記ダミー配線が配置され、対応する前記外部端子は対応する前記ランドおよび前記ダミー配線に接続している、請求項1〜3の何れか1項に記載の半導体装置。
- 前記ダミー配線は、先端に幅広部が形成されている、請求項1〜4の何れか1項に記載の半導体装置。
- 前記ダミー配線は、対応する前記ランドに接続された配線に接続されている、請求項1〜5の何れか1項に記載の半導体装置。
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JP5970348B2 (ja) * | 2012-11-16 | 2016-08-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9237647B2 (en) * | 2013-09-12 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure with through molding via |
KR102408126B1 (ko) * | 2015-05-29 | 2022-06-13 | 삼성전자주식회사 | 솔더 브릿지를 억제할 수 있는 전기적 패턴을 갖는 전기적 장치 |
JP6487286B2 (ja) * | 2015-07-07 | 2019-03-20 | 日立オートモティブシステムズ株式会社 | 配線基板 |
JP6866778B2 (ja) * | 2017-06-12 | 2021-04-28 | 富士通株式会社 | パッケージ基板及びパッケージ基板の製造方法 |
JP7519248B2 (ja) | 2020-09-18 | 2024-07-19 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
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US5859474A (en) * | 1997-04-23 | 1999-01-12 | Lsi Logic Corporation | Reflow ball grid array assembly |
JP3210881B2 (ja) * | 1997-06-05 | 2001-09-25 | ソニーケミカル株式会社 | Bgaパッケージ基板 |
US6303878B1 (en) * | 1997-07-24 | 2001-10-16 | Denso Corporation | Mounting structure of electronic component on substrate board |
JP3875407B2 (ja) * | 1998-07-23 | 2007-01-31 | シチズン時計株式会社 | 半導体パッケージ |
US6400018B2 (en) * | 1998-08-27 | 2002-06-04 | 3M Innovative Properties Company | Via plug adapter |
JP2001217355A (ja) * | 1999-11-25 | 2001-08-10 | Hitachi Ltd | 半導体装置 |
JP2001230513A (ja) * | 2000-02-15 | 2001-08-24 | Denso Corp | プリント基板及びその製造方法 |
JP2001320155A (ja) * | 2000-05-11 | 2001-11-16 | Mitsubishi Electric Corp | プリント配線板のランド構造 |
JP2003289122A (ja) * | 2003-04-28 | 2003-10-10 | Hitachi Ltd | ボールグリッドアレイ型半導体装置 |
US7456493B2 (en) * | 2005-04-15 | 2008-11-25 | Alps Electric Co., Ltd. | Structure for mounting semiconductor part in which bump and land portion are hardly detached from each other and method of manufacturing mounting substrate used therein |
JP2007027287A (ja) * | 2005-07-14 | 2007-02-01 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2007317842A (ja) * | 2006-05-25 | 2007-12-06 | Elpida Memory Inc | プリント配線基板及びこれを用いた半導体パッケージ |
JP2009076569A (ja) * | 2007-09-19 | 2009-04-09 | Nec Electronics Corp | 半導体パッケージ、実装基板、およびこれらを含む半導体装置 |
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US20090154125A1 (en) | 2009-06-18 |
US7660130B2 (en) | 2010-02-09 |
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