JP5970348B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5970348B2 JP5970348B2 JP2012252309A JP2012252309A JP5970348B2 JP 5970348 B2 JP5970348 B2 JP 5970348B2 JP 2012252309 A JP2012252309 A JP 2012252309A JP 2012252309 A JP2012252309 A JP 2012252309A JP 5970348 B2 JP5970348 B2 JP 5970348B2
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Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
以下の実施の形態で説明する技術は、配線基板(インタポーザ基板)の実装面に、複数の外部電極パッドが行列状に配置されたエリアアレイ型の半導体装置に広く適用可能であるが、本実施の形態では、一例として、外部電極パッドに半田ボールが接合されたBGA(Ball Grid Array)型の半導体装置に適用した実施態様について説明する。図1は本実施の形態の半導体装置の斜視図、図2は、図1に示す半導体装置の下面図である。また、図3は、図1に示す封止体を取り除いた状態で配線基板上の半導体装置の内部構造を示す透視平面図である。また、図4は図1のA−A線に沿った断面図である。また、図5は、図2に示す半田ボールを取り除いた状態を示す平面図である。また、図6は、図5に示すソルダレジスト膜を取り除いた状態を示す平面図である。
まず、本実施の形態の半導体装置1の構成の概要について、図1〜図6を用いて説明する。本実施の形態の半導体装置1は、半導体チップ2(図3、図4参照)、および半導体チップ2が搭載された配線基板3を有する。図4に示すように半導体チップ2は、配線基板3の上面(面、チップ搭載面)3a側に搭載され、封止体(樹脂体)4により覆われている。
次に、図1〜図6に示す配線基板3の実装面側の詳細構造について説明する。図7は、図4に示す放熱用の導体パターンと実装基板の端子とを半田ボールを介して電気的に接続した状態を示す拡大断面図である。また、図8は、図5に示す配線基板のうち、チップ搭載領域の裏側周辺を拡大して示す拡大平面図である。また、図9は、図7に対する変形例を示す拡大断面図である。また、図10は、図8に示すB部の拡大平面図である。また、図11は、図10に示す仮想直線に沿った拡大断面図である。また、図23は図8に対する検討例を示す拡大平面図である。また、図24は、図11に対する検討例を示す拡大断面図であって、図23に示す一つの開口部の断面に対応している。また、図12は図10に対する変形例を示す拡大平面図である。また、図13は、図8に示す複数のランドのうちの一つを拡大して示す拡大平面図である。
次に、図10および図11に示す導体パターン3PL1の露出部3TLの向きについて説明する。図14は、図5に示す配線基板の実装面において、温度サイクル負荷が印加された時の応力分布を模式的に示す説明図である。なお、図14では、応力が加わる方向を矢印で示し、応力の大きさを矢印の太さで示している。また、図14では、領域3b1、3b2の境界を見易くするため、領域3b1には斜線のハッチング、領域3b2にはドットパターンをそれぞれ付して示している。また、図14では、見易さのために、図5に示す複数の開口部3k1、3k2、ランド10、および導体パターン3PL1は、図示を省略している。
上記のように、本実施の形態の半導体装置1の特徴の一部を説明したが、以下では、好ましい実施態様について更に説明する。
次に、図1〜図19を用いて説明した半導体装置1の製造方法(組立工程)について、図20に示すフロー図を用いて説明する。図20は、図1〜図19を用いて説明した半導体装置の組立工程のフローを示す説明図である。また、図21は、図20に示す基板準備工程で準備する配線基板の全体構造を示す平面図である。なお、以下の製造方法の説明においては、図1に示す配線基板3に相当するデバイス領域が複数個設けられた、所謂、多数個取り基板を準備して、複数のデバイス領域のそれぞれについて組立を行う製造方法について説明する。また、図21に示す複数のデバイス領域30aのそれぞれは、図1〜図19を用いて説明した配線基板3に相当するので、以下の説明では、必要に応じて図1〜図19を参照して説明する。
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
2 半導体チップ
2a 表面(主面、上面)
2b 裏面(主面、下面)
2c 側面
3 配線基板
3a 上面(面、第1主面、チップ搭載面)
3b 下面(面、第2主面、実装面)
3b1 領域(半導体チップと厚さ方向に重なる領域)
3b2 領域
3bc1、3bc2、3bc3 中心
3c 側面
3d ボンディングリード(端子、チップ搭載面側端子、パッド、ボンディングパッド)
3e コア層(絶縁層)
3eb 下面(下地面)
3f、3h ソルダレジスト膜(絶縁層)
3fk1 開口部
3hc 開口側面
3k1、3k2 開口部
3pk1 導体開口部
3r 配線
3smd 領域(SMD構造の領域)
3nsmd 領域(NSMD構造の領域)
3t 放熱導体
3th 層間導体(ビア配線、スルーホール配線)
3CP 被覆部
3CPc 側面
3HP 放熱経路
3PL1、3PL2 導体パターン(導体プレーン、ベタパターン)
3TL 露出部
3TLc 側面
4 封止体(樹脂体)
4a 上面(面)
4b 下面(面)
4c 側面
5 ダイボンド材(接着材)
6 ワイヤ(導電性部材)
7 半田ボール
7p1、7p2 離間距離
7p3 最短距離
10、10a、10b ランド(外部端子、電極パッド、外部電極パッド)
10W 引出配線
10c 側面
20 実装基板
21 端子
21a 電極端子
21b 放熱端子
30 配線基板
30a デバイス領域
30b 枠部(外枠)
30c デバイス領域
MC 金属部材
MTF 金属膜
PD パッド(電極パッド、チップ電極)
R1、R2、R3、R4 領域
VL1、VL2 仮想直線
VP1、VP2、VP3、VP4 交点(仮想点)
W1、W2 長さ(円弧距離)
θ1、θ2 角度
Claims (18)
- 複数の電極パッドが形成された表面、および前記表面の反対側に位置する裏面を有する半導体チップと、
前記半導体チップが搭載されているチップ搭載面、前記チップ搭載面の反対側に位置する実装面、前記チップ搭載面に配置され前記半導体チップの前記複数の電極パッドと電気的に接続されている複数の第1パッド、前記実装面に行列状に配置され前記複数の第1パッドと電気的に接続されている複数のランド、前記実装面において、前記半導体チップと厚さ方向に重なる位置に配置される第1導体パターン、および前記実装面を覆う第1絶縁層を有する配線基板と、
を有し、
前記第1絶縁層には、前記複数のランドのそれぞれの一部が露出するように設けられている複数の第1開口部と、前記第1導体パターンの複数個所が露出するように設けられている複数の第2開口部と、が設けられ、
前記第1導体パターンには、複数の第1導体開口部が設けられ、
前記第1導体開口部において、前記第1導体パターンの上層に形成されている第2絶縁層が露出しており、
前記複数の第2開口部のそれぞれの輪郭と、前記複数の第1導体開口部とが、平面視において重なっている半導体装置。 - 請求項1において、
前記実装面において、前記半導体チップと厚さ方向に重なる第1領域の中心と、前記複数の第2開口部のそれぞれの中心と、を通過する仮想直線を第1仮想直線とすると、
前記第1仮想直線と前記複数の第2開口部のそれぞれとの交点のうち前記第1領域の中心側に配置される第1交点には、前記第1導体パターンが配置され、前記第1領域の中心から遠い側に配置される第2交点には、前記第1導体開口部が配置されている半導体装置。 - 請求項2において、
前記複数のランドのそれぞれは、前記チップ搭載面側と前記実装面側とを電気的に接続する層間導電路に向かって形成された引出配線と一体に形成され、
前記複数のランドは、前記第1領域とは異なる第2領域に形成され、
前記複数のランドには、
前記実装面において、前記引出配線が前記実装面の周縁部に向かって配置される第1ランドと、
前記実装面において、前記引出配線が前記第1領域に向かって配置される第2ランドと、が含まれる半導体装置。 - 請求項3において、
前記実装面の最外周に配置されるランドのうちの半分以上が前記第1ランドである半導体装置。 - 請求項4において、
前記複数の第1開口部において、前記複数のランドのそれぞれには、半田ボールが接合されており、
前記複数の第2開口部のそれぞれにおいて、前記第1導体パターンには半田ボールが接合されている半導体装置。 - 請求項5において、
前記複数の第1開口部において、前記複数のランドのそれぞれの側面が前記第1絶縁層から露出している半導体装置。 - 請求項6において、
前記第1導体パターンは、前記第1領域の周縁部を覆うように形成されている半導体装置。 - 請求項7において、
前記実装面には、前記第1領域を囲むように配置される前記第2領域が設けられ、
前記第2領域において、最内周に配置される前記複数のランドのそれぞれは、前記第1領域の中心に向かって前記引出配線が配置されている半導体装置。 - 請求項1において、
前記複数の第1導体開口部のそれぞれの開口面積は、前記複数の第2開口部のそれぞれの開口面積より小さい半導体装置。 - 請求項1において、
前記複数の第1導体開口部のそれぞれは、前記複数の第2開口部のそれぞれの輪郭に沿って延びるように形成されている半導体装置。 - 請求項1において、
前記複数の第1導体開口部のそれぞれは、前記複数の第2開口部の輪郭のそれぞれの1/4以上と重なっている半導体装置。 - 請求項1において、
前記複数の第1導体開口部のそれぞれは、前記複数の第2開口部の輪郭のそれぞれの半分以上と重なっている半導体装置。 - 請求項5において、
前記複数のランドは、前記複数の第1開口部と重なる位置において、前記第1絶縁層から露出する複数の第1露出部を有し、
前記第1導体パターンは、前記複数の第2開口部のそれぞれと重なる位置において、前記第1絶縁層から露出する複数の第2露出部を有し、
前記複数の第1露出部のそれぞれの露出面積は、前記複数の第2露出部のそれぞれの露出面積と同じである半導体装置。 - 請求項5において、
前記複数のランドは、前記複数の第1開口部と重なる位置において、前記第1絶縁層から露出する複数の第1露出部を有し、
前記第1導体パターンは、前記複数の第2開口部のそれぞれと重なる位置において、前記第1絶縁層から露出する複数の第2露出部を有し、
前記複数の第1露出部のそれぞれの形状は、前記複数の第2露出部のそれぞれの形状と同じである半導体装置。 - 請求項5において、
前記複数のランドは、前記複数の第1開口部と重なる位置において、前記第1絶縁層から露出する複数の第1露出部を有し、
前記第1導体パターンは、前記複数の第2開口部のそれぞれと重なる位置において、前記第1絶縁層から露出する複数の第2露出部を有し、
前記複数の第1露出部および前記複数の第2露出部の露出面には、基材である金属部材を覆うように、前記金属部材よりも前記半田ボールに対する濡れ性が高い金属膜が形成されている半導体装置。 - 請求項15において、
前記複数のランドおよび前記第1導体パターンの基材である前記金属部材は、銅(Cu)から成り、
前記金属部材を覆う前記金属膜には、ニッケル(Ni)が含まれる半導体装置。 - 請求項1において、
前記配線基板の前記チップ搭載面には、前記半導体チップと厚さ方向に重なる位置に第2導体パターンが形成されており、
前記第2導体パターンと、前記第1導体パターンとの間には、前記第2導体パターンおよび前記第1導体パターンに接続される複数の層間導体が設けられている半導体装置。 - 請求項1において、
前記第1導体パターンは、前記複数の第2開口部のそれぞれと重なる位置において、前記第1絶縁層から露出する複数の露出部と、前記第1絶縁層に覆われる被覆部とを有し、
前記第1導体パターンが形成される下地絶縁層である第2絶縁層の下地面と前記露出部の側面とが成す第1角度は、前記下地面と前記被覆部の側面とが成す第2角度よりも小さい半導体装置。
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