JP2009283835A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP2009283835A JP2009283835A JP2008136644A JP2008136644A JP2009283835A JP 2009283835 A JP2009283835 A JP 2009283835A JP 2008136644 A JP2008136644 A JP 2008136644A JP 2008136644 A JP2008136644 A JP 2008136644A JP 2009283835 A JP2009283835 A JP 2009283835A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- chip
- semiconductor chip
- semiconductor device
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01043—Technetium [Tc]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
【解決手段】配線基板2と、配線基板2の一面2c側に載置された半導体チップ6と、配線基板の一面2c側に形成され、ボンディングワイヤ8を介して半導体チップ6の電極パッド7に接続される接続パッド3と、配線基板2の他面側に配置されたバンプとを少なくとも備え、半導体チップ6のチップ辺6aが配線基板2の角部2bに向けられるとともに、半導体チップ6の各チップ角部6bが、配線基板2の各外周辺2aに近接して配置されるように半導体チップ6が配置され、配線基板2の一面2c上には半導体チップ6の各チップ辺6aと配線基板2の各角部2bによって囲まれた角部領域2eが設けられるとともに、角部領域2eに接続パッド3が配置されている半導体装置1を採用する。
【選択図】図1
Description
本発明の半導体装置は、4つの外周辺が4つの角部で連結されてなる平面視矩形状の配線基板と、前記配線基板の一面側に載置され、4つのチップ辺が4つのチップ角部で連結されてなる平面視矩形状の半導体チップと、前記配線基板の一面側に形成され、ボンディングワイヤを介して前記半導体チップの電極パッドに接続される接続パッドと、前記配線基板の他面側に格子状に配置された複数のバンプと、前記バンプと前記接続パッドを接続するために前記配線基板に形成された内部配線とを少なくとも具備してなり、前記半導体チップの前記4つのチップ辺が前記配線基板の前記角部に向けられるとともに、前記半導体チップの前記各チップ角部が、前記配線基板の前記各外周辺に近接して配置されるように前記半導体チップが配置され、前記配線基板の一面上には前記半導体チップの各チップ辺と前記配線基板の各角部によって囲まれた角部領域が設けられるとともに、前記角部領域に前記接続パッドが配置されていることを特徴とする。
また、本発明の半導体装置においては、前記半導体チップの一面上に前記チップ辺に沿って複数の前記電極パッドが配列される一方、前記角部領域の複数の前記接続パッドが、前記配線基板の前記角部側に湾曲しつつ半導体チップの前記チップ辺に沿って一列に配列されており、前記の各電極パッドと前記の各接続パッドとを連結する前記の複数のボンディングワイヤが相互に、前記電極パッドから前記接続パッドに向けて扇状に広がるように配線されていることが好ましい。
また、本発明の半導体装置においては、前記半導体チップの一面上に前記チップ辺に沿って複数の前記電極パッドが配列される一方、前記角部領域の複数の前記接続パッドが、前記配線基板の前記角部側に湾曲しつつ半導体チップの前記チップ辺に沿って二列に配列されていることが好ましい。
更に、本発明の半導体装置においては、前記接続パッドが、平面視円弧状に配列されていることが好ましい。
更にまた本発明の半導体装置においては、前記配線基板の前記一面上に、前記半導体チップ、前記角部領域及び前記ボンディングワイヤを封止する封止樹脂が積層されていることが好ましい。
また、本発明の半導体装置の製造方法においては、前記配線基板として、前記複数の前記接続パッドが、前記配線基板の前記角部側に湾曲しつつ前記半導体チップの前記チップ辺の搭載位置に沿って一列に配列された配線基板を用意するとともに、前記半導体チップとして、その一面上に前記チップ辺に沿って複数の前記電極パッドが配列された半導体チップを用意し、前記の各電極パッドと前記の各接続パッドとを複数の前記ボンディングワイヤで接続する際に、各ボンディングワイヤが相互に、前記電極パッドから前記接続パッドに向けて扇状に広がるように配線することが好ましい。
更に、本発明の半導体装置の製造方法においては、前記配線基板として、前記複数の前記接続パッドが、前記配線基板の前記角部側に湾曲しつつ前記半導体チップの前記チップ辺の搭載位置に沿って二列に配列された配線基板を用意するとともに、前記半導体チップとして、その一面上に前記チップ辺に沿って複数の前記電極パッドが配列された半導体チップを用意して、前記の各電極パッドと前記の各接続パッドとを複数の前記ボンディングワイヤで接続することが好ましい。
更にまた、本発明の半導体装置の製造方法においては、前記接続工程と前記バンプ形成工程との間に、前記配線基板の前記一面に、前記半導体チップ及び前記ボンディングワイヤを封止する封止樹脂を積層する工程を行うことが好ましい。
図5は半導体装置の製造方法を示す工程図であり、図6は載置工程を示す図であり、図7は接続工程を示す図であり、図8は封止樹脂の積層工程を示す図であり、図9はバンプ形成工程を示す図であり、図10は、分割工程を示す図である。なお、図5〜図10における(a)は配線母板の平面模式図であり、(b)は(a)のC−C’線〜H−H’線にそれぞれ対応する断面模式図である。
これにより、小スペースで高密度なワイヤ配線が可能となり、ワイヤボンディング工程の処理効率を向上できる。
Claims (9)
- 4つの外周辺が4つの角部で連結されてなる平面視矩形状の配線基板と、前記配線基板の一面側に載置され、4つのチップ辺が4つのチップ角部で連結されてなる平面視矩形状の半導体チップと、前記配線基板の一面側に形成され、ボンディングワイヤを介して前記半導体チップの電極パッドに接続される接続パッドと、前記配線基板の他面側に格子状に配置された複数のバンプと、前記バンプと前記接続パッドを接続するために前記配線基板に形成された内部配線とを少なくとも具備してなり、
前記半導体チップの前記4つのチップ辺が前記配線基板の前記角部に向けられるとともに、前記半導体チップの前記各チップ角部が、前記配線基板の前記各外周辺に近接して配置されるように前記半導体チップが配置され、前記配線基板の一面上には前記半導体チップの各チップ辺と前記配線基板の各角部によって囲まれた角部領域が設けられるとともに、前記角部領域に前記接続パッドが配置されていることを特徴とする半導体装置。 - 前記半導体チップの一面上に前記チップ辺に沿って複数の前記電極パッドが配列される一方、前記角部領域の複数の前記接続パッドが、前記配線基板の前記角部側に湾曲しつつ半導体チップの前記チップ辺に沿って一列に配列されており、前記の各電極パッドと前記の各接続パッドとを連結する前記の複数のボンディングワイヤが相互に、前記電極パッドから前記接続パッドに向けて扇状に広がるように配線されていることを特徴とする請求項1に記載の半導体装置。
- 前記半導体チップの一面上に前記チップ辺に沿って複数の前記電極パッドが配列される一方、前記角部領域の複数の前記接続パッドが、前記配線基板の前記角部側に湾曲しつつ半導体チップの前記チップ辺に沿って二列に配列されていることを特徴とする請求項1に記載の半導体装置。
- 前記接続パッドが、平面視円弧状に配列されていることを特徴とする請求項2または請求項3に記載の半導体装置。
- 前記配線基板の前記一面上に、前記半導体チップ、前記角部領域及び前記ボンディングワイヤを封止する封止樹脂が積層されていることを特徴とする請求項1乃至請求項4の何れか一項に記載の半導体装置。
- 4つの外周辺が4つの角部で連結されてなる平面視矩形状の基板であって、前記基板の一面上の前記角部の近傍に接続パッドが配置されてなる平面視矩形形状の配線基板を用意し、
前記配線基板の前記一面上に、4つのチップ辺が4つのチップ角部で連結されてなる平面視矩形状の半導体チップを、前記4つのチップ辺が前記配線基板の前記角部に向けるとともに、前記各チップ角部が前記配線基板の前記各外周辺に近接するように、前記半導体チップを前記配線基板に載置する載置工程と、
前記半導体チップの電極パッドと前記配線基板の前記接続パッドとをボンディングワイヤによって接続する接続工程と、
前記配線基板の他面に、複数のバンプを格子状に配置して、前記配線基板の内部に形成された内部配線を介して前記バンプを前記接続パッドに接続するバンプ形成工程と、を具備してなることを特徴とする半導体装置の製造方法。 - 前記配線基板として、前記複数の前記接続パッドが、前記配線基板の前記角部側に湾曲しつつ前記半導体チップの前記チップ辺の搭載位置に沿って一列に配列された配線基板を用意するとともに、
前記半導体チップとして、その一面上に前記チップ辺に沿って複数の前記電極パッドが配列された半導体チップを用意し、
前記の各電極パッドと前記の各接続パッドとを複数の前記ボンディングワイヤで接続する際に、各ボンディングワイヤが相互に、前記電極パッドから前記接続パッドに向けて扇状に広がるように配線することを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記配線基板として、前記複数の前記接続パッドが、前記配線基板の前記角部側に湾曲しつつ前記半導体チップの前記チップ辺の搭載位置に沿って二列に配列された配線基板を用意するとともに、
前記半導体チップとして、その一面上に前記チップ辺に沿って複数の前記電極パッドが配列された半導体チップを用意して、
前記の各電極パッドと前記の各接続パッドとを複数の前記ボンディングワイヤで接続することを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記接続工程と前記バンプ形成工程との間に、前記配線基板の前記一面に、前記半導体チップ及び前記ボンディングワイヤを封止する封止樹脂を積層する工程を行うことを特徴とする請求項6乃至請求項8の何れか一項に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008136644A JP2009283835A (ja) | 2008-05-26 | 2008-05-26 | 半導体装置及びその製造方法 |
US12/470,809 US8072069B2 (en) | 2008-05-26 | 2009-05-22 | Semiconductor device and method of manufacturing a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008136644A JP2009283835A (ja) | 2008-05-26 | 2008-05-26 | 半導体装置及びその製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014168480A Division JP2014212356A (ja) | 2014-08-21 | 2014-08-21 | 半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2009283835A true JP2009283835A (ja) | 2009-12-03 |
Family
ID=41341484
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008136644A Ceased JP2009283835A (ja) | 2008-05-26 | 2008-05-26 | 半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8072069B2 (ja) |
JP (1) | JP2009283835A (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7859092B2 (en) * | 2007-01-02 | 2010-12-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structures |
CN102842574A (zh) * | 2012-07-03 | 2012-12-26 | 日月光半导体制造股份有限公司 | 用于堆叠的半导体封装构造 |
JP6815880B2 (ja) * | 2017-01-25 | 2021-01-20 | 株式会社ディスコ | 半導体パッケージの製造方法 |
US11729915B1 (en) * | 2022-03-22 | 2023-08-15 | Tactotek Oy | Method for manufacturing a number of electrical nodes, electrical node module, electrical node, and multilayer structure |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59181653A (ja) * | 1983-03-31 | 1984-10-16 | Toshiba Corp | リ−ドフレ−ム |
JPH1056093A (ja) * | 1996-08-07 | 1998-02-24 | Hitachi Ltd | 半導体装置およびその半導体装置を組み込んだ電子装置 |
JP2002319595A (ja) * | 2001-04-23 | 2002-10-31 | Hitachi Ltd | 半導体装置の製造方法 |
JP2004128290A (ja) * | 2002-10-04 | 2004-04-22 | Renesas Technology Corp | 半導体装置 |
JP2005005440A (ja) * | 2003-06-11 | 2005-01-06 | Renesas Technology Corp | 半導体装置 |
JP2006196615A (ja) * | 2005-01-12 | 2006-07-27 | Sumitomo Metal Electronics Devices Inc | 半導体素子搭載用基板 |
JP2007042761A (ja) * | 2005-08-02 | 2007-02-15 | Matsushita Electric Ind Co Ltd | 半導体装置用基板、半導体装置の製造方法、及び封止金型 |
JP2007165420A (ja) * | 2005-12-12 | 2007-06-28 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2007173655A (ja) * | 2005-12-26 | 2007-07-05 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2008103550A (ja) * | 2006-10-19 | 2008-05-01 | Aoi Electronics Co Ltd | 半導体装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58216494A (ja) | 1982-06-09 | 1983-12-16 | 富士通株式会社 | 電子部品の実装構造 |
US5444303A (en) * | 1994-08-10 | 1995-08-22 | Motorola, Inc. | Wire bond pad arrangement having improved pad density |
JPH09162531A (ja) | 1995-12-08 | 1997-06-20 | Matsushita Electric Ind Co Ltd | ボールグリッドアレイのバンプ配置方法 |
JP2001210749A (ja) | 2000-01-26 | 2001-08-03 | Kyocera Corp | バンプ電極付き配線基板およびその製造方法 |
US6747331B2 (en) * | 2002-07-17 | 2004-06-08 | International Business Machines Corporation | Method and packaging structure for optimizing warpage of flip chip organic packages |
JP2004140079A (ja) | 2002-10-16 | 2004-05-13 | Canon Inc | エリアアレイ型半導体装置とそれを用いた電子回路基板 |
JP2006073625A (ja) | 2004-08-31 | 2006-03-16 | Sharp Corp | 電子部品 |
US7341887B2 (en) * | 2004-10-29 | 2008-03-11 | Intel Corporation | Integrated circuit die configuration for packaging |
JP2007095964A (ja) | 2005-09-28 | 2007-04-12 | Renesas Technology Corp | 半導体装置の製造方法 |
-
2008
- 2008-05-26 JP JP2008136644A patent/JP2009283835A/ja not_active Ceased
-
2009
- 2009-05-22 US US12/470,809 patent/US8072069B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59181653A (ja) * | 1983-03-31 | 1984-10-16 | Toshiba Corp | リ−ドフレ−ム |
JPH1056093A (ja) * | 1996-08-07 | 1998-02-24 | Hitachi Ltd | 半導体装置およびその半導体装置を組み込んだ電子装置 |
JP2002319595A (ja) * | 2001-04-23 | 2002-10-31 | Hitachi Ltd | 半導体装置の製造方法 |
JP2004128290A (ja) * | 2002-10-04 | 2004-04-22 | Renesas Technology Corp | 半導体装置 |
JP2005005440A (ja) * | 2003-06-11 | 2005-01-06 | Renesas Technology Corp | 半導体装置 |
JP2006196615A (ja) * | 2005-01-12 | 2006-07-27 | Sumitomo Metal Electronics Devices Inc | 半導体素子搭載用基板 |
JP2007042761A (ja) * | 2005-08-02 | 2007-02-15 | Matsushita Electric Ind Co Ltd | 半導体装置用基板、半導体装置の製造方法、及び封止金型 |
JP2007165420A (ja) * | 2005-12-12 | 2007-06-28 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2007173655A (ja) * | 2005-12-26 | 2007-07-05 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2008103550A (ja) * | 2006-10-19 | 2008-05-01 | Aoi Electronics Co Ltd | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US8072069B2 (en) | 2011-12-06 |
US20090289361A1 (en) | 2009-11-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8710647B2 (en) | Semiconductor device having a first conductive member connecting a chip to a wiring board pad and a second conductive member connecting the wiring board pad to a land on an insulator covering the chip and the wiring board | |
US7944049B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2012104790A (ja) | 半導体装置 | |
JP5543058B2 (ja) | 半導体装置の製造方法 | |
KR20100069589A (ko) | 반도체 디바이스 | |
USRE45932E1 (en) | Semiconductor device and method of manufacturing the same | |
US8507805B2 (en) | Wiring board for semiconductor devices, semiconductor device, electronic device, and motherboard | |
US8098496B2 (en) | Wiring board for semiconductor device | |
JP2012230981A (ja) | 半導体装置及びその製造方法 | |
KR20140124725A (ko) | 반도체 장치 및 그 제조 방법 | |
US8941237B2 (en) | Semiconductor device | |
JP5501562B2 (ja) | 半導体装置 | |
US20090108471A1 (en) | Wiring board of semiconductor device, semiconductor device, electronic apparatus, mother board, method of manufacturing wiring board of semiconductor device, method of manufacturing mother board and method of manufacturing electronic apparatus | |
JP2009283835A (ja) | 半導体装置及びその製造方法 | |
WO2014203739A1 (ja) | 半導体装置及びその製造方法 | |
JP2010263108A (ja) | 半導体装置及びその製造方法 | |
JP2010010269A (ja) | 半導体装置、半導体装置製造用中間体およびそれらの製造方法 | |
JP2009130048A (ja) | 半導体装置及び電子装置 | |
JP2004128290A (ja) | 半導体装置 | |
US20090189297A1 (en) | Semiconductor device | |
EP3182449A1 (en) | Semiconductor package | |
JP2014212356A (ja) | 半導体装置およびその製造方法 | |
US9117741B2 (en) | Semiconductor device | |
US20120048595A1 (en) | Wiring board and method of manufacturing a semiconductor device | |
JP2013157433A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110309 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120131 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20130731 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20130801 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130905 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20131001 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20131108 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20131217 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20131225 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20140106 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140331 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140422 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140821 |
|
A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20141007 |
|
A912 | Removal of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20141128 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20150327 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20150501 |
|
A045 | Written measure of dismissal of application [lapsed due to lack of payment] |
Free format text: JAPANESE INTERMEDIATE CODE: A045 Effective date: 20151027 |