WO2014103855A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

Info

Publication number
WO2014103855A1
WO2014103855A1 PCT/JP2013/084037 JP2013084037W WO2014103855A1 WO 2014103855 A1 WO2014103855 A1 WO 2014103855A1 JP 2013084037 W JP2013084037 W JP 2013084037W WO 2014103855 A1 WO2014103855 A1 WO 2014103855A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor chip
semiconductor
region
semiconductor device
stacked
Prior art date
Application number
PCT/JP2013/084037
Other languages
English (en)
French (fr)
Inventor
任志 友廣
Original Assignee
ピーエスフォー ルクスコ エスエイアールエル
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ピーエスフォー ルクスコ エスエイアールエル filed Critical ピーエスフォー ルクスコ エスエイアールエル
Priority to US14/655,209 priority Critical patent/US20150333041A1/en
Publication of WO2014103855A1 publication Critical patent/WO2014103855A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H01L23/4926—Bases or plates or solder therefor characterised by the materials the materials containing semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1511—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49131—Assembling to base an electrical component, e.g., capacitor, etc. by utilizing optical sighting device

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device in which a plurality of semiconductor chips are stacked on a wiring board and a manufacturing method thereof.
  • an object of the present invention is to provide a semiconductor device that realizes good wire bonding and a manufacturing method thereof.
  • a semiconductor device includes a wiring board on which a plurality of connection pads are formed, a first semiconductor chip mounted on the wiring board, and a plurality of electrodes that are stacked on the first semiconductor chip.
  • the semiconductor chip has a stacked region overlapping the first semiconductor chip and an overhang region overhanging from the first semiconductor chip, the electrode is formed in the overhang region, and the reinforcing plate is The above-mentioned problem is solved by being stacked on the second semiconductor chip so as to straddle the stacked region and the overhang region of the second semiconductor chip.
  • the method of manufacturing a semiconductor device includes a step of preparing a wiring board on which a plurality of connection pads are formed, a step of mounting a first semiconductor chip on the wiring board, and a second step of forming electrodes. Mounting the second semiconductor chip on the first semiconductor chip such that a part of the semiconductor chip is overhanging from the first semiconductor chip; and the second semiconductor chip overlapping the first semiconductor chip. Mounting a reinforcing plate on the second semiconductor chip so as to straddle the stacked region of the semiconductor chip and the overhang region of the second semiconductor chip overhanging from the first semiconductor chip; The problem described above is solved by including a step of electrically connecting a plurality of connection pads and the plurality of electrodes by wires.
  • a reinforcing plate is stacked on the second semiconductor chip so as to straddle the stacked region and the overhang region of the second semiconductor chip, thereby substantially reducing the overhang region of the second semiconductor chip. Since the thickness can be increased and the rigidity of the overhang region of the second semiconductor chip can be improved, it is formed in the overhang region of the second semiconductor chip without generating chip cracks or unbonded wires. A good load and ultrasonic wave can be applied to the formed electrode, and good wire bonding can be realized.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing the semiconductor device at the position of line A-A ′ in FIG. 1. It is process drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment.
  • FIG. 4 is a process diagram illustrating a manufacturing step of the semiconductor device following that of FIG. 3; It is sectional drawing which shows the semiconductor device of the 1st modification of 1st Embodiment. It is a top view which shows the semiconductor device of the 2nd modification of 1st Embodiment. It is a top view which shows the semiconductor device of the 3rd modification of 1st Embodiment.
  • FIG. 8 is a cross-sectional view showing the semiconductor device at the position of line A-A ′ in FIG. 7. It is process drawing which shows the manufacturing process of the semiconductor device of the 4th modification of 1st Embodiment. It is a top view which shows the semiconductor device which concerns on 2nd Embodiment of this invention.
  • FIG. 11 is a cross-sectional view showing the semiconductor device at the position of line A-A ′ in FIG. 10.
  • the direction parallel to the wiring board is the first direction X
  • the direction orthogonal to the first direction X and parallel to the wiring board is the second direction Y
  • the direction perpendicular to the wiring board is the third direction Z. It prescribes as
  • the semiconductor device 1 of the first embodiment is configured as an MCP type semiconductor device, and as shown in FIGS. 1 and 2, a wiring substrate 10, a first semiconductor chip 20 such as a DRAM memory chip, and a DRAM A second semiconductor chip 30 such as a memory chip, a silicon substrate 40 as a reinforcing plate, a first wire 50, a second wire 51, a sealing resin 60, and an external terminal 70 are provided.
  • the wiring substrate 10 includes an insulating base material 11 made of, for example, glass epoxy and formed in a substantially rectangular plate shape, and a wiring layer ( (Not shown) and an insulating film 12 formed so as to cover the wiring layer.
  • a plurality of connection pads 13 are connected to the wiring layer on one side of the wiring board 10.
  • a plurality of lands 14 are connected to the wiring layer on the other surface side of the wiring board 10. As shown in FIG. 1, the plurality of connection pads 13 are arranged in the vicinity of the peripheral edge of one surface of the wiring board 10. The plurality of lands 14 are arranged in a lattice pattern on the other surface of the wiring board 10. The plurality of connection pads 13 and the plurality of lands 14 are connected to each other by a wiring continuous therewith and vias penetrating the insulating base material 11. Wires 50 and 51 are connected to the connection pad 13, and an external terminal 70 is mounted on the land 14.
  • the insulating film 12 is, for example, a solder resist (SR).
  • the insulating film 12 is formed on the entire surface of the wiring board 10 except for a predetermined region. In other words, the insulating film 12 is partially removed with respect to a predetermined region, and has one or more openings.
  • the opening 15 is formed on one surface side of the wiring substrate 10. The opening 15 exposes a region where the plurality of connection pads 13 are formed and a peripheral region thereof. Also on the other surface side of the wiring substrate 10, openings for exposing the plurality of lands 14 are formed.
  • the first semiconductor chip 20 is formed in a substantially rectangular plate shape, and is mounted on the one surface side of the wiring board 10 with its longitudinal direction aligned with the second direction Y. .
  • the other surface of the first semiconductor chip 20 is bonded and fixed to a region where the insulating film 12 of the wiring substrate 10 is formed by an adhesive member 80 such as DAF (Die Attached Film).
  • the first semiconductor chip 20 has a predetermined circuit (not shown) and a first electrode pad 21 formed on one side thereof. As shown in FIG. 1, the plurality of first electrode pads 21 are arrayed along each short side of the first semiconductor chip 20. As shown in FIG. 1, the first electrode pad 21 and the connection pad 13 are connected by a first wire 50.
  • the second semiconductor chip 30 is formed in a substantially rectangular plate shape, and is laminated on one surface of the first semiconductor chip 20 in a state where the longitudinal direction thereof is along the first direction X. It is installed. As shown in FIG. 1, the second semiconductor chip 30 is arranged so as not to cover the region where the first electrode pad 21 of the first semiconductor chip 20 is formed. As a result, the first direction X Both ends of the second semiconductor chip 30 in the overhang over the first semiconductor chip 20 (that is, protrude). As a result, the second semiconductor chip 30 is formed on both sides of the stacked region 32 overlapping the first semiconductor chip 20 and the stacked region 32 in the first direction X, as shown in FIGS. 1 and 2. An overhang region 33 that overhangs from the semiconductor chip 20 is formed. The other surface of the second semiconductor chip 30 is bonded and fixed to the first semiconductor chip 20 by an adhesive member 80 such as DAF.
  • an adhesive member 80 such as DAF.
  • the second semiconductor chip 30 has a predetermined circuit (not shown) and a second electrode pad 31 formed on one side thereof.
  • the plurality of second electrode pads 31 are arranged along the respective short sides of the second semiconductor chip 30 (overhang region 33).
  • the second electrode pads 31 and the connection pads 13 are illustrated in FIG. As shown in FIG. 2, they are connected by the second wire 51.
  • Two silicon substrates 40 are stacked on the second semiconductor chip 30 as shown in FIGS. 1 and 2.
  • One of the silicon substrates 40 is stacked on the second semiconductor chip 30 so as to straddle the stacked region 32 and one of the overhang regions 33.
  • the other of the silicon substrates 40 is stacked on the second semiconductor chip 30 so as to straddle the stacked region 32 and the other of the overhang regions 33.
  • the silicon substrate 40 is bonded and fixed to the second semiconductor chip 30 by an adhesive member 80 such as DAF.
  • the first wire 50 is made of a conductive metal such as Au, and is connected to the first electrode pad 21 and the connection pad 13.
  • the second wire 51 is made of a conductive metal such as Au, and connects the second electrode pad 31 and the connection pad 13.
  • the sealing resin 60 is made of an insulating resin such as an epoxy resin. As shown in FIG. 2, the first semiconductor chip 20, the second semiconductor chip 30, and the first wire 50 are formed on one side of the wiring substrate 10. And the second wire 51 and one surface of the wiring substrate 10 are covered.
  • the external terminal 70 is configured as a solder ball and is mounted on the land 14 of the wiring board 10.
  • the specific form of the external terminal 70 may be other than the solder ball.
  • FIG. 3A shows a wiring motherboard 10a including a plurality of product formation regions R partitioned by dicing lines L.
  • FIG. These product formation regions R are regions that are later cut individually along the dicing line L to become the wiring substrate 10.
  • an insulating film 12, a connection pad 13, a land 14 and an opening 15 are formed in each product formation region R.
  • the first semiconductor chip 20 and the second semiconductor chip 30 are sequentially mounted on one surface of the wiring board 10 (wiring mother board 10a).
  • the first semiconductor chip 20 is bonded and fixed to one surface of the wiring substrate 10 (wiring mother substrate 10a) by an adhesive member 80 such as DAF provided on the other surface of the first semiconductor chip 20.
  • the second semiconductor chip 30 is bonded and fixed to one surface of the first semiconductor chip 20 by an adhesive member 80 such as DAF provided on the other surface of the second semiconductor chip 30.
  • two silicon substrates 40 are mounted on one surface of the second semiconductor chip 30.
  • the silicon substrate 40 is bonded and fixed to one surface of the second semiconductor chip 30 by an adhesive member 80 such as DAF provided on the other surface of the silicon substrate 40.
  • one of the silicon substrates 40 is stacked on the second semiconductor chip 30 so as to straddle the stacked region 32 and one of the overhang regions 33 as shown in FIG. Is stacked on the second semiconductor chip 30 so as to straddle the stacked region 32 and the other of the overhang regions 33.
  • the second wire 51 is used to connect the connection pads 13 of the wiring board 10 (wiring mother board 10a) and the second electrode pads 31 of the second semiconductor chip 30. Are electrically connected. Similarly, the connection pads 13 of the wiring board 10 (wiring mother board 10a) and the first electrode pads 21 of the first semiconductor chip 20 are electrically connected using the first wires 50.
  • a wire bonding apparatus (not shown) can be used for connection using the wires 50 and 51.
  • the connection is performed by, for example, ball bonding using an ultrasonic thermocompression bonding method.
  • the tips of the wires 50 and 51 in which balls are formed by melting are ultrasonically thermocompression bonded onto the electrode pads 21 and 31 so that the wires 50 and 51 draw a predetermined loop shape.
  • the rear end is ultrasonically thermocompression-bonded on the corresponding connection pad 13.
  • the wiring substrate 10 (wiring mother substrate 10a) on which the first semiconductor chip 20, the second semiconductor chip 30, and the silicon substrate 40 are mounted is collectively molded.
  • the sealing resin 60 is formed.
  • a transfer mold apparatus (not shown) provided with an upper mold (not shown), a lower mold (not shown) and the like is used.
  • this collective mold is configured such that the wiring board 10 (wiring mother board 10a) that has undergone the die bonding process and the wire bonding process is placed in a space formed by an upper mold (not shown) and a lower mold (not shown). It is performed by arranging and allowing a thermosetting epoxy resin or the like to flow into the space.
  • external terminals 70 are mounted on the lands 14 provided on the other surface side of the wiring board 10 (wiring mother board 10a).
  • the mounting of the external terminal 70 can be performed using, for example, a suction mechanism (not shown) provided with a plurality of suction holes (not shown) arranged corresponding to the plurality of lands 14.
  • a suction mechanism not shown
  • a flux is transferred and formed on the held external terminals 70, and are collectively mounted on the land 14.
  • the connection between the external terminal 70 and the land 14 is fixed by reflow processing.
  • a wiring board 10 (wiring mother board) is used using a dicing blade (not shown). 10a) and the sealing resin 60 are cut along the dicing line L. Thereby, the wiring board 10 (wiring mother board 10a) is separated into pieces for each product formation region R, and then the separated wiring board 10 (wiring mother board 10a) and the sealing resin 60 are diced into tapes ( By picking up from (not shown), a semiconductor device 1 as shown in FIGS. 1 and 2 is obtained.
  • the silicon substrate 40 is placed on the second semiconductor chip 30 so as to straddle the stacked region 32 and the overhang region 33 of the second semiconductor chip 30.
  • the substantial thickness of the overhang region 33 of the second semiconductor chip 30 can be increased, and the rigidity of the overhang region 33 of the second semiconductor chip 30 can be improved. Without causing cracks or unbonded wires, it is possible to satisfactorily apply a load or an ultrasonic wave to the second electrode pad 31 formed in the overhang region 33 of the second semiconductor chip 30 and realize a good wire bonding. .
  • the second semiconductor chip 30 since it is not necessary to set the second semiconductor chip 30 thick in order to suppress chip cracks and the like, the second semiconductor chip 30 can be thinned.
  • the silicon substrate 40 in the third direction Z is required. Is set within the range of the height of the wire loop 51a and the resin in the third direction Z, the installation of the silicon substrate 40 does not affect the thickness of the semiconductor device 1 in the third direction Z. .
  • one surface of the silicon substrate 40 facing the side opposite to the second semiconductor chip 30 side is covered with the sealing resin 60.
  • one surface of the silicon substrate 40 facing the side opposite to the second semiconductor chip 30 side is covered with a sealing resin 60. Not exposed to the outside.
  • the thickness of the semiconductor device 1 in the third direction Z can be reduced, and the heat dissipation of the semiconductor device 1 can be improved.
  • the silicon substrate 40 is second so that both ends of the silicon substrate 40 in the second direction Y overhang from the second semiconductor chip 30. It is mounted on the semiconductor chip 30. That is, as shown in FIG. 6, the silicon substrate 40 has an overhang region 42 that overhangs from the second semiconductor chip 30 in the second direction Y.
  • the adhesion area between the silicon substrate 40 and the second semiconductor chip 30 can be increased, and the rigidity of the overhang region 33 of the second semiconductor chip 30 is further increased. It can be improved.
  • one silicon substrate 40 is disposed on the second semiconductor chip 30 as shown in FIGS. Specifically, the silicon substrate 40 is stacked on the second semiconductor chip 30 so as to straddle the stacked region 32 and a pair of overhang regions 33 formed on both sides of the stacked region 32.
  • the bonding area between the silicon substrate 40 and the second semiconductor chip 30 can be increased, and the rigidity of the overhang region 33 of the second semiconductor chip 30 is further increased. It can be improved. Further, compared to the first embodiment using two silicon substrates 40, only one silicon substrate 40 is required, so that manufacturing efficiency can be improved.
  • a semiconductor wafer on which a plurality of second semiconductor chips 30 are formed is prepared.
  • An adhesive member 80 is fixed to the semiconductor wafer, and a dicing tape T is attached to the semiconductor wafer, and a second electrode pad 31 is formed in advance at a predetermined location.
  • the stacked region 32 (more precisely, the portion that is to become the stacked region 32) and the overhang region 33 (more precisely, the overhang region 33) of the second semiconductor chip 30
  • a plurality of silicon substrates 40 are mounted at predetermined positions so as to straddle the planned portion).
  • the semiconductor wafer on which the plurality of second semiconductor chips 30 are formed is cut along the dicing line L.
  • the chip stacking process of the semiconductor device 1 can be simplified by mounting the silicon substrate 40 at the semiconductor wafer stage as compared with the case of the first embodiment.
  • the silicon substrate 40 is configured as a third semiconductor chip 40 such as a flash memory chip on which a predetermined circuit is formed.
  • a plurality of third electrode pads 41 are formed on the third semiconductor chip 40, and these third electrode pads 41 are connected to the connection pads 13 by the third wires 52. Electrically connected.
  • the same arrangement as that in the first embodiment can be achieved by simply changing the stacked arrangement of the plurality of semiconductor chips 20, 30, and 40. An effect is obtained, and the wire bonding property in the overhang region 33 of the second semiconductor chip 30 can be improved without arranging a new silicon substrate 40.
  • one of the two overhang regions 33 of the second semiconductor chip 30 (the overhang region 33 on the left side of the drawing in FIGS. 10 and 11).
  • the overhang amount from the first semiconductor chip 20 in the first direction X is set small. In this way, when the overhang amount from the first semiconductor chip 20 is small, the problem of wire bonding is small, so in the second embodiment, the other of the two overhang regions 33 (FIG. 10).
  • the third semiconductor chip 40 is mounted only on the overhang region 33) on the right side of the drawing.
  • the second semiconductor chip 30 may be mounted on the first semiconductor chip 20 so that only the portion overhangs from the first semiconductor chip 20.
  • the silicon substrate is stacked and mounted on the overhang region of the upper semiconductor chip.
  • any material may be used as long as it has a thermal expansion coefficient similar to that of the silicon substrate.
  • SYMBOLS 1 Semiconductor device 10 ... Wiring board 10a ... Wiring mother board 11 ... Insulating base material 12 ... Insulating film 13 ... Connection pad 14 ... Land 15 ... Opening 20 First semiconductor chip 21 First electrode pad 30 Second semiconductor chip 31 Second electrode pad 32 Laminated region 33 Overhang region 40 .. Silicon substrate (reinforcing plate, third semiconductor chip) 41 ... 3rd electrode pad 42 ... Overhang area 50 ... 1st wire 51 ... 2nd wire 51a ... Wire loop 52 ... 3rd wire 60 ...

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

　複数の接続パッド１３が形成された配線基板１０と、配線基板１０上に搭載された第１の半導体チップ２０と、第１の半導体チップ２０上に積層され、複数の電極３１を有する第２の半導体チップ３０と、第２の半導体チップ３０上に積層された補強板４０と、複数の接続パッド１３と複数の電極３１とを電気的に接続する複数のワイヤとを備え、第２の半導体チップ３０は、第１の半導体チップ２０に重なる積層領域３２と、第１の半導体チップ２０からオーバーハングするオーバーハング領域３３とを有し、電極３１は、オーバーハング領域３３に形成され、補強板４０は、第２の半導体チップ３０の積層領域３２とオーバーハング領域３３とに跨るように、第２の半導体チップ３０上に積層されている半導体装置１。

Description

半導体装置およびその製造方法
　本発明は、半導体装置およびその製造方法に関し、特に、配線基板上に複数の半導体チップが積層された半導体装置およびその製造方法に関する。
　従来、複数の半導体チップを搭載したＭＣＰ（Ｍｕｌｔｉ　Ｃｈｉｐ　Ｐａｃｋａｇｅ）半導体装置において、上段の半導体チップのオーバーハング領域をバンプやワイヤによって支える構成が知られている（例えば、特許文献１乃至特許文献３参照。）。
特開２００９－０９９６９７号公報 特開２００９－１９４１８９号公報 特開２０１１－０８６９４３号公報
　ところが、携帯機器の小型・薄型化により、半導体装置の薄型化が進んでおり、半導体装置に搭載される半導体チップを薄型化する必要が出てきている。そして、上段の半導体チップの厚さが薄くなると、上記従来技術では、上段の半導体チップのオーバーハング領域に形成された電極をワイヤボンディングする際の荷重をバンプやワイヤで支えられず、良好にワイヤ接続できなくなる恐れがある、という問題があった。
　そこで、本発明は、従来の問題を解決するものであって、すなわち、本発明の目的は、良好なワイヤボンディングを実現する半導体装置およびその製造方法を提供することである。
　本発明の半導体装置は、複数の接続パッドが形成された配線基板と、前記配線基板上に搭載された第１の半導体チップと、前記第１の半導体チップ上に積層され、複数の電極を有する第２の半導体チップと、前記第２の半導体チップ上に積層された補強板と、前記複数の接続パッドと前記複数の電極とを電気的に接続する複数のワイヤとを備え、前記第２の半導体チップは、前記第１の半導体チップに重なる積層領域と、前記第１の半導体チップからオーバーハングするオーバーハング領域とを有し、前記電極は、前記オーバーハング領域に形成され、前記補強板は、前記第２の半導体チップの前記積層領域と前記オーバーハング領域とに跨るように、前記第２の半導体チップ上に積層されていることにより、前述した課題を解決したものである。
　本発明の半導体装置の製造方法は、複数の接続パッドが形成された配線基板を用意する工程と、前記配線基板上に第１の半導体チップを搭載する工程と、電極が形成された第２の半導体チップの一部分を前記第１の半導体チップからオーバーハングさせるように、前記第２の半導体チップを前記第１の半導体チップ上に搭載する工程と、前記第１の半導体チップに重なる前記第２の半導体チップの積層領域と、前記第１の半導体チップからオーバーハングする前記第２の半導体チップのオーバーハング領域とに跨るように、前記第２の半導体チップ上に補強板を搭載する工程と、前記複数の接続パッドと前記複数の電極とをワイヤによって電気的に接続する工程とを含むことにより、前述した課題を解決したものである。
　本発明では、第２の半導体チップの積層領域とオーバーハング領域とに跨るように、第２の半導体チップ上に補強板を積層することにより、第２の半導体チップのオーバーハング領域の実質的な厚さを厚くし、第２の半導体チップのオーバーハング領域の剛性を向上させることが可能であるため、チップクラックやワイヤ未接合を発生させることなく、第２の半導体チップのオーバーハング領域に形成された電極に荷重や超音波を良好に印加でき、良好なワイヤボンディングを実現できる。
本発明の第１実施形態に係る半導体装置を示す平面図である。 図１のＡ－Ａ’線位置において半導体装置を示す断面図である。 第１実施形態の半導体装置の製造工程を示す工程図である。 図３に続く半導体装置の製造工程を示す工程図である。 第１実施形態の第１変形例の半導体装置を示す断面図である。 第１実施形態の第２変形例の半導体装置を示す平面図である。 第１実施形態の第３変形例の半導体装置を示す平面図である。 図７のＡ－Ａ’線位置において半導体装置を示す断面図である。 第１実施形態の第４変形例の半導体装置の製造工程を示す工程図である。 本発明の第２実施形態に係る半導体装置を示す平面図である。 図１０のＡ－Ａ’線位置において半導体装置を示す断面図である。
　以下、本発明の半導体装置の複数の実施形態および変形例を図面に基づいて説明する。
　なお、以下の説明では、配線基板に平行な方向を第１方向Ｘ、第１方向Ｘに直交し且つ配線基板に平行な方向を第２方向Ｙ、配線基板に垂直な方向を第３方向Ｚとして規定する。
　以下、本発明の第１実施形態である半導体装置１を図１乃至図４に基づいて説明する。
　第１実施形態の半導体装置１は、ＭＣＰ型の半導体装置として構成され、図１および図２に示すように、配線基板１０と、ＤＲＡＭのメモリチップ等の第１の半導体チップ２０と、ＤＲＡＭのメモリチップ等の第２の半導体チップ３０と、補強板としてのシリコン基板４０と、第１のワイヤ５０と、第２のワイヤ５１と、封止樹脂６０と、外部端子７０とを備えている。
　配線基板１０は、図１および図２に示すように、例えばガラスエポキシから形成され略四角形の板状に形成された絶縁基材１１と、絶縁基材１１の両面にパターン形成された配線層（図示しない）と、配線層を覆うように形成された絶縁膜１２とを有している。
　配線基板１０の一面側の配線層には、複数の接続パッド１３が接続形成されている。また、配線基板１０の他面側の配線層には、複数のランド１４が接続形成されている。複数の接続パッド１３は、図１に示すように、配線基板１０の一面の周縁部近傍に配列形成されている。また、複数のランド１４は、配線基板１０の他面に格子状に配置されている。複数の接続パッド１３と複数のランド１４とは、それらに連続する配線と絶縁基材１１を貫くビア等により互いに接続されている。接続パッド１３には、ワイヤ５０、５１が接続され、ランド１４には、外部端子７０が搭載される。
　絶縁膜１２は、例えばソルダーレジスト（ＳＲ）である。絶縁膜１２は、予め定められた所定の領域を除いて配線基板１０の両面全面に形成される。換言すると、絶縁膜１２は、その一部が所定の領域に関して除去されており、一つ以上の開口部を有している。例えば、配線基板１０の一面側には、開口部１５が形成される。開口部１５は、複数の接続パッド１３が形成された領域およびその周辺領域を露出させる。配線基板１０の他面側においても、複数のランド１４をそれぞれ露出させる開口部が形成される。
　第１の半導体チップ２０は、図１に示すように、略長方形の板状に形成され、その長手方向を第２方向Ｙに沿わせた状態で、配線基板１０の一面側に搭載されている。第１の半導体チップ２０の他面は、ＤＡＦ（Ｄｉｅ　Ａｔｔａｃｈｅｄ　Ｆｉｌｍ）等の接着部材８０によって、配線基板１０の絶縁膜１２が形成されている領域に接着固定されている。
　第１の半導体チップ２０は、その一面側に所定の回路（図示しない）および第１の電極パッド２１が形成されている。複数の第１の電極パッド２１は、図１に示すように、第１の半導体チップ２０の各短辺に沿って配列形成されている。第１の電極パッド２１と接続パッド１３とは、図１に示すように、第１のワイヤ５０により接続されている。
　第２の半導体チップ３０は、図１に示すように、略長方形の板状に形成され、その長手方向を第１方向Ｘに沿わせた状態で、第１の半導体チップ２０の一面上に積層搭載されている。第２の半導体チップ３０は、図１に示すように、第１の半導体チップ２０の第１の電極パッド２１が形成された領域を覆うことがないように配置され、その結果、第１方向Ｘにおける第２の半導体チップ３０の両端は、第１の半導体チップ２０に対して外側にオーバーハングする（すなわち、はみ出す）。これにより、第２の半導体チップ３０には、図１や図２に示すように、第１の半導体チップ２０に重なる積層領域３２と、第１方向Ｘにおける積層領域３２の両側に形成され第１の半導体チップ２０からオーバーハングするオーバーハング領域３３とが形成される。第２の半導体チップ３０の他面は、ＤＡＦ等の接着部材８０により第１の半導体チップ２０に接着固定される。
　第２の半導体チップ３０は、その一面側に所定の回路（図示しない）および第２の電極パッド３１が形成されている。複数の第２の電極パッド３１は、第２の半導体チップ３０（オーバーハング領域３３）の各短辺に沿って配列形成され、第２の電極パッド３１と接続パッド１３とは、図１や図２に示すように、第２のワイヤ５１により接続されている。
　シリコン基板４０は、図１や図２に示すように、第２の半導体チップ３０上に２つ積層されている。シリコン基板４０の一方は、積層領域３２とオーバーハング領域３３の一方とに跨るように、第２の半導体チップ３０上に積層されている。シリコン基板４０の他方は、積層領域３２とオーバーハング領域３３の他方とに跨るように、第２の半導体チップ３０上に積層されている。シリコン基板４０は、ＤＡＦ等の接着部材８０により第２の半導体チップ３０に接着固定される。
　第１のワイヤ５０は、例えばＡｕ等の導電性金属から成り、第１の電極パッド２１と接続パッド１３と接続する。第２のワイヤ５１は、例えばＡｕ等の導電性金属から成り、第２の電極パッド３１と接続パッド１３とを接続する。
　封止樹脂６０は、エポキシ樹脂等の絶縁性樹脂から成り、図２に示すように、配線基板１０の一面側において、第１の半導体チップ２０と第２の半導体チップ３０と第１のワイヤ５０と第２のワイヤ５１と配線基板１０の一面とを覆っている。
　外部端子７０は、本実施形態では、はんだボールとして構成され、配線基板１０のランド１４に搭載されている。なお、外部端子７０の具体的態様は、はんだボール以外であってもよい。
　つぎに、第１実施形態における半導体装置１の製造方法について、図３および図４に基づいて以下に説明する。
　まず、図３（ａ）には、ダイシングラインＬによって区画された複数の製品形成領域Ｒを含む配線母基板１０ａが示されている。これら製品形成領域Ｒは、後にダイシングラインＬに沿って個々に切断され配線基板１０となる領域である。各製品形成領域Ｒには、絶縁膜１２、接続パッド１３、ランド１４、および、開口部１５が、形成されている。
　次に、図３（ｂ）に示すように、配線基板１０（配線母基板１０ａ）の一面上に、第１の半導体チップ２０および第２の半導体チップ３０を順番に搭載する。第１の半導体チップ２０は、第１の半導体チップ２０の他面に設けられたＤＡＦ等の接着部材８０によって、配線基板１０（配線母基板１０ａ）の一面に接着固定される。同様に、第２の半導体チップ３０は、第２の半導体チップ３０の他面に設けられたＤＡＦ等の接着部材８０によって、第１の半導体チップ２０の一面に接着固定される。
　次に、図３（ｃ）に示すように、第２の半導体チップ３０の一面上に、２つのシリコン基板４０を搭載する。シリコン基板４０は、シリコン基板４０の他面に設けられたＤＡＦ等の接着部材８０によって、第２の半導体チップ３０の一面に接着固定される。
　この際、シリコン基板４０の一方は、図３（ｃ）に示すように、積層領域３２とオーバーハング領域３３の一方とに跨るように、第２の半導体チップ３０上に積層され、シリコン基板４０の他方は、積層領域３２とオーバーハング領域３３の他方とに跨るように、第２の半導体チップ３０上に積層される。
　次に、図３（ｄ）に示すように、第２のワイヤ５１を用いて、配線基板１０（配線母基板１０ａ）の接続パッド１３と第２の半導体チップ３０の第２の電極パッド３１とを電気的に接続する。また、同様に、第１のワイヤ５０を用いて、配線基板１０（配線母基板１０ａ）の接続パッド１３と第１の半導体チップ２０の第１の電極パッド２１とを電気的に接続する。
　この際、ワイヤ５０、５１を用いた結線には、図示しないワイヤボンディング装置を用いることができる。結線は、例えば、超音波熱圧着法を用いたボールボンディングにより行われる。具体的には、溶融によりボールが形成されたワイヤ５０、５１の先端を電極パッド２１、３１上に超音波熱圧着し、ワイヤ５０、５１が所定のループ形状を描くように、ワイヤ５０、５１の後端を対応する接続パッド１３上に超音波熱圧着する。
　次に、図４（ａ）に示すように、第１の半導体チップ２０や第２の半導体チップ３０やシリコン基板４０を搭載した配線基板１０（配線母基板１０ａ）に、一括モールドを施すことによって、封止樹脂６０を形成する。この一括モールドには、上型（図示しない）および下型（図示しない）等を備えたトランスファーモールド装置（図示しない）が用いられる。具体的には、この一括モールドは、上型（図示しない）および下型（図示しない）によって形成される空間内に、ダイボンディング工程およびワイヤボンディング工程を経た配線基板１０（配線母基板１０ａ）を配置し、前記空間内に熱硬化性のエポキシ樹脂等を流入させることによって行われる。
　次に、図４（ｂ）に示すように、配線基板１０（配線母基板１０ａ）の他面側に設けられたランド１４にそれぞれ外部端子７０を搭載する。この外部端子７０の搭載は、例えば、複数のランド１４に対応して配列形成された複数の吸着孔（図示しない）を備えた吸着機構（図示しない）を用いて行うことができる。この場合、複数の外部端子７０を吸着機構（図示しない）に吸着保持させ、保持された外部端子７０にフラックスを転写形成して、ランド１４に一括搭載する。その後、リフロー処理により、外部端子７０とランド１４との間を接続固定する。
　次に、図４（ｃ）に示すように、封止樹脂６０にダイシングテープ（図示しない）を貼り付けて支持した状態で、ダイシングブレード（図示しない）を用いて、配線基板１０（配線母基板１０ａ）および封止樹脂６０をダイシングラインＬに沿って切断する。これにより、配線基板１０（配線母基板１０ａ）は、製品形成領域Ｒ毎に個片化され、その後、個片化された配線基板１０（配線母基板１０ａ）および封止樹脂６０をダイシングテープ（図示しない）からピックアップすることで、図１および図２に示すような半導体装置１が得られる。
　このようにして得られた第１実施形態の半導体装置１では、第２の半導体チップ３０の積層領域３２とオーバーハング領域３３とに跨るように、第２の半導体チップ３０上にシリコン基板４０を積層することにより、第２の半導体チップ３０のオーバーハング領域３３の実質的な厚さを厚くし、第２の半導体チップ３０のオーバーハング領域３３の剛性を向上させることが可能であるため、チップクラックやワイヤ未接合を発生させることなく、第２の半導体チップ３０のオーバーハング領域３３に形成された第２の電極パッド３１に荷重や超音波を良好に印加でき、良好なワイヤボンディングを実現できる。
　また、チップクラック等の抑制の為に第２の半導体チップ３０を厚く設定する必要がなくなるため、第２の半導体チップ３０の薄型化を実現できる。
　なお、第２のワイヤ５１のワイヤループ５１ａの形成、および、信頼性確保のための第２のワイヤ５１上の樹脂の厚さを確保する必要があることから、第３方向Ｚにおけるシリコン基板４０の厚みが、第３方向Ｚにおけるワイヤループ５１ａおよび樹脂の高さの範囲内で設定されていれば、シリコン基板４０の設置が第３方向Ｚにおける半導体装置１の厚みに影響を及ぼすことはない。
　つぎに、本発明の第１実施形態の第１変形例である半導体装置１について、図５に基づいて説明する。以下では、第１実施形態との相違点のみを説明する。
　上述した第１実施形態では、図２に示すように、第２の半導体チップ３０側とは反対側に面するシリコン基板４０の一面は、封止樹脂６０によって覆われている。
　これに対して、第１実施形態の第１変形例では、図５に示すように、第２の半導体チップ３０側とは反対側に面するシリコン基板４０の一面は、封止樹脂６０によって覆われておらず、外部に露出している。
　これにより、第１実施形態の第１変形例では、第３方向Ｚにおける半導体装置１の厚みを低減できるとともに、半導体装置１の放熱性を向上できる。
　つぎに、本発明の第１実施形態の第２変形例である半導体装置１について、図６に基づいて説明する。以下では、第１実施形態との相違点のみを説明する。
　第１実施形態の第２変形例では、図６に示すように、第２方向Ｙにおけるシリコン基板４０の両端が、第２の半導体チップ３０からオーバーハングするように、シリコン基板４０が第２の半導体チップ３０に搭載されている。すなわち、シリコン基板４０は、図６に示すように、第２方向Ｙに向けて第２の半導体チップ３０からオーバーハングするオーバーハング領域４２を有している。
　これにより、第１実施形態の第２変形例では、シリコン基板４０と第２の半導体チップ３０との接着面積を増大することができ、第２の半導体チップ３０のオーバーハング領域３３の剛性を一層向上できる。
　つぎに、本発明の第１実施形態の第３変形例である半導体装置１について、図７および図８に基づいて説明する。以下では、第１実施形態との相違点のみを説明する。
　第１実施形態の第３変形例では、図７や図８に示すように、シリコン基板４０は、第２の半導体チップ３０上に１つ配置されている。具体的には、シリコン基板４０は、積層領域３２と、積層領域３２の両側に形成された一対のオーバーハング領域３３とに跨るように、第２の半導体チップ３０上に積層されている。
　これにより、第１実施形態の第３変形例では、シリコン基板４０と第２の半導体チップ３０との接着面積を増大することができ、第２の半導体チップ３０のオーバーハング領域３３の剛性を一層向上できる。また、２つのシリコン基板４０を用いた第１実施形態と比較して、１つのシリコン基板４０で済むため、製造効率を向上できる。
　つぎに、本発明の第１実施形態の第４変形例である半導体装置１について、図９に基づいて説明する。以下では、第１実施形態との相違点のみを説明する。
　上述した第１実施形態では、図３（ｂ）および図３（ｃ）に示すように、個片化された第２の半導体チップ３０を第１の半導体チップ２０上に搭載した後、シリコン基板４０を第２の半導体チップ３０上に搭載するものとして説明した。
　これに対して、第１実施形態の第４変形例では、まず、図９（ａ）に示すように、複数の第２の半導体チップ３０が形成された半導体ウェハを用意する。この半導体ウェハには、接着部材８０が固着されるとともに、ダイシングテープＴが貼り付けてあり、また、所定箇所に第２の電極パッド３１が予め形成されている。
　次に、図９（ｂ）に示すように、第２の半導体チップ３０の積層領域３２（正確には積層領域３２となる予定の部分）とオーバーハング領域３３（正確にはオーバーハング領域３３となる予定の部分）とに跨るように、複数のシリコン基板４０を所定箇所に搭載する。
　次に、図９（ｃ）に示すように、複数の第２の半導体チップ３０が形成された半導体ウェハを、ダイシングラインＬに沿って切断する。
　次に、図９（ｄ）に示すように、ダイシングテープＴから、各第２の半導体チップ３０をピックアップすることで、シリコン基板４０が搭載された第２の半導体チップ３０が複数得られる。
　これにより、第１実施形態の第４変形例では、半導体ウェハ段階でシリコン基板４０を搭載することにより、第１実施形態の場合と比較して、半導体装置１のチップ積層工程を簡略化できる。
　つぎに、本発明の第２実施形態である半導体装置１について、図１０および図１１に基づいて説明する。以下では、第１実施形態との相違点のみを説明する。
　第２実施形態では、シリコン基板４０が、所定の回路が形成されたＦｌａｓｈのメモリチップ等の第３の半導体チップ４０として構成されている。
　第３の半導体チップ４０には、図１０や図１１に示すように、複数の第３の電極パッド４１が形成され、これら第３の電極パッド４１は、第３のワイヤ５２によって接続パッド１３に電気的に接続されている。
　このように、３つ以上の半導体チップ２０、３０、４０を搭載した半導体装置１では、複数の半導体チップ２０、３０、４０の積層配置を変更するだけで、第１実施形態の場合と同様の効果が得られ、新たなシリコン基板４０を配置することなく、第２の半導体チップ３０のオーバーハング領域３３におけるワイヤボンディング性を向上できる。
　なお、第２実施形態では、図１０や図１１に示すように、第２の半導体チップ３０の２つのオーバーハング領域３３のうち一方（図１０および図１１では図面左側のオーバーハング領域３３）の、第１方向Ｘにおける第１の半導体チップ２０からのオーバーハング量が小さく設定されている。そして、このように、第１の半導体チップ２０からのオーバーハング量が小さい場合には、ワイヤボンディング性の問題が少ないため、第２実施形態では、２つのオーバーハング領域３３のうち他方（図１０および図１１では図面右側のオーバーハング領域３３）上のみに、第３の半導体チップ４０が搭載されている。
　なお、上記では、第１方向Ｘにおける第２の半導体チップ３０の両端が第１の半導体チップ２０からオーバーハングする例を説明したが、第１方向Ｘにおける第２の半導体チップ３０の一方の端部のみが第１の半導体チップ２０からオーバーハングするように、第２の半導体チップ３０を第１の半導体チップ２０上に搭載してもよい。
　以上、本発明者によってなされた発明を実施形態および変形例に基づき説明したが、本発明は上記実施形態や変形例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。
　例えば、上述した各実施形態および各変形例を適宜組み合わせて実施してもよい。
　また、上記では、長方形状で短辺にそれぞれ複数の電極パッドが配置された複数の半導体チップをクロス積層する半導体装置のオーバーハング領域にシリコン基板を積層した場合について説明したが、上段の半導体チップが下段の半導体チップからオーバーハングする構成の半導体装置であればどのような半導体装置に適用してもよい。
　また、上記では、上段の半導体チップのオーバーハング領域にシリコン基板を積層搭載する場合について説明したが、シリコン基板と同様な熱膨張係数を有する材料であればどのような材料を用いてもよい。
　また、上記では、２段のメモリチップ、或いは、２段のＤＲＡＭのメモリチップとＦｌａｓｈのメモリチップを積層した半導体装置に適用した場合について説明したが、上段の半導体チップが下段の半導体チップからオーバーハングする構成であれば、ロジックチップとメモリチップ等、どのような半導体装置の組合せでもよい。
　　１　　・・・　半導体装置
　１０　　・・・　配線基板
　１０ａ　・・・　配線母基板
　１１　　・・・　絶縁基材
　１２　　・・・　絶縁膜
　１３　　・・・　接続パッド
　１４　　・・・　ランド
　１５　　・・・　開口部
　２０　　・・・　第１の半導体チップ
　２１　　・・・　第１の電極パッド
　３０　　・・・　第２の半導体チップ
　３１　　・・・　第２の電極パッド
　３２　　・・・　積層領域
　３３　　・・・　オーバーハング領域
　４０　　・・・　シリコン基板（補強板、第３の半導体チップ）
　４１　　・・・　第３の電極パッド
　４２　　・・・　オーバーハング領域
　５０　　・・・　第１のワイヤ
　５１　　・・・　第２のワイヤ
　５１ａ　・・・　ワイヤループ
　５２　　・・・　第３のワイヤ
　６０　　・・・　封止樹脂
　７０　　・・・　外部端子
　８０　　・・・　接着部材
　Ｌ　　　・・・　ダイシングライン
　Ｒ　　　・・・　製品形成領域
　Ｔ　　　・・・　ダイシングテープ
　Ｘ　　　・・・　第１方向
　Ｙ　　　・・・　第２方向
　Ｚ　　　・・・　第３方向

Claims (10)

  1. 　複数の接続パッドが形成された配線基板と、
    　前記配線基板上に搭載された第１の半導体チップと、
    　前記第１の半導体チップ上に積層され、複数の電極を有する第２の半導体チップと、
    　前記第２の半導体チップ上に積層された補強板と、
    　前記複数の接続パッドと前記複数の電極とを電気的に接続する複数のワイヤとを備え、
    　前記第２の半導体チップは、前記第１の半導体チップに重なる積層領域と、前記第１の半導体チップからオーバーハングするオーバーハング領域とを有し、
    　前記電極は、前記オーバーハング領域に形成され、
    　前記補強板は、前記第２の半導体チップの前記積層領域と前記オーバーハング領域とに跨るように、前記第２の半導体チップ上に積層されていることを特徴とする半導体装置。
  2. 　前記補強板は、シリコン基板であることを特徴とする請求項１に記載の半導体装置。
  3. 　前記接続パッドは、前記第１の半導体チップ側に面する前記配線基板の一面に形成されていることを特徴とする請求項１または請求項２に記載の半導体装置。
  4. 　前記第２の半導体チップの前記電極は、前記補強板側に面する前記第２の半導体チップの一面に形成されていることを特徴とする請求項１乃至請求項３のいずれか１項に記載の半導体装置。
  5. 　前記補強板は、接着部材によって接着固定されることで、前記第２の半導体チップ上に積層されていることを特徴とする請求項１乃至請求項４のいずれか１項に記載の半導体装置。
  6. 　前記補強板は、第３の半導体チップであることを特徴とする請求項１乃至請求項５のいずれか１項に記載の半導体装置。
  7. 　前記配線基板の一面側において、前記第１の半導体チップと前記第２の半導体チップと前記補強板とを覆う封止樹脂をさらに備え、
    　前記第２の半導体チップ側とは反対側に面する前記補強板の一面は、前記封止樹脂に覆われておらず、外部に露出していることを特徴とする請求項１乃至請求項６のいずれか１項に記載の半導体装置。
  8. 　前記第２の半導体チップの前記オーバーハング領域は、前記積層領域を挟んで前記積層領域の両側にそれぞれ形成され、
    　前記補強板は、前記積層領域と、前記積層領域の両側に形成された一対の前記オーバーハング領域とに跨るように、前記第２の半導体チップ上に積層されていることを特徴とする請求項１乃至請求項７のいずれか１項に記載の半導体装置。
  9. 　前記第２の半導体チップの前記オーバーハング領域は、前記配線基板に平行な第１方向に向けて、前記第１の半導体チップからオーバーハングし、
    　前記補強板は、前記配線基板に平行かつ前記第１方向に交差する第２方向に向けて、前記第２の半導体チップからオーバーハングするオーバーハング領域を有していることを特徴とする請求項１乃至請求項８のいずれか１項に記載の半導体装置。
  10. 　複数の接続パッドが形成された配線基板を用意する工程と、
    　前記配線基板上に第１の半導体チップを搭載する工程と、
    　電極が形成された第２の半導体チップの一部分を前記第１の半導体チップからオーバーハングさせるように、前記第２の半導体チップを前記第１の半導体チップ上に搭載する工程と、
    　前記第１の半導体チップに重なる前記第２の半導体チップの積層領域と、前記第１の半導体チップからオーバーハングする前記第２の半導体チップのオーバーハング領域とに跨るように、前記第２の半導体チップ上に補強板を搭載する工程と、
    　前記複数の接続パッドと前記複数の電極とをワイヤによって電気的に接続する工程とを含むことを特徴とする半導体装置の製造方法。
PCT/JP2013/084037 2012-12-25 2013-12-19 半導体装置およびその製造方法 WO2014103855A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/655,209 US20150333041A1 (en) 2012-12-25 2013-12-19 Semiconductor device and manufacturing method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012-280972 2012-12-25
JP2012280972 2012-12-25

Publications (1)

Publication Number Publication Date
WO2014103855A1 true WO2014103855A1 (ja) 2014-07-03

Family

ID=51020942

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/084037 WO2014103855A1 (ja) 2012-12-25 2013-12-19 半導体装置およびその製造方法

Country Status (3)

Country Link
US (1) US20150333041A1 (ja)
TW (1) TW201442158A (ja)
WO (1) WO2014103855A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220059493A1 (en) * 2020-08-19 2022-02-24 Kioxia Corporation Semiconductor device and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006216776A (ja) * 2005-02-03 2006-08-17 Fujitsu Ltd 樹脂封止型半導体装置
JP2007142128A (ja) * 2005-11-18 2007-06-07 Renesas Technology Corp 半導体装置およびその製造方法
WO2011113136A1 (en) * 2010-03-18 2011-09-22 Mosaid Technologies Incorporated Multi-chip package with offset die stacking and method of making same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6359340B1 (en) * 2000-07-28 2002-03-19 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement
US7378725B2 (en) * 2004-03-31 2008-05-27 Intel Corporation Semiconducting device with stacked dice
US7968373B2 (en) * 2008-05-02 2011-06-28 Stats Chippac Ltd. Integrated circuit package on package system
KR101686553B1 (ko) * 2010-07-12 2016-12-14 삼성전자 주식회사 반도체 패키지 및 패키지 온 패키지

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006216776A (ja) * 2005-02-03 2006-08-17 Fujitsu Ltd 樹脂封止型半導体装置
JP2007142128A (ja) * 2005-11-18 2007-06-07 Renesas Technology Corp 半導体装置およびその製造方法
WO2011113136A1 (en) * 2010-03-18 2011-09-22 Mosaid Technologies Incorporated Multi-chip package with offset die stacking and method of making same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220059493A1 (en) * 2020-08-19 2022-02-24 Kioxia Corporation Semiconductor device and manufacturing method thereof
US11837569B2 (en) * 2020-08-19 2023-12-05 Kioxia Corporation Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
TW201442158A (zh) 2014-11-01
US20150333041A1 (en) 2015-11-19

Similar Documents

Publication Publication Date Title
US8786102B2 (en) Semiconductor device and method of manufacturing the same
US8076770B2 (en) Semiconductor device including a first land on the wiring substrate and a second land on the sealing portion
JP5579402B2 (ja) 半導体装置及びその製造方法並びに電子装置
US7575953B2 (en) Stacked die with a recess in a die BGA package
US7948089B2 (en) Chip stack package and method of fabricating the same
JP2009099697A (ja) 半導体装置及びその製造方法
US20120286411A1 (en) Semiconductor device and manufacturing method thereof, and semiconductor module using the same
JP2013115190A (ja) 半導体装置の製造方法
US10537018B2 (en) Semiconductor device
US8803304B2 (en) Semiconductor package and manufacturing method thereof
JP2010147070A (ja) 半導体装置
JP5557439B2 (ja) 半導体装置及びその製造方法
JP5501562B2 (ja) 半導体装置
US9252126B2 (en) Multi Chip Package-type semiconductor device
US8098496B2 (en) Wiring board for semiconductor device
US20160141272A1 (en) Semiconductor device and method of manufacturing same
US8072069B2 (en) Semiconductor device and method of manufacturing a semiconductor device
WO2014103855A1 (ja) 半導体装置およびその製造方法
JP2007173655A (ja) 半導体装置
JP2013157433A (ja) 半導体装置
US20160064301A1 (en) Semiconductor device
JP2011233672A (ja) 半導体装置および半導体装置の製造方法
JP2013143524A (ja) 半導体装置およびその製造方法
US20090189272A1 (en) Wafer Level Chip Scale Packages Including Redistribution Substrates and Methods of Fabricating the Same
JP2008251930A (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13869134

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 14655209

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

NENP Non-entry into the national phase

Ref country code: JP

122 Ep: pct application non-entry in european phase

Ref document number: 13869134

Country of ref document: EP

Kind code of ref document: A1