JP2006165466A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2006165466A JP2006165466A JP2004358543A JP2004358543A JP2006165466A JP 2006165466 A JP2006165466 A JP 2006165466A JP 2004358543 A JP2004358543 A JP 2004358543A JP 2004358543 A JP2004358543 A JP 2004358543A JP 2006165466 A JP2006165466 A JP 2006165466A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 185
- 238000012360 testing method Methods 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 60
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- 229920005989 resin Polymers 0.000 claims description 83
- 239000000463 material Substances 0.000 description 29
- 229910000679 solder Inorganic materials 0.000 description 29
- 239000002184 metal Substances 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000000523 sample Substances 0.000 description 6
- 238000007689 inspection Methods 0.000 description 5
- 230000001105 regulatory effect Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
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- 229910052802 copper Inorganic materials 0.000 description 3
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- 238000000151 deposition Methods 0.000 description 3
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- 238000005498 polishing Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
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Abstract
【解決手段】 他の半導体装置と接続される実装用端子92を基板81の一方の側に設け、実装用端子92が設けられた側とは反対側の基板81にテスト用端子103を配設した。
【選択図】 図4
Description
(実施例)
図3及び図4を参照して、本発明の本実施例による半導体装置80について説明する。図3は、本発明の本実施例による半導体装置の平面図であり、図4は、図3に示した半導体装置のB−B線方向の断面図である。なお、図3に示したR1は、モールド樹脂109に露出されたテスト用端子103の平坦な面103Aの直径(以下、「直径R1」とする)を示している。また、図4に示したCは半導体チップ105が配設される上部樹脂層96上の領域(以下、「チップ配設領域C」とする)、H1は電極パッド106を基準とした際のワイヤ107の高さ(以下、「高さH1」とする)、T1は電極パッド106を含んだ半導体チップ105の厚さ(以下、「厚さT1」とする)、T2は上部樹脂層96の上面を基準とした際のモールド樹脂109の厚さ(以下、「厚さT2」とする)、R2はテスト用端子103の略球形状とされた部分の直径(以下、「直径R2」とする)、R3は略球形状とされた実装用端子92の直径(以下、「直径R3」とする)をそれぞれ示している。
11,51,71,81,115,131 基板
12,82 基材
12A,82A,96A 上面
12B,82B,87A 下面
13,83 貫通ビア
14,95 上部配線
15,96 上部樹脂層
16,33,88,97 ビア
17 配線
19,53 接続部
21,38,91,102 ソルダーレジスト
25,55,105,123 半導体チップ
26,56,106 電極パッド
28,107 ワイヤ
29 モールド樹脂
31,85 下部配線
32,87 下部樹脂層
32A,87A,103A,109A,125A,134A 面
35,37,54,61,89,101,117,121,132,151 接続パッド
41,62,72,92,118,125,134 実装用端子
42,103 テスト用端子
57 スタッドバンプ
58 はんだ
59 アンダーフィル樹脂
99 ワイヤ接続部
109 モールド樹脂
136 第1の接続部
137 第2の接続部
138 ソルダーレジスト
141 個別部品
142 電極
143 はんだペースト
145 パッケージ
146 パッケージ本体
147 リードフレーム
A,C チップ配設領域
H1 高さ
R1〜R8 直径
T1〜T4 厚さ
Claims (4)
- 半導体チップと、
実装用端子とテスト用端子とが配設されると共に、前記半導体チップが実装される基板とを備えた半導体装置において、
前記テスト用端子を、前記実装用端子が設けられた前記基板の側とは反対側に設けたことを特徴とする半導体装置。 - 前記半導体チップは、前記テスト用端子が設けられた側の前記基板に実装されており、
前記テスト用端子を、前記半導体チップよりも突出させたことを特徴とする請求項1に記載の半導体装置。 - 前記半導体チップは、ワイヤにより前記基板と接続されており、
前記テスト用端子を、前記ワイヤよりも突出させたことを特徴とする請求項2に記載の半導体装置。 - 前記半導体チップは、前記ワイヤを保護する樹脂に覆われており、前記テスト用端子の一部は、前記樹脂から露出していることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004358543A JP4444088B2 (ja) | 2004-12-10 | 2004-12-10 | 半導体装置 |
TW094141878A TWI395302B (zh) | 2004-12-10 | 2005-11-29 | 半導體元件及半導體元件之製造方法 |
US11/291,599 US20060125077A1 (en) | 2004-12-10 | 2005-12-01 | Semiconductor device |
CNA2005100228837A CN1812082A (zh) | 2004-12-10 | 2005-12-09 | 半导体器件 |
KR1020050120531A KR20060065561A (ko) | 2004-12-10 | 2005-12-09 | 반도체 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2004358543A JP4444088B2 (ja) | 2004-12-10 | 2004-12-10 | 半導体装置 |
Related Child Applications (1)
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JP2007241376A Division JP4704404B2 (ja) | 2007-09-18 | 2007-09-18 | 半導体装置とその製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2006165466A true JP2006165466A (ja) | 2006-06-22 |
JP4444088B2 JP4444088B2 (ja) | 2010-03-31 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2004358543A Active JP4444088B2 (ja) | 2004-12-10 | 2004-12-10 | 半導体装置 |
Country Status (5)
Country | Link |
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US (1) | US20060125077A1 (ja) |
JP (1) | JP4444088B2 (ja) |
KR (1) | KR20060065561A (ja) |
CN (1) | CN1812082A (ja) |
TW (1) | TWI395302B (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008218505A (ja) * | 2007-02-28 | 2008-09-18 | Sony Corp | 基板およびその製造方法、半導体パッケージおよびその製造方法、並びに半導体装置およびその製造方法 |
JP2009043845A (ja) * | 2007-08-07 | 2009-02-26 | Kyocer Slc Technologies Corp | 配線基板 |
JP2010103348A (ja) * | 2008-10-24 | 2010-05-06 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2014197597A (ja) * | 2013-03-29 | 2014-10-16 | ローム株式会社 | 半導体装置 |
TWI483321B (zh) * | 2012-09-19 | 2015-05-01 | Zhen Ding Technology Co Ltd | 層疊封裝結構及其製作方法 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JPWO2007069606A1 (ja) | 2005-12-14 | 2009-05-21 | 新光電気工業株式会社 | チップ内蔵基板の製造方法 |
JP2008016630A (ja) * | 2006-07-06 | 2008-01-24 | Matsushita Electric Ind Co Ltd | プリント配線板およびその製造方法 |
US8406004B2 (en) * | 2008-12-09 | 2013-03-26 | Stats Chippac Ltd. | Integrated circuit packaging system and method of manufacture thereof |
CN103346137A (zh) * | 2013-06-24 | 2013-10-09 | 曙光信息产业(北京)有限公司 | 集成电路封装件及其工艺方法 |
KR102237870B1 (ko) * | 2013-10-25 | 2021-04-09 | 엘지이노텍 주식회사 | 인쇄회로기판 및 그 제조방법과 이를 이용하는 반도체 패키지 |
KR102192569B1 (ko) * | 2015-11-06 | 2020-12-17 | 삼성전자주식회사 | 전자 부품 패키지 및 그 제조방법 |
US10204889B2 (en) * | 2016-11-28 | 2019-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of forming thereof |
US10541209B2 (en) * | 2017-08-03 | 2020-01-21 | General Electric Company | Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof |
US10804115B2 (en) | 2017-08-03 | 2020-10-13 | General Electric Company | Electronics package with integrated interconnect structure and method of manufacturing thereof |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100266693B1 (ko) * | 1998-05-30 | 2000-09-15 | 김영환 | 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법 |
JP2001339011A (ja) * | 2000-03-24 | 2001-12-07 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US6326700B1 (en) * | 2000-08-15 | 2001-12-04 | United Test Center, Inc. | Low profile semiconductor package and process for making the same |
US6798057B2 (en) * | 2002-11-05 | 2004-09-28 | Micron Technology, Inc. | Thin stacked ball-grid array package |
-
2004
- 2004-12-10 JP JP2004358543A patent/JP4444088B2/ja active Active
-
2005
- 2005-11-29 TW TW094141878A patent/TWI395302B/zh active
- 2005-12-01 US US11/291,599 patent/US20060125077A1/en not_active Abandoned
- 2005-12-09 KR KR1020050120531A patent/KR20060065561A/ko active Search and Examination
- 2005-12-09 CN CNA2005100228837A patent/CN1812082A/zh active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008218505A (ja) * | 2007-02-28 | 2008-09-18 | Sony Corp | 基板およびその製造方法、半導体パッケージおよびその製造方法、並びに半導体装置およびその製造方法 |
JP2009043845A (ja) * | 2007-08-07 | 2009-02-26 | Kyocer Slc Technologies Corp | 配線基板 |
JP2010103348A (ja) * | 2008-10-24 | 2010-05-06 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US8810047B2 (en) | 2008-10-24 | 2014-08-19 | Ps4 Luxco S.A.R.L. | Semiconductor device and method of manufacturing the same |
TWI483321B (zh) * | 2012-09-19 | 2015-05-01 | Zhen Ding Technology Co Ltd | 層疊封裝結構及其製作方法 |
JP2014197597A (ja) * | 2013-03-29 | 2014-10-16 | ローム株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
TWI395302B (zh) | 2013-05-01 |
CN1812082A (zh) | 2006-08-02 |
KR20060065561A (ko) | 2006-06-14 |
TW200625561A (en) | 2006-07-16 |
US20060125077A1 (en) | 2006-06-15 |
JP4444088B2 (ja) | 2010-03-31 |
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