CN1622328A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1622328A CN1622328A CNA2004100956257A CN200410095625A CN1622328A CN 1622328 A CN1622328 A CN 1622328A CN A2004100956257 A CNA2004100956257 A CN A2004100956257A CN 200410095625 A CN200410095625 A CN 200410095625A CN 1622328 A CN1622328 A CN 1622328A
- Authority
- CN
- China
- Prior art keywords
- semiconductor element
- electrode
- semiconductor
- semiconductor device
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 600
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims description 81
- 238000007789 sealing Methods 0.000 claims abstract description 91
- 239000011347 resin Substances 0.000 claims abstract description 78
- 229920005989 resin Polymers 0.000 claims abstract description 78
- 239000002184 metal Substances 0.000 claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims abstract description 52
- 239000000463 material Substances 0.000 claims abstract description 46
- 230000002093 peripheral effect Effects 0.000 claims description 41
- 238000012856 packing Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 25
- 238000005520 cutting process Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 208000034189 Sclerosis Diseases 0.000 claims 8
- 230000003340 mental effect Effects 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 40
- 230000001070 adhesive effect Effects 0.000 description 40
- 239000000203 mixture Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 241000218202 Coptis Species 0.000 description 4
- 235000002991 Coptis groenlandica Nutrition 0.000 description 4
- 230000000712 assembly Effects 0.000 description 4
- 238000000429 assembly Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
本发明揭示一种半导体器件及其制造方法,通过小片接合材料(7)使第一半导体元件(3)和第二半导体元件(8)粘接,在一侧的表面上有第三电极(2)和在另一侧的表面的周围部分有第四电极(12)的半导体载体上(1),利用倒装接合使所述第一半导体元件(3)的所述第一电极(6a)和所述第三电极(2)接合,利用引线接合通过金属细线(10)使第二半导体元件8的焊盘9和半导体载体(1)的第四电极(12)连接,将绝缘密封树脂(13)填入所述半导体载体(1)和第二半导体元件(8)之间的第一半导体元件(3)的周围及金属细线(10)的布线部,将该密封充填区域(13)的外形尺寸做成和第二半导体元件(8)几乎相同。
Description
技术领域
本发明涉及将多个半导体元件层叠在一起的层叠型半导体器件及其制造方法。
背景技术
伴随着小而轻的便携式信息设备等的功能扩大,以装有多个半导体器件的半导体存储器为主,需要将多个半导体器件层叠在一起的、而且小而薄的层叠型半导体器件。
首先,参照图23A及图23B说明日本专利公开公报:特开2002-270763揭示的第一现有例子(半导体载体的电极和上方的半导体元件的电极之间利用金属细线连接的半导体器件)。
第一现有例子揭示的所述半导体器件中,在表面的电极上形成凸点56的第一半导体元件53使其表面侧朝下,与多层电路用布线基板即半导体载体51接合。在所述半导体载体51的上表面形成与第一半导体元件53导通用的多个第一电极62、和与第二半导体元件58导通用的多个第二电极52。然后,利用导电粘接剂65使上述多个第一电极62和在第一半导体元件53上形成的凸点56接合。该导电粘接剂65预先涂在凸点56上。然后,在互相接合的第一半导体元件53和半导体载体51的间隙中填入填充材料54进行覆盖。第二半导体元件58再通过小片接合材料57与第一半导体元件53的背面(图23A中的上表面)粘接,第二半导体元件58和第一半导体元件53层叠在一起。接着利用引线接合法,通过金属细线60将第二半导体元件58的焊盘59和半导体载体51的上表面的多个第二电极52互相电气连接。又再在第二半导体元件58及半导体载体51之间将绝缘性的密封树脂63填入半导体元件53的周围和金属细线60的布线部,来进行密封。最后,外部端子电极61装在半导体载体51的下表面(外面)。
以下,参照图24A及图24B说明日本专利公开公报:特开2003-347505揭示的第二现有例子(用内部引线代替第一现有例子中使用的金属细线的半导体器件)。
第二现有例子揭示的半导体器件将第一半导体元件73、第二半导体元件78、和载带71层叠配置在同一组件内。然后载带71和所述半导体元件73、78通过载带71的内部引线75电气连接。即在载带71表面侧设置的阵列上形成多个接合面72,外部端子电极81装在所述接合面72上。另外,从所述接合面72引出的内部引线75分别与第一半导体元件73的电极凸点74及/或设在第二半导体元件78的上表面周边部的电极凸点79接合。密封树脂83再从第一、第二半导体元件68的上表面填入载带71的外周部,保护内部引线75及焊盘74、79。
但是,上述第一现有例子的半导体器件的结构中有阻碍小型化的因素存在。即,所述半导体器件为了使第二半导体元件58的焊盘59和半导体载体51的第二电极52连接,采用引线接合法,如图23B所示,在这种采用引线接合法连接的场合,由于金属细线60露出在第二半导体器件58的外缘之外,因此由绝缘密封树脂63充填的密封充填区(接合区域)70至少要设置到第二半导体元件58的外侧,安装面积大于第二半导体元件58,这就阻碍了半导体器件的小型化。
又一个存在的问题是,由于用树脂把第一半导体元件53及第二半导体元件58整体封死,散热情况变差。
再在上述第二现有例子的半导体器件中,还有阻碍向多引脚化(外部端子电极81的多极化)发展的因素存在。即,所述半导体器件在同一封装内层叠配置的半导体元件73、78由于利用内部引线75和接合面72电气连接,因此内部引线75的布线在某种程度上对能配置的接合面72的数量产生限制。另外,半导体元件73、78的安装部分一定要比半导体器件小。因而这也阻碍了半导体器件的多引脚化。
本发明为解决上述问题而提出,目的在于提供一种能促进小型化、并散热良好的半导体器件及其制造方法。
发明内容
本发明是在另一侧的表面上设置第一电极的第一半导体元件的一侧的表面上粘接着第二半导体元件。所述第二半导体元件做得比所述第一半导体元件大,而且在所述另一侧的表面的外周部上设置第二电极。布线基板一侧的表面上的第三电极利用倒装接合法和所述第一半导体元件的所述第一电极接合。设置在所述布线基板的另一侧的表面的外周部上的第四电极利用引线接合法通过金属细线和所述第二半导体元件的所述第二电极连接。在所述第二半导体元件和所述布线基板之间利用绝缘密封树脂将所述第一半导体元件的周围和所述金属细线的布线部密封,所述密封树脂的密封填充区域做成和第二半导体元件的外形尺寸几乎相同。
附图说明
图1为表示本发明有关的半导体器件第一实施形态的侧面断面图。
图2A~图2E为分别表示同上的半导体器件的第一制造步骤用的说明图。
图3A~图3E为分别表示同上的半导体器件的第二制造步骤用的说明图。
图4A~图4J为分别表示同上的半导体器件的第二制造步骤用的说明图。
图5表示同上的半导体器件的变形例子,为具有多个半导体元件的半导体器件的侧面断面图。
图6为表示本发明有关的半导体器件第二实施形态的侧面断面图。
图7表示同上的半导体器件的变形例子,为具有多个第一半导体元件的半导体器件的侧面断面图。
图8为表示本发明有关的半导体器件第三实施形态的侧面断面图。
图9A~图9F为分别说明同上的半导体器件的第一制造步骤用的侧面断面图。
图10A~图10D为分别说明同上的半导体器件的第二制造步骤用的侧面断面图。
图11E~图11G为说明各同上的半导体器件的第二制造步骤用的侧面断面图。
图12表示同上的半导体器件的变形例子,为具有多个第一半导体元件的半导体器件的侧面断面图。
图13为表示本发明有关的半导体器件第四实施形态的侧面断面图。
图14表示同上的半导体器件的变形例子,为具有多个第一半导体元件的半导体器件的侧面断面图。
图15为表示本发明有关的半导体器件第五实施形态的侧面断面图。
图16A~图16F为分别说明同上的半导体器件的第一制造步骤用的侧面断面图。
图17A~图17F为分别说明同上的半导体器件的第二制造步骤用的侧面断面图。
图18表示同上的半导体器件的变形例子,为具有多个第一半导体元件的半导体器件的侧面断面图。
图19为表示本发明有关的半导体器件第六实施形态的侧面断面图。
图20A~图20F为分别说明同上的半导体器件的第一制造步骤用的侧面断面图。
图21A~图21F为分别说明同上的半导体器件的第二制造步骤用的侧面断面图。
图22表示同上的半导体器件的变形例子,为具有多个第一半导体元件的半导体器件的侧面断面图。
图23A为表示第一现有半导体器件的侧面断面图,图23B为表示第一现有半导体器件的平面断面图。
图24A为表示第二现有半导体器件的侧面断面图,图24B为表示第二现有半导体器件的平面断面图。
具体实施方式
[第一实施形态]
参照图1~图3说明本发明有关的半导体器件的第一实施形态、和其第一种制造方法及第二种制造方法的第一实施形态。
如图1所示,该半导体器件包括第一半导体元件3、第二半导体元件8、及多层电路用布线基板即半导体载体1。
所述第一半导体元件3在其另一侧的表面(以下,在图1中称为下表面)的第一电极即电极6a上形成多个凸起电极即凸点6。另外,第二半导体元件8的外形尺寸做得比第一半导体元件3大,而且,在另一侧的表面上,在比第一半导体元件3的外形尺寸更靠外侧的外周部上形成第二电极即焊盘9。所述半导体载体1的多个第三电极即第一粘接层2与多个所述凸点6对应,在一侧的表面(以下,图1中称为上表面)上形成,另外,多个第四电极即第二粘接层12在另一侧的表表面的外周部上形成。这里使用的半导体载体1的材料可以采用玻璃纤维环氧树脂基板、有机基板、陶瓷基板之类的基板。本例中使用玻璃纤维环氧树脂基板。
接着在所述半导体载体1上形成多个外部端子电极11,所述外部端子电极11在另外一侧的表面的外周部上与规定的第一粘接层2导通。所述半导体载体1的外形尺寸和第一半导体元件3的外形尺寸相同或略大。又因半导体载体1要和第二半导体元件8电气连接,所以所述半导体载体1的外形尺寸采用至少比第二半导体元件8的外形尺寸小1mm以上的尺寸。然后,第二半导体元件8的另一侧的表面通过小片接合材料7与第一半导体元件3一侧的表面粘接。另外,利用倒装接合法,第一半导体元件3的凸点6通过导电粘接剂5与半导体载体1的第一粘接层2接合,所述半导体载体1层叠在第一半导体元件3的另一侧的表面上。另外,填充材料4注入第一半导体元件3和半导体载体1之间的间隙及周围部分,以保护凸点6。再用引线接合法,从所述第二半导体元件8的焊盘9通过金属细线10连接在半导体载体1的另一侧的表面的周围部分形成的第一粘接层2。
再又为了保护所述第一半导体元件3、第二半导体元件8、和金属细线10,将绝缘密封树脂13从第二半导体元件8的另一侧的表面开始到半导体载体1充填在半导体载体1的周围和金属细线10的布线部上进行密封。然后在和第二半导体元件8的外形尺寸大致相同的范围内形成该密封树脂13的密封充填区域20。
(所述半导体器件的第一种制造方法)
以下,参照图2A~图2E说明第一实施形态有关的所述半导体器件的第一种制造方法。
如图2A所示,所述第一半导体元件3的另一侧的表面通过小片接合材料7与第二半导体元件8的一侧的表面粘接(工序A)。这一小片接合材料可采用绝缘性的糊状物或绝缘片,这里用绝缘片。
如图2B所示,在所述第一半导体元件3的电极6a上形成凸点6。凸点可以用电镀凸点或利用金线的柱形凸点,这里使用柱形凸点。
然后,如图2C所示,在所述凸点6上涂了导电粘接剂5之后反转,使得第二半导体元件8向上,配置在半导体载体1上。接着利用倒装接合法,使凸点6和第一粘接层2接合,第一半导体元件3层叠在半导体载体1上(工序B)。再将填充材料4注入第一半导体元件3和半导体载体1的间隙及周围部分,以保护凸点6(工序C)。
如图2D所示,再反转使得所述第二半导体元件8向下。第二粘接层12形成于所述半导体载体1的另一侧的表面的周围部分。利用引线接合法,通过金属细线10将第二半导体元件8的焊盘9和所述第二粘接层12电气连接(工序D)。
如图2E所示,为了保护所述第一半导体元件3、第二半导体元件8、金属细线10,将密封树脂13从第二半导体元件8的另一侧的表面到半导体载体1充填入第一半导体元件3及半导体载体1的周围和金属细线10的布线部,来进行密封(工序E)。这里,形成了范围大致和第二半导体元件8的外形尺寸相同的充填了密封树脂13的密封充填区域(接合区域)20,然后,通过安装外部端子电极11,从而完成所述半导体器件的制造。
还有,作为上述第一种制造方法的变形例,是先用倒装接合法在半导体载体1的一侧的表面上接合第一半导体元件3(工序B),在注入填充材料4(工序C)后,通过小片接合材料7在第一半导体元件3的背面粘接第二半导体元件8(工序A),即次序也可以为工序B、工序C、工序A、工序D、工序E。
这里,如图1所示,为了使所述外部端子电极11与外部良好连接,保护金属细线10和第二粘接层12的密封树脂13的厚度t做成比外部端子电极11的安装高度h要薄。这是由于若密封树脂13的厚度t做得比外部端子电极11的高度h要厚,则在安装该半导体器件时,由于密封树脂13厚度t的阻碍,妨碍与外部端子电极11的连接的原因。例如,外部电极11的安装高度h=约250μm,密封树脂13的厚度t=约200μm,金属细线10的高度离半导体载体1的另外一侧的表面形成约150μm。这里示出的厚度和高度均能根据外部端子电极11的高度任意地改变实施,但是,一般的半导体器件上,外部端子电极11的安装高度h和密封树脂13的厚度t之差(h-t)至少要大于50μm。
(所述半导体器件的第二种制造方法)(晶片组件切割法)
以下参照图3A~图3E、图4F~图4J说明第一实施形态的所述半导体器件的第二种制造方法。
首先,如图3A所示,在所述第一半导体元件3的一侧的表面上设置电极6a。然后,如图3B所示,在所述第一半导体元件3的电极6a上形成凸点6。
再如图3C所示,在所述凸点6上涂导电粘接剂5后,将第一半导体元件3反转,使得电极6a向下,配置在半导体载体1上。接着利用倒装接合法,使凸点6、和半导体载体1的第一粘接层2接合,第一半导体元件3层叠在半导体载体1的一侧的表面上(工序B)。再把填充材料4注入第一半导体元件3和半导体载体1的间隙和周围部分,以保护凸点6(工序C)。
然后,如图3D所示,所述第二半导体元件8处于多个元件形成一体的(切割前)的晶片基板15的状态,如图3E所示,在该晶片基板15状态下的各第二半导体元件8的另一侧的表面上,通过小片接合材料7分别粘接所述第一半导体元件3(工序A)。然后,利用引线接合,通过金属细线10将所述第二半导体元件8的焊盘9和半导体载体1的第二粘接层12电气连接(工序D)。该小片接合材料可采用绝缘糊状物或绝缘片,这里使用绝缘片。
再如图4F、4G所示,为了保护所述第一半导体元件3、第二半导体元件8、金属细线10,密封树脂13从第二半导体元件8的另一侧的表面到半导体载体1填入第一半导体元件3及半导体载体1的周围和金属细线10的布线部,来进行密封(工序E)。
最后,如图4H、图4I所示,树脂密封好后,所述晶片基板15利用刀片16切割,分离形成前述半导体器件(工序F)。最终,如图4I所示,得到一片一片所述半导体器件。
再如图4I所示,外部端子电极11安装在所述半导体载体1上(工序G)。通过这样,完成所述半导体器件的制造。
第二种制造方法能将所述小片接合工序(工序A)、引线接合工序(工序D)、树脂密封工序(工序E)、切片工序(工序F)集中起来,制造多个半导体器件,故生产效率高。
如上所述,根据第一实施形态,由于在比所述第二半导体元件8的外形更内侧处,用金属细线10连接第二半导体元件8的焊盘9和在半导体载体1的另一侧的表面(下表面)上形成的第二粘接层12,所以能形成外形尺寸和第二半导体元件8大致相同的用绝缘密封树脂13密封的密封填充区域20。因而,上述第一实施形态由于不必如现有的半导体器件那样,利用引线接合将金属细线扩展到半导体元件的外侧进行配置,所以在现实的组件形态下,最短的线(金属细线)长=0.4mm,接合区焊点的长度为200μm=0.2mm,因而组件每边1.2mm[=0.4+0.2]×2]的区域就不再需要,能将该密封充填区域20做得小于1mm,从而能提供更加小型的层叠型的所述半导体器件。
还有,如图5所示,第一实施形态的半导体器件的结构也能做成将多个第一半导体元件3a、3b配置在半导体载体21的一侧的表面上。这时,在制造方法上,是在利用倒装接合法将第一半导体元件3a、3b层叠在半导体载体1的一侧的表面(工序B)时,先接合第一半导体元件3a,接着,下一个为第一半导体元件3b,依照这样的次序,逐个和半导体载体1接合。
[第二实施形态]
参照图6说明本发明有关的半导体器件及其制造方法的第二实施形态。还有,和第一实施形态相同的构件上标注相同的标号,其说明省略。
上述第一实施形态的所述半导体器件为了和外部端子电极11的外部保持良好的连接,有一个条件为,保护金属细线10及第二粘接层12的密封树脂13的厚度t做得比外部端子电极11的安装高度要薄。如取该密封树脂13的厚度t例如为200μm,则外部端子电极11的安装高度h要取250μm以上,因此,外部端子电极11例如为焊球时,要将焊球大小做得大于250μm。由此,存在的问题为限制与外部连接的端子数,会不适用于多引脚的所述半导体器件。
因此,在第二实施形态中,提供一种对外部端子电极11的安装高度h限制极小的所述半导体器件及其制造方法。
即半导体载体21的另一侧的表面(以下,在图6中称为下表面)由中央部分厚度t并有外部端子电极11的凸出面21a、和在该凸出面21a的外周部通过台阶部21c厚度变薄而且具有第二粘接层12的后缩面21b组成。凸出面21a和后缩面21b间的台阶部21c的高度h做成和覆盖金属细线10及第二粘接层12的密封树脂13的厚度t大致相同。由于利用该台阶部21c的高度H吸收密封树脂13的厚度t,所以密封树脂13的表面和凸出面21a能在几乎相同的平面上形成,对外部端子电极11的安装高度h不会有限制。当然,即使密封树脂13的厚度t≤台阶部21c的高度h也没有问题,再在尽管密封树脂13的厚度t>台阶部21c的高度h,但在其差很小的场合,外部端子电极11的安装高度h的限制变得极小。
因此,在所述外部端子电极11为焊球或镀焊锡时,外部端子电极11的高度能自由地变更。另外,即使半导体载体21的外部端子电极11为无焊锡的LGA(接合面网格阵列),也完全能适应,另外,外部端子电极11的数量也无限制,能适用于多引脚的层叠型的所述半导体器件。
还有,第二实施形态的所述半导体器件的制造方法中,能利用和第一实施形态相同的制造方法进行制造。
根据所述第二实施形态,由于在所述半导体载体21的另一侧的表面上,设置有外部端子电极11的凸出面21a、和在其外周部厚度变薄而且有第二粘接层12的后缩面21b,利用其高度h能吸收密封树脂13的厚度t,即覆盖第二粘接层12的从所述凸出面21a凸出的所述密封树脂13的厚度t能减去从后缩面21b至凸出面21a的高度H,所以对外部端子电极11的安装高度h无限制。
还有,第二实施形态的所述半导体器件如图7所示,多个第一半导体元件3a、3b能配置在半导体载体21的一侧的表面上。这种场合,在制造方法中,是利用倒装接合法将第一半导体元件3a、3b层叠在半导体载体1的一侧的表面上(工序B)时,先接合第一半导体元件3a,然后,下一个为第一半导体元件3b,按照这样的次序逐个与半导体载体1接合。
[第三实施形态]
参照图8~图11说明本发明有关的半导体器件及其制造方法的第三实施形态。再者,和第一及第二实施形态相同构件上标注相同标号,其说明从略。
如图8所示,第一半导体元件3在一侧的表面(以后,在图8中称为上表面)有第五电极即电极面31。另外,第二半导体元件8在另一侧的表面(以后,在图8中称为下表面)的中央部分设置第六电极即电极面32,另一侧的表面的外周部形成第二电极即焊盘9。
凸出电极即凸点33形成于第一半导体元件3的电极面31。然后,利用倒装接合,通过导电粘接剂5将第一半导体元件3的凸点33和所述第二半导体元件8的电极面32接合,第一半导体元件3层叠在第二半导体元件8的另一侧的表面上。然后,向第一半导体元件3和第二半导体元件8之间形成的间隙和周围部分注入填充材料4,以保护凸点33。
上述第一半导体元件3和第二半导体元件8的连接方法称为CCC(Chip-On-Chip芯片上芯片)结构,由此,第一半导体元件3和第二半导体元件8能以较近的距离电气连接,第一、第二半导体元件3、8之间能高速动作。
然后,第一半导体元件3的另一侧的表面和半导体载体1的一侧的表面利用小片接合材料7接合层叠。再利用引线接合,通过金属细线10使第二半导体元件8的焊盘9和设在半导体载体1的另一侧的表面上的第四电极即第二粘接层12连接。另外,为了保护这些金属细线10,绝缘密封树脂13从第二半导体元件8的另一侧的表面起到半导体载体1填入第一半导体元件3和半导体载体1的第二粘接层12的周围及金属细线10的布线部,进行树脂密封,形成外形尺寸和第二半导体元件8大致相同的由所述密封树脂13密封的密封树脂区域20。
(所述半导体器件的第一种制造方法)
以下,参照图9A~图9F说明第三实施形态有关的所述半导体器件的第一种制造方法。
如图9A所示,在所述第一半导体元件3的一侧的表面上设置电极面31。如图9B所示,在第一半导体元件3的电极面31上形成凸点33。凸点33能采用电镀凸点或使用金线的柱形凸点,这里使用柱形凸点。
接着,如图9C所示,在所述第二半导体元件8的另一侧的表面的电极面32上,设置凸点座。接着,在凸点33上涂导电粘接剂5后,利用倒装接合使第一半导体元件3和第二半导体元件8的电极面32接合(工序H)。再将填充材料4注入第一半导体元件3和第二半导体元件8之间的间隙及周围部分保护凸点33(工序I)。
接着,如图9D所示,所述第一半导体元件3通过小片接合材料7与半导体载体1的一侧的表面粘接(工序J)。这里小片接合材料7能用绝缘糊状物或绝缘片,现采用绝缘片。
接着,如图9E所示,在所述半导体载体1的另一侧的表面的外周部上形成第二粘接层12,利用引线接合使所述第二粘接层12和第二半导体元件8的焊盘9通过金属细线10电气连接(工序K)。再为了保护第一半导体元件3、第二半导体元件8、金属细线10,密封树脂13从第二半导体元件8的另一侧的表面到半导体载体1填入第一半导体元件3和半导体载体1的周围及金属细线10的布线部,来进行密封(工序L)。这里,密封树脂13充填的密封充填区域(接合区域)20形成于外形尺寸和第二半导体元件8大致相同的范围。
接着,如图9F所示,通过把外部端子电极11安装在所述半导体载体21的另一侧的表面上,从而完成所述半导体器件的制造。
还有,作为上述第一种制造方法的变形例,可以为先将第一半导体元件3粘接在半导体载体1上(工序J)后,再利用倒装接合使第一半导体元件3与半导体载体1的一侧的表面接合(工序H)及注入填充材料4(工序I),采用这样的次序、即工序J、工序H、工序I、工序K、工序L的次序。
(所述半导体器件的第二种制造方法)(晶片组件切割法)
参照图10A~图10D及图11E~图11G说明上述第二实施形态的所述半导体器件的第二种制造方法。
如图10A所示,第五电极即电极面31设在所述第一半导体元件3的一侧的表面上。如图10B所示,在电极面31上形成凸起电极即凸点33。
如图10C所示,所述第二半导体元件8为多个元件形成一体的(切割前的)晶片基板15的状态,该晶片基板15状态下的各第二半导体元件8的第六电极面即电极面32上利用倒装接合通过凸点33和第一半导体元件3的电极面31接合,第一半导体元件3分别层叠在第二半导体元件8上(工序H),再在第一半导体元件3和第二半导体元件8之间的间隙和周围部分注入填充材料4,以保护凸点33(工序I)。
如图10D所示,通过小片接合材料7使所述第一半导体元件3的另一侧的表面和半导体载体1的一侧的表面粘接,第一半导体元件3、第二半导体元件8层叠在半导体载体1上(工序J)。
如图11E所示,利用引线接合,通过金属细线10使所述半导体载体1的粘接层12和第二半导体元件8的焊盘9电气连接(工序K)。
如图11F所示,为了保护所述第一、第二半导体元件3、8、和金属细线10,在第二半导体元件8和半导体载体1之间将密封树脂13填入第一半导体元件3和半导体载体1的周围及金属细线10的布线部,来进行密封(工序L)。然后,安装外部端子电极11。
最后用切刀切割树脂密封后的所述晶片基板15,将所述半导体器件分开(工序N),如图11G所示,制成一片一片的所述半导体器件。
根据第二种制造方法,将倒装接合工序(工序H)、填充材料注入工序(工序I)、小片接合工序(工序J)、引线接合工序(工序K)、树脂密封工序(工序L)、切片工序(工序N)集中起来,能制造多片所述半导体器件,能高效地生产。
这里,如图8所示,为了使所述外部端子电极11和外部保持良好的连接,保护金属细线10和第二粘接层12的密封树脂13的厚度t做得比外部端子电极11的安装高度h要薄。这是由于若密封树脂13的厚度t比外部端子电极11的高度h厚,则在安装时,密封树脂13的厚度t就变成阻碍,妨碍外部端子电极11的连接。
根据上述第三实施形态,由于能取得和第一实施形态同样的作用效果,同时还利用倒装接合使所述第一半导体元件3和第二半导体元件8连接并层叠在一起,故半导体元件3、8间能高速动作。另外,根据上述制造方法,能制造和第一实施形态的所述半导体器件同样作用效果的层叠体形状的半导体器件。又因第一半导体元件3和第二半导体元件8利用倒装接合连接,故能提供半导体元件3、8之间能高速动作的所述半导体器件。
再者,如图12所示,也可以将多个第一半导体元件3a、3b配置在半导体载体1的一侧的表面上。
[第四实施形态]
参照图13说明本发明有关的半导体器件及其制造方法的第四实施形态。再者,在和第一~第三实施形态相同的构件上标注相同标号,其说明省略。
半导体载体21由在另一侧的表面上形成具有外部端子电极11的凸出面21a、和在该凸出面21a上通过台阶部21c而形成具有第二粘接层12的后缩面21b。该所述半导体器件能用和第三实施形态相同的方法制造。
利用所述半导体载体21,除了第三实施形态的所述半导体器件的效果外,还具有和第二实施形态同样的效果,即通过在半导体载体21的另一侧的表面设置有外部端子电极11的凸出面21a和其外周部厚度薄并具有第二粘接层12的后缩面21b,从而利用其高度H能吸收密封树脂13的厚度t。即覆盖第二粘接层12从所述凸出面21a上凸出的所述密封树脂13的厚度t由于能减去从后缩面21b至凸出面21a的高度h,所以能取得外部端子电极11的安装高度h不受限制的独特效果。
又如图14所示,也可将多个第一半导体元件3a、3b配置在半导体载体21的一侧的表面上。
[第五实施形态]
参照图15~17说明本发明有关的半导体器件及其制造方法的第五实施形态。该第五实施形态利用载带41代替第一~第四实施形态的半导体载体1。和第一~第四实施形态相同的构件上标注相同标号,其说明省略。
如图15所示,凸点6形成于设在第一半导体元件3的另一侧的表面(以后,在图15中称下表面)上的第一电极即电极6a上。第一半导体元件3的所述凸点6利用倒装接合通过导电粘接剂5与设置在所述载带41的一侧的表面(以后,在图15中称上表面)上的第七电极即粘接层42接合。由此第一半导体元件3层叠在载带41的一侧的表面上。然后,把填充材料4注入第一半导体元件3和载带41之间形成的间隙和周围部分中,以保护凸点6。
所述第二半导体元件8的另一侧的表面通过小片接合材料7与第一半导体元件3的一侧的表面粘接,使第二半导体元件8层叠在第一半导体元件3的一侧的表面上。再又,在载带41上一体形成的内部引线43与第二半导体元件8的表面的第二电极即焊盘9电气连接。然后,密封树脂43从第二半导体元件8的另一侧的表面到载带41填入第一半导体元件3的周围和内部引线43的布线部,利用所述密封树脂13保护第一半导体元件3、第二半导体元件8、内部接线43。充填密封树脂13的密封充填区域(接合区域)20形成于和第二半导体元件8的外形尺寸几乎相同的范围。还有,与粘接层42或内部引线43导通的外部端子电极11形成于载带41的另一侧的表面。
(所述半导体器件的第一种制造方法)
参照图16A~图16F说明上述第五实施形态有关的所述半导体器件的第一种制造方法。
如图16A所示,电极6a设在所述第一半导体元件3的另一侧的表面上。如图16B所示,所述电极6a上形成凸起电极即凸点6。可以采用电镀凸点或金线的柱形凸点作为所述凸点6,这里采用柱形凸点。
如图16C所示,通过小片接合材料7使所述第一半导体元件3的一侧的表面和第二半导体元件8的另一侧的表面粘接,第一半导体元件3和第二半导体元件8层叠在一起(工序O)。这里,小片接合材料7可采用绝缘糊状物或绝缘片,现采用绝缘片。
如图16D所示,利用倒装接合,使所述第一半导体元件3的电极6a的凸点6和载带41的粘接层42接合,第一半导体元件3和第二半导体元件8层叠在载带41上(工序P)。然后,把填充材料4注入第一半导体元件3和载带41之间的间隙和周围部分,以保护凸点6(工序Q)。载带41的内部引线43再与第二半导体元件8的焊盘9连接,使第二半导体元件8和载带41电气连接(工序R)。
如图16E所示,为了保护所述第一、第二半导体元件3、8和内部引线43,密封树脂13从第二半导体元件8的另一侧的表面到载带41填入第一半导体元件3的周围和内部引线43的布线部,来进行密封(工序S)。这里密封树脂13的密封充填区域20形成与第二半导体元件8外形尺寸几乎相同的范围。
最后,如图16F所示,外部端子电极11安装在载带41的另一侧的表面上,完成所述半导体器件的制造。
(所述半导体器件的第二种制造方法)(晶片组件切割法)
参照图17A~图17F说明上述第五实施形态有关的半导体器件的第二种制造方法。
如图17A所示,电极6a设在所述第一半导体元件3的另一侧的表面上。如图17B所示,所述电极6a上形成凸起电极即凸点6。如图17C所示,利用倒装接合使第一半导体元件3的电极6a的凸点6和载带41的一侧的表面的粘接层42接合,第一半导体元件3和载带41层叠(工序P)。再把填充材料4注入第一半导体元件3和载带41间的间隙和周围部分,以保护凸点6(工序Q)。
如图17D所示,所述第二半导体元件8处于多个元件形成一体的(切片前的)晶片基板15的状态,第一半导体元件3的一侧的表面通过小片接合材料7与所述晶片基板15的状态下的各第二半导体元件8的另一侧的表面粘接(工序O)。然后,载带41的内部引线43连接第二半导体元件8的焊盘9,使载带41和第二半导体元件8电气连接(工序R)。
如图17E所示,为了保护所述第一、第二半导体元件3、8和内部引线43,密封树脂13从第二半导体元件8的另一侧的表面到载带41充填入第一半导体元件3的周围和内部引线43的布线部,来进行密封(工序S),然后,外部端子电极11装在载带41的另一侧的表面上。
如图17F所示,利用刀片切割树脂密封好的所述晶片基板15,形成一片一片的所述半导体器件,制造过程结束(工序T)。
通过采用该制造工序,能将接合工序、树脂密封工序、切割工序集中起来制造多个半导体器件,能高效地生产。
根据上述第四实施形态的所述半导体器件,和第一、第二实施形态作比较,通过半导体载体1变更为带状载体41、及采用内部引线43代替金属细线10,从而能提供更薄的所述半导体器件。尤其是内部引线43从载带41开始形成一体引出,与第二半导体元件8的焊盘9连接,所以,在载带41的另一侧的表面上无凸起物。即半导体器件的第一现有的例子中,在半导体载体1的另一侧的表面上,有第一半导体元件53上的金属细线60及覆盖保护金属细线60的密封树脂63,故需要一定的厚度。与此相比,第四实施形态的所述半导体器件由于在所述载带41的另一侧的表面上无金属细线10和一定厚度的密封树脂13,所以能做得更加薄。例如若第一实施形态中的金属细线60的高度为100μm,则保护其的密封树脂63的厚度要200μm。由此,能将第四实施形态的所述半导体器件的厚度能做得比其薄200μm左右。
还如图18所示,在所述半导体器件中,可以将多个第一半导体元件3配置在载带81的平面上。
[第六实施形态]
参照图19~21说明本发明有关的半导体器件及其制造方法的第六实施形态。还有,和第一~第五实施形态相同的构件上标注相同标号,其说明从略。
如图19所示,凸出电极即凸点33形成于设置在第一半导体元件3的一侧的表面(以下,在图19中称为上表面)的第五电极即电极面31上。另外,第六电极即电极面32设在第二半导体元件8的另一侧的表面(以下,在图19中称为下表面)的中央部分。再在第二半导体元件8的另一侧的表面的外周部上形成第二电极即焊盘9。
凸点33形成于所述第一半导体元件3的电极面31上。利用倒装接合使所述凸点33通过导电粘接剂5与第二半导体元件8的电极面32接合,将第二半导体元件8层叠在所述第一半导体元件3上。然后,把填充材料4注入所述第一半导体元件3和第二半导体元件8之间形成的间隙及周围部分中,以保护凸点33。
所述第一半导体元件3和第二半导体元件8的连接方法称为COC(Chip-On-Chip芯片上芯片)结构,由此,半导体元件3、8之间能高速动作。
然后,通过小片接合材料7将载带41的一侧的表面和第一半导体元件3的另一侧的表面接合,使载带41和第一半导体元件3层叠。在所述载带41上一体形成的内部连线43与第二半导体元件8的焊盘9电气连接。然后,密封树脂13从第二半导体元件8到载带41填入第一半导体元件3的周围和内部引线43的布线部,以保护第一、第二半导体元件3、8及内部引线43。充填了密封树脂13的密封充填区域(接合区域)20形成于和第二半导体元件8的外形尺寸几乎相同的范围。
(第一种制造方法)
参照图20A~图20F说明第六实施形态的所述半导体器件的第一种制造方法
如图20A所示,电极31设置在所述第一半导体元件3的一侧的表面上。如图20B所示,在所述电极31上形成凸点33。对于凸点33可采用电镀凸点或利用金线的柱形凸点,这里用柱形凸点。
如图20C所示,在所述第二半导体元件8的电极面32上设置凸点座。然后,在所述凸点33上涂导电粘接剂5,利用倒装接合使所述第一半导体元件3的电极面31和第二半导体元件8的电极面32的所述凸点座接合,第一半导体元件3和第二半导体元件8层叠在一起(工序U)。再把填充材料4注入第一半导体元件3和第二半导体元件9之间的间隙和周围部分,以保护凸点33(工序V)。
如图20D所示,将所述载带41通过小片接合材料7与第一半导体元件3的另一侧的表面粘接(工序W)。这里,对于小片接合材料7可采用绝缘糊状物或绝缘片,现采用绝缘片。然后,所述的载带41的内部引线43连接第二半导体元件8的焊盘9,使第二半导体元件8和载带41电气连接(工序X)。
如图20E所示,为保护所述第一、第二半导体元件3、8和内部引线43,从第二半导体元件8的另一侧的表面到载带41将密封树脂13填入第一半导体元件3的周围和内部引线43的布线部,来进行密封。这里,密封树脂13的密封充填区域20形成于和第二半导体元件8的外形尺寸几乎相同的范围(工序Y)。
最后如图20F所示,外部端子电极11装在载带41的另一侧的表面上,完成所述半导体器件的制造。
(所述半导体器件的第二种制造方法)(晶片组件切割法)
参照图21A~图21F说明实施形态6有关的所述半导体器件的第二种制造方法。
如图21A所示,电极面31设置在第一半导体元件3的一侧的表面上。如图2 1B所示,在所述电极面31上形成凸点33。如图21C所示,载带41通过小片接合材料7连接第一半导体器件3的另一侧的表面(工序W)。
如图21D所示,所述第二半导体元件8处于多个形成一体的(切割前的)晶片基板15的状态。利用倒装接合通过导电粘接剂5使第一半导体元件3的电极面31的凸点33和所述晶片基板15的状态下的各第二半导体元件8的电极面32接合,在各第二半导体元件8上分别层叠第一半导体元件3(工序U)。然后,把填充材料4注入第一半导体元件3和第二半导体元件8之间,以保护凸点33(工序V)。载带41的内部引线43再连接第二半导体元件8的焊盘9,使载带41和第二半导体元件8电气连接(工序X)。
如图21E所示,密封树脂13填入所述第二半导体元件8和载带41之间及周围部分,来进行密封。外部端子电极11再装在载带41上(工序Y)。
如图21F所示,用刀片切割晶片基板15,形成一片一片的所述半导体器件,完成所述半导体器件的制造(工序Z)。
通过采用这一制造工序,能将倒装接合工序(工序U)、填充材料的注入工序(工序V)、引线连接工序(工序X)、树脂密封工序(工序Y)、切片工序(工序Z)集中起来制造多个半导体器件,能高效地生产。
根据上述构成,和第一、第二实施例比较,通过利用内部引线43代替金属细线10及将半导体载体1变更为载带41,从而能提供更薄的所述半导体器件。尤其是内部接线43因为从载带41开始形成一体引出并与第二半导体元件8的焊盘9连接,所以所述半导体器件在载带41的另一侧的表面上无凸起物,当然也就薄,并能做成外形也简单的构成,降低外部端子电极11的安装高度h。另外,又因第一半导体元件3和第二半导体元件8采用COC(芯片上芯片)的结构,故第一、第二半导体元件3、8之间能高速动作。
又如图22所示,所述半导体器件也可以将多个第一半导体元件3a、3b配置在载带85的一侧的表面上而构成。
再在上述所有的实施形态的所述半导体器件中,能将易发热的功率IC用作第二半导体元件8。这是由于第二半导体元件8的背面未被树脂密封而露出在外,能有效地散热。这样,本发明也能适用于要求良好散热性的半导体器件。
Claims (22)
1.一种半导体器件,其特征在于,包括
在另一侧的表面上具有第一电极的第一半导体元件;
形成外形尺寸比所述第一半导体元件大、而且与所述第一半导体元件的另一侧的表面粘接并在所述另一侧的表面的外周部设置第二电极的第二半导体元件;
在一侧的表面上形成利用倒装接合与所述第一半导体元件的所述第一电极接合的第三电极的布线基板;
利用引线接合使设在所述布线基板的另一侧的表面的外周部上的第四电极和所述第二半导体元件的所述第二电极连接的金属细线;及
在所述第二半导体元件和所述布线基板之间密封所述第一半导体元件的周围和所述金属细线的布线部的绝缘密封树脂,
所述密封树脂的密封充填区域做成外形尺寸和第二半导体元件几乎相同。
2.一种半导体器件,其特征在于,包括
在一侧的表面上具有第五电极的第一半导体元件;
在另一侧的表面上设置利用引线接合连接所述第五电极的第六电极/而且外形尺寸做得比所述第一半导体元件大并再在所述另一侧的表面的外周部上设置第二电极的第二半导体元件;
一侧的表面粘接并层叠所述第一半导体元件、另一侧的表面的外周部上形成第四电极的布线基板;
利用引线接合连接所述布线基板的所述第四电极和所述第二半导体元件的所述第二电极的金属细线;及
在所述第二半导体元件和所述布线基板之间密封所述第一半导体元件的周围和所述金属细线的布线部的绝缘密封树脂,
所述密封树脂的密封充填区域做成外形尺寸和第二半导体元件几乎相同。
3.如权利要求1或2所述的半导体器件,其特征在于,
外部电极端子凸出设置在所述布线基板的另一侧的表面上,
所述外部电极端子的高度做成比覆盖所述第四电极的所述密封树脂的厚度要厚。
4.如权利要求1或2所述的半导体器件,其特征在于,
外部电极端子凸出设置在所述布线基板的另一侧的表面上,
所述外部电极端子的高度做得比覆盖所述第四电极的所述密封树脂的厚度要厚,
所述第一半导体元件为多个。
5.如权利要求1或2所述的半导体器件,其特征在于,
所述第二半导体元件为易发热的半导体元件
外部电极端子凸出设置在所述布线基板的另一侧的表面上,
所述外部电极端子的高度做得比覆盖所述第四电极的所述密封树脂的厚度要厚。
6.如权利要求1或2所述的半导体器件,其特征在于,包括
在所述布线基板的另一侧的表面上形成所述外部端子电极的凸出面;及形成于所述凸出面的外周部的厚度比所述凸出面薄、而且设置所述第四电极并再覆盖所述密封树脂的后缩面,
覆盖所述第四电极、并从所述凸出面凸出的所述密封树脂的厚度是减去从所述后缩面至所述凸出面的高度。
7.如权利要求1至2所述的半导体器件,其特征在于,包括
在所述布线基板的另一侧的表面上形成所述外部端子电极的凸出面;及形成于所述凸出面的外周部的厚度比所述凸出面薄、而且设置所述第四电极并再覆盖所述密封树脂的后缩面,
覆盖所述第四电极、并从所述凸出面凸出的所述密封树脂的厚度是减去从所述后缩面至所述凸出面的高度,
所述第一半导体元件为多个。
8.如权利要求1或2所述的半导体器件,其特征在于,包括
在所述布线基板的另一侧的表面上形成所述外部端子电极的凸出面;及形成于所述凸出面的外周部的厚度比所述凸出面薄、而且设置所述第四电极并再覆盖所述密封树脂的后缩面,
覆盖所述第四电极、并从所述凸出面凸出的所述密封树脂的厚度是减去从所述后缩面至所述凸出面的高度,
所述第二半导体元件为易发热的半导体元件。
9.一种半导体器件,其特征在于,包括
在另一侧的表面上有第一电极的第一半导体元件;
外形尺寸做得比所述第一半导体元件大、而且还有粘接在所述第一半导体元件的一侧的表面上的粘接面及设在该粘接面的外周部上的第二电极的第二半导体元件;
具有通过倒装接合和所述第一半导体元件的所述第一电极连接的第三电极的载带;
设在所述载带上并连接所述第二半导体元件的所述第二电极的内部引线;及
在所述第二半导体元件和所述内部引线间将所述第一半导体元件的周围和所述引线的布线部密封的绝缘密封树脂,
所述密封树脂的密封充填区域做成外形尺寸和所述第二半导体元件几乎相同。
10.一种半导体器件,其特征在于,包括
在一侧的表面上有第五电极的第一半导体元件;
有在另一侧的表面上形成的第六电极并利用倒装接合使所述第六电极连接所述第五电极而层叠在第一半导体元件的一侧的表面上,而且外形尺寸做成比所述第一半导体元件大、并再在另一侧的表面的外周部上设置第二电极的第二半导体元件;
与所述第一半导体元件的另一侧的表面粘接的载带;
设在所述载带上并连接所述第二半导体元件的第二电极的内部引线;及
在所述第二半导体元件及内部引线间将所述第一半导体元件的周围和所述内部引线的布线部密封的绝缘密封树脂;
所述密封树脂的密封充填区域做成外形尺寸和第二半导体元件几乎相同。
11.如权利要求1、2、9或10中任何一项所述的半导体器件,其特征在于,
所述第一半导体元件为多个。
12.如权利要求1、2、9或10中任何一项所述的半导体器件,其特征在于,
所述第二半导体元件为易发热的半导体元件。
13.一种半导体器件的制造方法,其特征在于,在制造如权利要求1所述的半导体器件时,依次进行以下的工序:
与所述第一半导体元件粘接所述第二半导体元件的工序A、
在所述第一半导体元件和所述布线基板间注入所述填充材料并使其硬化的工序C、
利用引线接合通过金属细线连接所述第二半导体元件的所述第二电极和所述布线基板的所述第四电极的工序D、及
在所述第二半导体元件和所述布线基板之间将所述密封树脂填入所述第一半导体元件的周围和所述金属细线的布线部来进行密封的工序E。
14.一种半导体器件的制造方法,其特征在于,在制造如权利要求1所述的半导体器件时,依次进行以下的工序:
利用倒装接合使形成于所述第一电极的所述凸起电极和所述布线基板的所述第三电极接合、将所述第一半导体元件层叠在所述布线基板上的工序B;
将所述填充材料注入所述第一半导体器件和所述布线基板之间并使其硬化的树脂密封工序C;
将所述第二半导体元件粘接在所述第一半导体元件上的工序A;
利用引线接合通过所述金属细线连接所述第二半导体元件的所述第二电极和所述布线基板的第四电极的工序D;及
在所述第二半导体元件和所述布线基板之间将所述密封树脂填入所述第一半导体元件的周围和所述金属细线的布线部来进行密封的密封工序E。
15.如权利要求13或14所述的半导体器件的制造方法,其特征在于,
所述工序A中的所述第二半导体元件使用多个形成一体的晶片基板状态的元件,
在所述工序E后,进行用切刀切断所述晶片基板、将所述第一半导体元件与所述布线基板叠在一起的所述第二半导体元件互相分开的工序F。
16.一种半导体器件的制造方法,其特征在于,在制造如权利要求2所述的半导体器件时,依次进行以下的工序:
利用倒装接合所述第一半导体元件的所述第一电极和所述第二半导体元件的所述第六电极接合的工序H、
把所述填充材料注入所述第一半导体元件和所述第二半导体元件间的间隙及周围部分使其硬化的工序I、
使所述第一半导体元件和所述布线基板粘接的工序J、
利用引线接合通过金属细线使所述第二半导体元件的所述第二电极和所述布线基板的第四电极连接的工序K、及
在所述第二半导体元件和所述布线基板之间将所述密封树脂填入所述第一半导体元件的周围和所述金属细线的布线部来进行密封的工序L。
17.一种半导体器件的制造方法,其特征在于,在制造如权利要求2所述的半导体器件时,依次进行以下的工序:
使所述第一半导体元件和所述布线基板粘接的工序J、
利用倒装接合使所述第一半导体元件的所述第五电极和所述第二半导体元件的所述第六电极接合的工序H、
将所述填充材料注入所述第一半导体元件和所述第二半导体元件间的间隙及周围部分中并使其硬化的工序I、
利用引线接合通过所述金属细线使所述第二半导体元件的所述第二电极连接所述布线基板的所述第四电极的工序K、及
在所述第二半导体元件和所述布线基板间将所述密封树脂充填入所述第一半导体元件的周围和所述金属细线的布线部来进行密封的工序L。
18.如权利要求16或17所述的半导体器件的制造方法,其特征在于,
所述工序H中的第二半导体元件使用多个形成一体的晶片基板状态的元件,
在所述工序L后,进行用切刀切断所述晶片基板、将所述第一半导体元件与所述布线基板层叠在一起的第二半导体元件互相分开的工序N。
19.一种半导体器件的制造方法,其特征在于,在制造如权利要求9所述的半导体器件时,依次进行以下的工序:
使所述第一半导体元件和所述第二半导体元件粘接的工序O、
利用倒装接合使所述第一半导体元件的所述第一电极和所述载带的所述第七电极接合的工序P、
把填充材料注入所述第一半导体元件和所述载带间的间隙及周围部分中并使其硬化的工序Q、
使所述载带的所述内部引线和所述第二半导体器件的所述第二电极连接的工序R、及
在所述第二半导体元件和所述载带之间将所述密封树脂充填入所述第一半导体元件的周围和所述内部引线的布线部来进行密封的工序S。
20.一种半导体器件的制造方法,其特征在于,在制造如权利要求9所述的半导体器件时,依次进行以下的工序:
利用倒装接合使所述第一半导体元件的所述第一电极和所述载带的所述第七电极接合的工序P、
把所述填充材料注入所述第一半导体元件和所述载带之间的间隙及周围部分并使其硬化的工序Q、
使所述第一半导体元件与多个形成一体的晶片基板状态的所述第二半导体元件粘接的工序O、
使所述载带的所述内部引线与所述第二半导体元件的第二电极连接的工序R、
在所述第二半导体元件和所述载带之间将所述密封树脂填入所述第一半导体元件的周围和内部引线的布线部来进行密封的工序P、及
切割所述晶片基板而将所述第一半导体元件与所述布线基板层叠在一起的所述第二半导体元件互相分开的工序T。
21.一种半导体器件的制造方法,其特征在于,在制造如权利要求10所述的半导体器件时,依次进行以下的工序:
通过倒装接合使所述第一半导体元件的所述第五电极和所述第二半导体元件的所述第六电极接合的工序U、
把所述填充材料注入所述第一半导体元件和所述第二半导体元件之间的间隙及周围部分并使其硬化的工序V、
使所述第一半导体元件和所述载带粘接的工序W、
使所述载带的所述内部引线和所述第二半导体元件的所述第二电极连接的工序X、及
在所述第二半导体元件和所述载带之间将所述密封树脂填入所述第一半导体元件的周围和所述内部引线的布线部来进行密封的工序Y。
22.一种半导体器件的制造方法,其特征在于,在制造如权利要求10所述的半导体器件时,依次进行以下工序:
使所述第一半导体元件和所述载带粘接的工序W、
利用倒装接合使所述第一半导体元件的所述第五电极和多个形成一体的晶片基板状态的所述第二半导体元件的第六电极接合的工序U、
把所述填充材料注入所述第一半导体元件和所述第二半导体元件之间的间隙和周围部分并使其硬化的工序V、
使所述载带的所述内部引线连接所述第二半导体元件的所述第二电极的工序X、
将所述密封树脂填入所述第二半导体元件和所述载带之间来进行密封的工序Y、及
切割所述晶片基板并将所述第一半导体元件与所述布线基板层叠在一起的所述第二半导体元件互相分开的工序。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003398288 | 2003-11-28 | ||
JP2003398288 | 2003-11-28 | ||
JP2004197483A JP2005183923A (ja) | 2003-11-28 | 2004-07-05 | 半導体装置およびその製造方法 |
JP2004197483 | 2004-07-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1622328A true CN1622328A (zh) | 2005-06-01 |
Family
ID=34622222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2004100956257A Pending CN1622328A (zh) | 2003-11-28 | 2004-11-26 | 半导体器件及其制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7298045B2 (zh) |
JP (1) | JP2005183923A (zh) |
KR (1) | KR100771936B1 (zh) |
CN (1) | CN1622328A (zh) |
TW (1) | TWI260058B (zh) |
Families Citing this family (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6906416B2 (en) * | 2002-10-08 | 2005-06-14 | Chippac, Inc. | Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package |
KR101313391B1 (ko) * | 2004-11-03 | 2013-10-01 | 테세라, 인코포레이티드 | 적층형 패키징 |
US7364945B2 (en) | 2005-03-31 | 2008-04-29 | Stats Chippac Ltd. | Method of mounting an integrated circuit package in an encapsulant cavity |
WO2006118720A2 (en) * | 2005-03-31 | 2006-11-09 | Stats Chippac Ltd. | Semiconductor assembly including chip scale package and second substrate and having exposed substrate surfaces on upper and lower sides |
US7354800B2 (en) | 2005-04-29 | 2008-04-08 | Stats Chippac Ltd. | Method of fabricating a stacked integrated circuit package system |
US7394148B2 (en) | 2005-06-20 | 2008-07-01 | Stats Chippac Ltd. | Module having stacked chip scale semiconductor packages |
US7749806B2 (en) * | 2005-09-22 | 2010-07-06 | Chipmos Technologies Inc. | Fabricating process of a chip package structure |
JP4466552B2 (ja) * | 2005-12-09 | 2010-05-26 | ソニー株式会社 | 固体撮像装置の製造方法 |
US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
US7456088B2 (en) | 2006-01-04 | 2008-11-25 | Stats Chippac Ltd. | Integrated circuit package system including stacked die |
US7768125B2 (en) | 2006-01-04 | 2010-08-03 | Stats Chippac Ltd. | Multi-chip package system |
US8012867B2 (en) * | 2006-01-31 | 2011-09-06 | Stats Chippac Ltd | Wafer level chip scale package system |
US7750482B2 (en) | 2006-02-09 | 2010-07-06 | Stats Chippac Ltd. | Integrated circuit package system including zero fillet resin |
US8704349B2 (en) | 2006-02-14 | 2014-04-22 | Stats Chippac Ltd. | Integrated circuit package system with exposed interconnects |
US7710735B2 (en) * | 2006-04-01 | 2010-05-04 | Stats Chippac Ltd. | Multichip package system |
KR100807352B1 (ko) * | 2006-05-09 | 2008-02-28 | 텔레포스 주식회사 | 전극 패드 상에 다수 개의 돌기부들을 구비하는 전극, 이를 구비하는 부품 실장 구조를 갖는 전자기기 및 전자기기의 부품 실장 방법 |
JP2008166438A (ja) | 2006-12-27 | 2008-07-17 | Spansion Llc | 半導体装置およびその製造方法 |
JP2009026861A (ja) * | 2007-07-18 | 2009-02-05 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US8722457B2 (en) * | 2007-12-27 | 2014-05-13 | Stats Chippac, Ltd. | System and apparatus for wafer level integration of components |
US11018133B2 (en) * | 2009-10-12 | 2021-05-25 | Monolithic 3D Inc. | 3D integrated circuit |
US10910364B2 (en) * | 2009-10-12 | 2021-02-02 | Monolitaic 3D Inc. | 3D semiconductor device |
JP2011146519A (ja) * | 2010-01-14 | 2011-07-28 | Panasonic Corp | 半導体装置及びその製造方法 |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
KR101075241B1 (ko) | 2010-11-15 | 2011-11-01 | 테세라, 인코포레이티드 | 유전체 부재에 단자를 구비하는 마이크로전자 패키지 |
US20120146206A1 (en) | 2010-12-13 | 2012-06-14 | Tessera Research Llc | Pin attachment |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US8404520B1 (en) | 2011-10-17 | 2013-03-26 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8372741B1 (en) | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9136254B2 (en) | 2013-02-01 | 2015-09-15 | Invensas Corporation | Microelectronic package having wire bond vias and stiffening layer |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05275578A (ja) * | 1992-03-27 | 1993-10-22 | Toshiba Corp | 半導体装置 |
JPH1084076A (ja) | 1996-09-05 | 1998-03-31 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2000243875A (ja) * | 1999-02-23 | 2000-09-08 | Shinko Electric Ind Co Ltd | 半導体装置 |
JP3701542B2 (ja) * | 2000-05-10 | 2005-09-28 | シャープ株式会社 | 半導体装置およびその製造方法 |
JP2002110851A (ja) * | 2000-10-03 | 2002-04-12 | Rohm Co Ltd | 半導体チップおよびそれを用いた半導体装置 |
JP2002270763A (ja) | 2001-03-14 | 2002-09-20 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP3910937B2 (ja) | 2003-05-26 | 2007-04-25 | 沖電気工業株式会社 | 半導体装置 |
-
2004
- 2004-07-05 JP JP2004197483A patent/JP2005183923A/ja active Pending
- 2004-11-23 TW TW093135916A patent/TWI260058B/zh not_active IP Right Cessation
- 2004-11-24 US US10/995,140 patent/US7298045B2/en active Active
- 2004-11-24 KR KR1020040096865A patent/KR100771936B1/ko not_active IP Right Cessation
- 2004-11-26 CN CNA2004100956257A patent/CN1622328A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
US7298045B2 (en) | 2007-11-20 |
KR100771936B1 (ko) | 2007-10-31 |
TWI260058B (en) | 2006-08-11 |
US20050116353A1 (en) | 2005-06-02 |
JP2005183923A (ja) | 2005-07-07 |
TW200524067A (en) | 2005-07-16 |
KR20050052356A (ko) | 2005-06-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1622328A (zh) | 半导体器件及其制造方法 | |
CN1161834C (zh) | 半导体器件及其制造方法 | |
CN1122304C (zh) | 树脂封装型半导体装置的制造方法 | |
CN1185709C (zh) | 半导体装置及其制造方法 | |
CN1041035C (zh) | 多芯片模块 | |
CN1779951A (zh) | 半导体器件及其制造方法 | |
CN1755907A (zh) | 半导体器件的制造方法 | |
CN1835222A (zh) | 半导体器件及其制造方法 | |
CN1929159A (zh) | 半导体发光装置 | |
CN1913187A (zh) | 在导热部分中具有凹部的led封装 | |
CN1445851A (zh) | 轻薄叠层封装半导体器件及其制造工艺 | |
CN1172438C (zh) | 封装有电路装置的电子部件及其制造方法 | |
CN1338779A (zh) | 半导体器件 | |
CN1532932A (zh) | 半导体装置及其制造方法、电子设备、电子仪器 | |
CN1207585A (zh) | 半导体装置及半导体装置的引线框架 | |
CN1381886A (zh) | 半导体器件和封装及其制造方法 | |
CN1877824A (zh) | 半导体器件、层叠式半导体器件和半导体器件的制造方法 | |
CN1641873A (zh) | 多芯片封装、其中使用的半导体器件及其制造方法 | |
CN1956183A (zh) | 电子部件内置式基板及其制造方法 | |
CN1581474A (zh) | 无引线型半导体封装及其制造方法 | |
CN101047146A (zh) | 半导体器件的制造方法 | |
CN1767177A (zh) | 半导体器件以及电子设备 | |
CN1397105A (zh) | 使用压电振动器的振荡电路容器及其制造方法和振荡器 | |
CN1767186A (zh) | 引线框架及其半导体封装 | |
CN1160781C (zh) | 分立半导体器件及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |