JP4802155B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP4802155B2 JP4802155B2 JP2007205746A JP2007205746A JP4802155B2 JP 4802155 B2 JP4802155 B2 JP 4802155B2 JP 2007205746 A JP2007205746 A JP 2007205746A JP 2007205746 A JP2007205746 A JP 2007205746A JP 4802155 B2 JP4802155 B2 JP 4802155B2
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- JP
- Japan
- Prior art keywords
- strip
- flip
- wiring conductor
- conductive protrusion
- resist layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
(1)絶縁層と配線導体とが交互に積層されており、最外層の絶縁層上に半導体素子接続用の帯状配線導体が複数並設されているとともに、各帯状配線導体上の一部に半導体素子の電極端子がフリップチップ接続されるフリップチップ用導電突起が前記帯状配線導体の幅と一致する幅で形成されており、かつ前記最外層の絶縁層上および前記帯状配線導体上に前記フリップチップ用導電突起の少なくとも上面を露出させるソルダーレジスト層が被着された配線基板であって、前記各帯状配線導体上の一部に、さらに電気テスト用のプローブが接続されるテスト用導電突起が前記帯状配線導体と一致する幅でかつ隣接するテスト用導電突起と位置をずらして形成されているとともに、各テスト用導電突起の上面が前記ソルダーレジスト層から露出していることを特徴とする配線基板。
(2)前記テスト用導電突起が、前記フリップチップ用導電突起を挟んで該突起の両側に交互に位置をずらせて形成されている前記(1)記載の配線基板。
(3)前記帯状配線導体の幅が30μm以下であり、互いに隣接する帯状配線導体間の間隔が45μm以下である前記(1)または(2)記載の配線基板。
(4)前記テスト用導電突起の上面と、その周囲の前記ソルダーレジスト層の上面とが実質的に同じ高さである前記(1)〜(3)のいずれかに記載の配線基板。
(5)前記フリップチップ用導電突起の上面と、その周囲の前記ソルダーレジスト層の上面とが実質的に同じ高さである前記(1)〜(4)のいずれかに記載の配線基板。
(6)前記フリップチップ用導電突起の長さが、該フリップチップ用導電突起の幅よりも長い前記(1)〜(5)のいずれかに記載の配線基板。
特に、前記(3)のように、帯状配線導体の幅が30μm以下であり、互いに隣接する帯状配線導体間の間隔が45μm以下である場合には、本発明にかかる配線基板の有用性がより向上する。
テスト用導電突起13は、隣接するテスト用導電突起13と位置をずらして形成されていればよく、例えば図6に示すような千鳥配置で形成されていてもよい。
3 絶縁基板
4 絶縁層
5 第二の配線導体
5a 半導体素子接続用の帯状配線導体
5b 外部接続用の配線導体
6 ソルダーレジスト層
6a ソルダーレジスト層用の樹脂
7 スルーホール
8 埋め込み樹脂
9 ビアホール
10 配線基板
12 フリップチップ用導電突起
13 テスト用導電突起
51 下地金属層
101 半導体集積回路素子
110 導電バンプ
111 半田ボール
112 充填樹脂
A1 第一開口
A2 第二開口
A3 第三開口
R1 第一レジスト層
R2 第二レジスト層
Claims (6)
- 絶縁層と配線導体とが交互に積層されており、
最外層の絶縁層上に半導体素子接続用の帯状配線導体が複数並設されているとともに、各帯状配線導体上の一部に半導体素子の電極端子がフリップチップ接続されるフリップチップ用導電突起が前記帯状配線導体の幅と一致する幅で形成されており、
かつ前記最外層の絶縁層上および前記帯状配線導体上に前記フリップチップ用導電突起の少なくとも上面を露出させるソルダーレジスト層が被着された配線基板であって、
前記各帯状配線導体上の一部に、さらに電気テスト用のプローブが接続されるテスト用導電突起が前記帯状配線導体と一致する幅でかつ隣接するテスト用導電突起と位置をずらして形成されているとともに、各テスト用導電突起の上面が前記ソルダーレジスト層から露出していることを特徴とする配線基板。 - 前記テスト用導電突起が、前記フリップチップ用導電突起を挟んで該突起の両側に交互に位置をずらせて形成されている請求項1記載の配線基板。
- 前記帯状配線導体の幅が30μm以下であり、互いに隣接する帯状配線導体間の間隔が45μm以下である請求項1または2記載の配線基板。
- 前記テスト用導電突起の上面と、その周囲の前記ソルダーレジスト層の上面とが実質的に同じ高さである請求項1〜3のいずれかに記載の配線基板。
- 前記フリップチップ用導電突起の上面と、その周囲の前記ソルダーレジスト層の上面とが実質的に同じ高さである請求項1〜4のいずれかに記載の配線基板。
- 前記フリップチップ用導電突起の長さが、該フリップチップ用導電突起の幅よりも長い請求項1〜5のいずれかに記載の配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007205746A JP4802155B2 (ja) | 2007-08-07 | 2007-08-07 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007205746A JP4802155B2 (ja) | 2007-08-07 | 2007-08-07 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
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JP2009043845A JP2009043845A (ja) | 2009-02-26 |
JP4802155B2 true JP4802155B2 (ja) | 2011-10-26 |
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JP2007205746A Expired - Fee Related JP4802155B2 (ja) | 2007-08-07 | 2007-08-07 | 配線基板 |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014123592A (ja) * | 2012-12-20 | 2014-07-03 | Ibiden Co Ltd | プリント配線板の製造方法及びプリント配線板 |
US9370097B2 (en) * | 2013-03-01 | 2016-06-14 | Qualcomm Incorporated | Package substrate with testing pads on fine pitch traces |
US9049791B2 (en) * | 2013-06-07 | 2015-06-02 | Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co. Ltd. | Terminations and couplings between chips and substrates |
US20220344225A1 (en) * | 2021-04-23 | 2022-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package including test line structure |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0750364A (ja) * | 1993-08-04 | 1995-02-21 | Sony Corp | 部品実装基板及び電子素子 |
JPH0718467U (ja) * | 1993-09-03 | 1995-03-31 | 株式会社ピーエフユー | プリント配線板 |
JPH09191169A (ja) * | 1996-01-10 | 1997-07-22 | Nec Corp | 印刷配線板 |
JP3670917B2 (ja) * | 1999-12-16 | 2005-07-13 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP2006013149A (ja) * | 2004-06-25 | 2006-01-12 | Shinko Seisakusho:Kk | プリント配線板の製造方法 |
JP4444088B2 (ja) * | 2004-12-10 | 2010-03-31 | 新光電気工業株式会社 | 半導体装置 |
JP4769022B2 (ja) * | 2005-06-07 | 2011-09-07 | 京セラSlcテクノロジー株式会社 | 配線基板およびその製造方法 |
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