CN1325136A - 板状体和半导体器件的制造方法 - Google Patents

板状体和半导体器件的制造方法 Download PDF

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Publication number
CN1325136A
CN1325136A CN01111672A CN01111672A CN1325136A CN 1325136 A CN1325136 A CN 1325136A CN 01111672 A CN01111672 A CN 01111672A CN 01111672 A CN01111672 A CN 01111672A CN 1325136 A CN1325136 A CN 1325136A
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Prior art keywords
plate body
cushion block
semiconductor element
wiring
protuberance
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CN01111672A
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CN1173400C (zh
Inventor
坂本则明
小林义幸
阪本纯次
真下茂明
大川克实
前原荣寿
高桥幸嗣
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication of CN1325136A publication Critical patent/CN1325136A/zh
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Abstract

韧性层有一体形成的BGA,作为支持衬底。但是该支持衬底是本来不必要的余料。而且韧性层自身价格高,韧性层的厚度是半导体器件薄型化的障碍。可通过形成由与第二焊接垫块17、布线18和外部取出用电极19实际相同的图形的导电覆盖膜11形成的板状体10、或形成经这个导电覆盖膜11半蚀刻的板状体30,使用半导体制造的后步骤制造BGA的结构的半导体器件23。

Description

板状体和半导体器件的制造方法
本发明涉及板状体和半导体器件的制造方法，尤其是解决BGA(ball gridarray)结构问题。
近年来，IC组件被采用在便携机器和小型高密度机器中，原来的IC组件和其安装概念正发生着巨大变化。具体说，例如电子材料(1998年9月那一期的第22页～)专集“CSP技术和支持其的安装材料与装置”中进行了叙述。
图15涉及把韧性层50用作插入衬底的BGA，图15A是平面图，图15B是沿着A-A线的剖面图。
在这个韧性层50上经粘结剂贴合铜箔图形51。在这个韧性层50上固定IC组件52，在这个IC组件52周围用所述铜箔形成焊接用垫块53。经与这个焊接用垫块53一体形成的布线54形成连接焊锡球用垫块55，在这个连接焊锡球用垫块55上形成焊锡球56。
图15A中以外侧的实线表示韧性层50，粗线的矩形是IC组件52。从图中看到，在这个IC组件52周围形成的焊接用垫块组53…的内侧上分散地形成连接焊锡球用垫块组55…。
这个连接焊锡球用垫块组55…的里侧加工有韧性层50，设置着开口部57，经这个开口部57形成焊锡球56。
所述的韧性层50同样把陶瓷衬底、印刷衬底等用作衬底，是这些衬底中最薄的部件。但是，问题在于韧性层的价格比陶瓷衬底、印刷衬底等的价格高，而且如果包括开口部57的加工费，就大幅度提高了BGA的成本。
要求在便携机器上安装的半导体器件更薄更轻，还要求上述的BGA薄而轻。但是，如果考虑形成Cu箔图形的步骤、装载IC组件52的步骤、以及焊接金属细线58的步骤，韧性层50是必须采用来作为支持衬底的部件，没有韧性层50时，不可能考虑制造方法。
而且，Cu箔图形通过粘结剂贴合在韧性层50上，也有这个Cu箔图形变形或脱落的问题。特别是IC组件52的垫块数目逐年增加，如果以BGA来实现，必须使Cu箔图形精细化。因此，布线54、焊接垫块53的接触面积减少，更容易发生Cu箔图形变形或脱落的问题。
而且如果考虑制造方法，有这样的问题：由于半导体制造者(maker)把预定的图形数据传送给韧性层制造者，韧性层制造者进行图形化后制造韧性层，半导体制造者购入完成这些后的韧性层，这样到制造BGA之前的时间非常短。因此，半导体制造者也有不能在短的交货期内把所述BGA交货给用户的问题。
由于IC组件52介于韧性层50之间，还有放热性差的问题。
本发明鉴于前述的多个问题而作出，首先，是作为一种板状体，具有平坦面构成的第一表面和与所述第一表面相对设置的由平坦面构成的第二表面，在所述第二表面上形成第一导电覆盖膜，该第一导电覆盖膜具有与下面所述的实质相同的图形：半导体元件装载区域的周围设置焊接垫块、与这个焊接垫块一体地向所述半导体元件装载区域延伸布线以及与该布线一体设置外部取出用电极。
其次，是作为一种板状体，具有平坦面构成的第一表面和与所述第一表面相对设置的由平坦面构成的第二表面，在所述第二表面上形成光刻胶，该光刻胶具有与下面所述的实质相同的图形：半导体元件装载区域的周围设置焊接垫块、与这个焊接垫块一体地向所述半导体元件装载区域延伸布线以及与该布线一体设置外部取出用电极。
第三，在对应于所述焊接垫块的区域设置导电覆盖膜，形成所述光刻胶以覆盖该导电覆盖膜。
通过经在板状体上形成的导电覆盖膜或光刻胶进行半蚀刻，可形成由板状体支持的导电图形，因此，半导体制造者通过拥有光刻设备就能独立地连续地制造板状体甚至半导体器件。
半导体元件的固定、使用金属细线的电连接、使用绝缘树脂的封装步骤能采用这种板状体作为支持衬底，而不需要原来作为支持衬底的韧性层。尤其，由于焊接垫块以细小的岛状存在、布线细长，即使不稳定状态的配置也由于和板状体成一整体存在而可能没有反向和剥落等变形。
通过经施压和蚀刻等从外表向里面进行穿透板状体的图形、中途停止的半蚀刻，能把导电图形的间隔加工地狭窄，能形成更细小的图形。而且，封装绝缘树脂来完全固定后，通过研磨、蚀刻板状体的里面等加工，可分离垫块和布线等，即使没有位置偏离，也能配置在预定位置上，而且即使引回布线长，也能进行没有变形的配置。
半蚀刻作为掩膜的光刻胶时，通过在焊接垫块部分上留下导电覆盖膜，能通过下面的步骤容易实现线焊接。
第四，由于在所述板状体的相对的侧边上形成与导销实质相同的图形，或形成插入所述导销的引导孔，模压时能高精度地实施所述板状体的金属模安装。
第五，所述板状体以导电箔构成，所述导电覆盖膜由与所述导电箔的材料不同的材料构成。
通过形成导电覆盖膜，凸部的侧面变弯曲，而且导电覆盖膜自身上形成遮盖件。顺便说一下，作为图形的焊接垫块和布线等被埋入具有锚定效果的绝缘树脂中。
第六，作为一种板状体，具有平坦面构成的第一表面和具有形成预定高度的凸部的、与所述第一表面相对形成的第二表面，所述凸部的构成为：半导体元件装载区域的周围设置的焊接垫块、与这个焊接垫块一体地向所述半导体元件装载区域延伸的布线以及与该布线一体设置外部取出用电极。
第七，所述凸部的表面设置导电覆盖膜。
第八，在至少对应于所述焊接垫块的区域设置导电覆盖膜。
第九，所述板状体以导电箔构成，所述导电覆盖膜由与所述导电箔的材料不同的材料构成。
在凸部构成导电图形的板状体可以是半导体元件安装、垫块的电连接和封装等半导体制造的后面步骤的设备。因此，与原来的引线框架一样，从例如制造者供应板状体，半导体制造者可制造BGA型的半导体器件。
半导体元件的固定、使用金属细线的电连接、使用绝缘树脂的封装步骤能采用这种板状体作为支持衬底，而不需要原来的韧性层。尤其，由于焊接垫块以岛状存在，即使不稳定状态的配置由于其和板状体成一整体也可能没有反向和剥落等变形。而且布线被延长，即使发生了反向、扭转，由于和板状体成一整体，也能解决这些问题。
由于以半蚀刻形成，能把垫块或布线等的间隔加工得狭窄，能形成更细小的垫块。而且，封装绝缘树脂并完全固定后，通过研磨、蚀刻板状体的里面等加工，可分离垫块、衬垫(tie pad)和布线等，即使没有位置偏离，也能配置在预定位置上。
第十，在所述板状体的相对的侧边上形成与导销实质相同的图形的凸部，或形成插入所述导销的引导孔。
第十一，在所述板状体上把所述凸部形成的预定图形配置成矩阵状，可大量生产。
第十二，所述板状体由Cu,Al,Fe-Ni合金，Cu-Al集层体或Al-Cu-Al的集层体构成。
第十三，所述凸部的侧面具有锚定结构。
第十四，所述导电覆盖膜在所述凸部的上面形成遮盖件。
第十五，通过把所述导电覆盖膜由Ni,Au,Ag或Pd构成而可具有锚定效果，同时，可进行线焊接、小片焊接(die bonding)。
第十六，作为一种板状体，具有在对应于树脂封装区域的整个面上逐渐过渡的平坦里面和形成凸部的表面，该凸部以从所述里面开始的预定厚度形成层状，在由与上面的金属模对接的区域所包围的区域中，由在半导体元件装载区域的周围设置的焊接垫块、与这个焊接垫块一体地向所述半导体元件装载区域延伸的布线以及与该布线一体设置外部取出用电极构成，至少由与所述上面的金属模对接的区域所包围的区域通过所述表面和所述上面金属模构成封闭空间。
第十七，具有步骤：准备一种板状体，该板状体具有在对应于树脂封装区域的整个面上逐渐过渡的平坦里面和形成凸部的表面，该凸部以从所述里面开始的预定厚度形成层状，由在与上面的金属模对接的区域所包围的区域中设置的焊接垫块、与这个焊接垫块一体地向所述半导体元件装载区域延伸的布线以及与该布线一体设置外部取出用电极构成；
在所述半导体元件装载区域装载半导体元件的同时，电连接所述焊接垫块和所述半导体元件；
把所述板状体装载到金属模中、把树脂填充到所述板状体和所述上面金属模构成的空间中；
取出在所述填充的树脂的里面上露出的板状体，分别把所述凸部分离开。
第十八，根据权利要求17的制造半导体器件的方法，其特征在于对应于所述树脂封装区域的所述板状体的里面的全部区域与下面金属模对接。
第十九，所述下面金属模的对接区域分散配置着抽取真空装置。
板状体由于形成层状，板状体的里面整个面被逐渐过渡地对接于下金属模，而且垫块等的导电图形由于配置在所述封闭空间内而根本不会把溢料排除到板状体的里面。
上面由于半导体器件可以通过导电图形、半导体元件及封装它们的绝缘树脂构成而没有韧性层，可实现半导体器件的薄型化和轻型化。而且，通过埋置导电电路或在导电箔的表面上形成导电覆盖膜，可形成在表面上具有遮盖件的焊接垫块和布线等，能产生锚定效果，实现了防止导电图形反向、脱落等的变形的BGA型半导体器件。
图1是说明本发明的板状体的图；
图2是说明本发明的板状体的图；
图3是说明采用本发明的板状体的半导体器件的制造方法的图；
图4说明采用本发明的板状体的半导体器件的制造方法的图；
图5是说明本发明的板状体的图；
图6是说明本发明的板状体的图；
图7是说明采用本发明的板状体的半导体器件的制造方法的图；
图8是说明采用本发明的板状体的半导体器件的制造方法的图；
图9是说明采用本发明的板状体的半导体器件的制造方法的图；
图10是说明采用本发明的板状体的半导体器件的制造方法的图；
图11是说明把板状体用作引线框架的图；
图12是说明采用本发明的板状体的半导体器件的制造方法的图；
图13是说明采用本发明的板状体的半导体器件的制造方法的图；
图14是说明采用本发明的板状体的半导体器件的制造方法的图；
图15是说明已有的BGA结构的半导体器件的图。
本发明涉及一种半导体器件，其在半导体芯片的周围配置焊接垫块，使用与该焊接垫块一体的布线而把外部取出用电极分散配置成矩阵状。一般地把在外部取出用电极上装配焊锡球的(操作)叫作BGA，在这里把含有以通常的焊锡装配来固定的半导体器件叫作BGA结构的半导体器件。
说明板状体的第一实施例
图1A表示把其效果优化得比采用原来的韧性层的BGA更好、实现更薄的组件的板状体。
如图1A所示，相对于原来的BGA，这个板状体10使在韧性层上印刷的导电图形由导电覆盖膜11形成。
即是说，是具有由平坦面构成的第一表面12和与所述第一表面12相对设置的由平坦面构成的第二表面13的板状体10，在所述第二表面13上在半导体元件装载区域14的周围形成与第二焊接垫块17实质相同的图形的第一导电覆盖膜11A。该第一导电覆盖膜11A被对应于图3所示的半导体元件15上的第一焊接垫块16来设置、形成与第二焊接垫块17实质相同的图形。形成第二导电覆盖膜11B、第三导电覆盖膜11C，其图形与所述的第二焊接垫块17一体地设置的布线18和外部取出用电极19实质相同。还有，这些导电覆盖膜11A～11C可以以同一材料构成，也可以以不同材料构成。但是，如后面的制造方法所判断的那样，导电覆盖膜11A～11C选择有效的材料作为耐蚀刻掩膜，而且导电覆盖膜11A的表面选择能以球焊法和超声波焊接法等施加Au和Al等构成的金属细线20的材料。
在图1～3的说明中判断采用面朝下型元件(SMD)作为半导体元件15时，导电覆盖膜11A选择能固定焊料、导电膏的材料。
在图1B中，这个板状体10替代所述导电覆盖膜11可形成光刻胶等的耐蚀刻掩膜MSK。此时，可进行使用金属细线的焊接或面朝下焊接，至少对应于第二焊接垫块1 7的部分上形成导电覆盖膜20，含有该导电覆盖膜的整个图形被光刻胶MSK覆盖。
本发明的特征在于所述板状体。如从后面的说明确定的那样，经板状体10的导电覆盖膜11或光刻胶MSK进行半蚀刻、在其上装载半导体元件15、用绝缘树脂21封装。之后，在由第二焊接垫块、布线18和外部取出用电极19构成的导电图形22被分离之前，蚀刻从绝缘树脂21的里面露出的板状体10，进行研磨或研削加工。通过采用这种制造方法，半导体器件可由半导体元件15、导电图形22、埋置这个半导体元件15和导电图形22的绝缘树脂21共3种材料构成。之后，可使得这个板状体10最终作为BGA结构的半导体器件23。
该结构的最大特征是在半蚀刻的板状体10的表面上形成导电覆盖膜或耐蚀刻掩膜MSK。
一般地，蚀刻可在纵向进行蚀刻，也可在横向上进行蚀刻。例如，各向同性的蚀刻时，明显出现的现象是纵向的蚀刻深度和横向的蚀刻长度实际相同。至于各向异性的蚀刻，横向的蚀刻长度即使比各向同性时小得多，也在所述横向上进行蚀刻。
例如，图15表示的BGA结构的半导体器件中，在形成韧性层50上的导电图形53～55时，必须去掉图形，以从贴合的Cu箔的表面一直贯通到里面。但是，导电图形之间也在横向上被蚀刻，导电图形22和相邻接的导电图形之间的间隔和Cu箔的厚度相关，不能做得比某一界限值小，因此难以形成细小的图形。即使是采用蚀刻型引线框架实现BGA结构的半导体器件时也有同样的现象发生。即使通过施压使引线框架脱开时，引线框架的厚度基本为引线框架的最小间隔，对于细小图形有界限。
但是，在板状体10上形成导电覆盖膜11或耐蚀刻掩膜MSK，之后，如果半蚀刻偏离了适合于形成细小图形的深度，可抑制横向上的蚀刻量，可实现更细小的导电图形22。
例如，2盎司(70微米)厚的板状体10上形成Ni,Ag,Au或Pd等的导电覆盖膜11作为图形化的导电覆盖膜，如果将其作为掩膜进行蚀刻直到把它完全贯通，把导电图形的间隔做得最窄，实际只能达到70微米。但是，把导电覆盖膜11作为耐蚀刻的掩膜使用，如果蚀刻板状体10直到35微米的深度，导电图形的间隔可加工到实际35微米那么窄。即，能实现2倍的安装效率。这种细小图形对应于板状体10的半蚀刻的深度变浅，可得到更细小的图形。
对于本发明的板状体10，考虑蚀刻设备、产量、制造成本，最好用湿蚀刻。但是，湿蚀刻是各向异性的，横向的蚀刻比较多。因此，使用导电覆盖膜11和耐蚀刻掩膜MSK的半蚀刻易于形成更细小的导电图形22。
由于本发明的板状体10中半蚀刻的导电图形22和板状体10一体地形成，不会有板状体10被固定的限制以及导电图形22偏离、反向。因此，具有对第二焊接垫块17的焊接稳定的特征。
而且，以所述的引线框架形成的BGA结构的半导体器件中有必要以吊线支持导电图形，而在本发明中则不必要。因此，不用考虑与吊线的交叉，具有可在任意位置上配置导电图形22从而导电图形22的设计变容易的优点。
板状体10上设置引导孔24时，在金属模上装载板状体10时更方便。
这个引导孔24以与导销实质相同的形状在对应的位置上经导电覆盖膜或光刻胶被图形化成圆形，在模压之前，可沿着这个图形通过钻孔、冲孔或蚀刻等形成开口。或者也可以准备原来已有开口的。通过在这个引导孔L24中插入导销可进行位置精度高的模压。
如上所述，通过经导电图形22、导电覆盖膜11或耐蚀刻掩膜MSK进行半蚀刻，这样可采用原来的韧性层或原来的引线框架。
半导体器件制造者一般有分为前步骤和后步骤的工厂，采用该板状体10进行模压的后步骤中，不设置通常的蚀刻设备。因此，通过设置导电覆盖膜11的成膜设备、蚀刻设备，通过从制造引线框架的金属材料制造者那里购入导电覆盖膜11或耐蚀刻掩膜MSK形成的板状体10，半导体制造者可制造使用这种板状体10的BGA结构的半导体器件23。
还有，如图1C所示，导电图形22可以是从一端到另一端具有实际一定的宽度的布线形状。把图1A、图1B中的垫块11A和电极11C设置成圆形和矩形等，但是可以是任意形状。
说明板状体的第二实施例
如图2所示，板状体30经所述导电覆盖膜11A或耐蚀刻掩膜MSK被汉蚀刻，导电图形22形成凸状。
即，作为具有平坦面构成的第一表面12和与所述第一表面12相对形成的第二表面13的板状体30，所述凸部31由在半导体元件装载区域14的周围设置的第二焊接垫块17、与该第二焊接垫块一体的布线18及与该布线一体的外部取出用电极19构成。
该板状体30与第一实施例说明的板状体10的结构、效果实质相同，。不同的是导电图形22在被半蚀刻的位置上。
因此，这里对半蚀刻位置进行描述。即，半导体制造者特别在后步骤中不需要Cu构成的板状体10的制造设备、蚀刻等的平板印刷设备。因此通过半蚀刻，如果购入具有凸部构成的导电图形22的板状体30，可与原来的引线框架一样的来处理板状体30，经后步骤中已有的设备可制造BGA结构的半导体器件23。
还有凸部构成的导电图形22也可对板状体10施压。施压时，由于第一表面12有飞边，必要时可对第一平面12进行研磨、研削以使之变得平坦。
说明采用板状体的半导体器件的制造方法的第三实施例
采用板状体10或30制造BGA结构的半导体器件23的过程采用图1到图4来说明。半蚀刻图1A的板状体10在图2A中，半蚀刻图1B的板状体10在图2B中。而且，半蚀刻图1C的板状体10在图2C中。图3以后说明采用图1A、图2A的制造。
首先如图1所示样准备板状体10。这个板状体10的第一表面12和第二表面13是平坦的，而且在第二表面13上形成形成有导电图形22的导电覆盖膜11或光刻胶等的耐蚀刻掩膜MSK。还有图1A中导电图形22的整个面上形成导电覆盖膜11，以斜线对导电覆盖膜11画上阴影线。图1B中不用导电覆盖膜11而采用光刻胶MSK，光刻胶MSK至少覆盖在对应于第二焊接垫块17的部分上形成的导电覆盖膜11A。还有，光刻胶MSK以虚线来界定(以上参考图1)。
接着，经所述导电覆盖膜11或光刻胶MSK半蚀刻板状体10。蚀刻深度比板状体10厚度浅。蚀刻深度浅，则可形成大致一样浅的细小图形。
之后，通过半蚀刻，如图2所示，导电图形22突出呈现在板状体10的第二表面13上。板状体10可以是Cu、Al、Fe-Ni合金、Cu-Al的集层体、Al-Cu-Al的集层体。尤其，Al-Cu-Al的集层体能防止因热膨胀系数的不同引起的反向。
例如，对于半导体制造者而言，如果后步骤中有蚀刻设备，从引线框架制造者购入图1的板状体10，或后步骤中没有蚀刻设备，通过购入半蚀刻后导电图形形成凸状的板状体30，可进行到下面的步骤(以上参考图2)。
接着，把半导体元件15固定在半导体元件装载区域14上，把半导体元件15的第一焊接垫块16和第二焊接垫块17电连接。在图中，由于半导体元件15面朝上安装，采用金属细线26作为连接装置。面朝下安装时，连接装置可考虑焊锡块、焊锡球等的焊料、Ag、Au等的导电膏、导电球或各向异性导电树脂等。
对于这个焊接，第二焊接垫块17与板状体30成为一体，而且板状体30的里面是平面。因此，板状体30与焊接机器的台面面对接。从而如果板状体30与焊接台完全固定，第二焊接垫块17位置即使没有偏离，可把焊接能量高效率地传播到金属细线20和第二焊接垫块17，金属细线20的连接强度可被提高。焊接台的固定例如如图9所示可在台面的整个面上设置多个抽真空孔V。
半导体元件15和板状体30的固定可使用绝缘粘结剂32形成，考虑放热性，也可混合硅酸、铝酸等的填料到该绝缘粘结剂32中。
之后，形成绝缘树脂21来覆盖所述导电图形、半导体元件57和连接装置。
例如使用金属模封装时，这个阶段使引导孔24开口，在开口插入金属模的导销。由于板状体30的第一表面12是平坦的，下金属模的面也形成平坦的。作为绝缘树脂21热塑性、热固性都可以。
这个模压可通过转移膜、注射膜、浸入或涂覆实现。作为树脂材料，环氧树脂等的热固化树脂可以以转移膜实现，液晶聚合物、对聚苯硫等的热塑性树脂可以以注射膜实现。
本实施例调整成使得绝缘树脂21的厚度从金属细线20的顶部算起向上约被覆盖100微米。这种厚度可考虑半导体器件23的强度而做得更厚，也可做得更薄。
关于注入，由于导电图形22和层状板状体30一体形成，如果板状体30的偏离没有限制，可一点没有导电图形22的位置偏离。这里下金属模与板状体30的里面固定也通过抽真空实现。可使用在金属模上配置的抑制销。
上面，绝缘树脂21中埋入作为凸部31形成的导电图形22和半导体元件15，并非凸部31而是下面的板状体30从里面露出来(上面参考图3)。
接着，取出露出所述绝缘树脂21的里面的板状体30，分别分离导电图形22。
这个分离步骤可考虑各种方法，可以通过蚀刻从里面取出，也可以通过研磨、研削等进行。也可采用两种方法。例如，在通过切削至露出绝缘树脂21时，出现夹在板状体30的切口和外侧上变薄的毛刺状的金属被吞入绝缘树脂21中的问题。因此，绝缘树脂21露出步骤之前，停止切削，之后通过蚀刻分离导电图形22时，导电图形22之间分布的绝缘树脂21中不会吞入板状体30的金属，这样，可防止细小间隔的导电图形22相互之间的短路。
在半蚀刻中，根据蚀刻深度的变化，导电图形22之间的绝缘树脂21可产生厚度的变化。因此分离导电图形22后，可通过研磨、研削等切削成目标厚度而形成精度高的一定厚度的组件。
之后，形成多个由半导体器件23构成的1个单元时，在分离步骤后，是切割成为单个半导体器件23的步骤。在图中以虚线表示切割线。
这里采用切割装置来分离成每一个，但是也可通过切开巧克力、施压和切割等方式进行。
露出里面的导电图形22如图4所示由绝缘树脂R覆盖，也可露出对应于外部取出用电极19的部分。这个露出的外部取出用电极19考虑与安装衬底的连接，选择焊锡球等的导电球的装配、焊锡球等的焊料或Ag粘结剂等的导电膏的附图、各向异性导电树脂的涂布等的连接装置。
在图4C中，经在外部取出用电极19上形成的光刻胶进行蚀刻，把外部取出用电极19形成凸状。接着，涂覆绝缘树脂R以露出外部取出用电极19。
如图4B、图4C所示，通过在里面上涂覆绝缘树脂，可使安装衬底侧的布线通过下层(以上参考图4)。
通过上面的制造方法，经多个导电图形22、半导体元件15和绝缘树脂31光3个要素可产生较轻薄而短小的BGA结构的半导体器件。
接着说明以上的制造方法产生的效果。
首先，第一，由于导电图形22被半蚀刻、与板状体30构成一体而被支持，可没有作为支持衬底用的韧性层。
第二，由于板状体30形成半蚀刻后构成凸部的导电图形22，可进行导电图形22的细小化。因此，导电图形22的宽度、导电图形22的间距可变狭窄，可形成平面大小的小组件。
第三，由于以所述3要素形成，可以必要的最小限度来形成，没有任何材料的浪费，可实现大幅度抑制成本的薄型半导体器件23。
第四，由于第二焊接垫块17、布线18和外部取出用电极19以半蚀刻形成凸部来形成并各自分离或封装后进行，采用引线框架的系杆(tie bar)、吊线等不再必要，图形设计容易了。
还有，这个BGA结构的半导体器件中仅安装一个半导体元件，但是也可安装多个。
说明板状体的第四实施例
与第一实施例同样，图5表示通过导电覆盖膜11形成导电图形22的板状体10。而且可以替代导电覆盖膜11，形成光刻胶等的耐蚀刻掩膜。此时，在与焊接垫块对应的部分上形成导电覆盖膜，形成也包括导电覆盖膜的光刻胶的图形。
图5的图形比图1更具体化，具体说，由以虚线包围的导电图形形成一个半导体器件所构成的图形单元34被形成矩阵状，包围该矩阵的金属模对接区域35具有预定宽度，形成为环状。即图5的图形表示在一个腔(cavity)内形成的导电图形。
在这个金属模对接区域35内侧设置位置符合标志36、37。连接符合标志36A和37A的线表示横向的切割线，连接符合标志36B和37B的线表示纵向的切割线。各个符合标志至少以一根短直线形成，根据这条直线，切割装置的刀刃的方向可被调整。这里符合标志被设置成要求的间隔(margin)，以两条直线构成，以便以要求的精度来进行切割。
而且，上述的金属模对接区域35的外侧形成用来形成引导孔的第一图形38、第二图形39。第二图形39的十字是以钻孔机形成引导孔时的对准标志。可不形成这个图形，而设置与预定的第一图形相同形状的引导孔。
由于上面除去切割线标志、金属模对接区域35外与第一实施例相同，本实施例的特征和效果等省略了。
说明板状体的第五实施例
如图6所示，板状体30经第四实施例所示的导电覆盖膜11或光刻胶等的耐蚀刻掩膜被半蚀刻并具有凸部31。第一符合标志28、第二符合标志39也通过半蚀刻形成凸状。
板状体30可进行与原来的引线框架，例如SIP、DIP、QIP等同样的处理。
形成具有平坦面构成的第一表面12和具有以预定高度形成的凸部31、与所述第一表面12相对形成的第二表面13的板状体30，
所述凸部31由在半导体元件装载区域14的周围形成的第二焊接垫块17、与该第二焊接垫块17一体地设置的布线18和与布线18一体地设置的外部取出用电极19构成。
该板状体30具有在各个图形被半蚀刻的状态中，可能进行原封不动地半导体元件的固定、电连接、封装、可由后面步骤中已有的设备进行制造的特征。
由于效果与第一实施例、第四实施例说明的相同，省略了对其的说明。
说明半导体器件的制造方法的第六实施例
接着使用图5到图11来说明制造方法。
首先如图5所示样准备板状体10。这个板状体10考虑焊料的粘着性、焊接性、电镀性选择其材料，作为材料，采用以Cu为主材料的导电箔、以铝为主材料的导电箔或以Fe-Ni等合金构成的层状的导电箔、Cu-Al的集层体、Al-Cu-Al的集层体等。之后，在这个板状体10的表面上，通过导电覆盖膜11或掩膜形成第二焊接垫块17、布线18、外部取出用电极19、金属模对接区域35、符合标志36、37、图形38、39。
作为板状体10采用的导电箔的厚度考虑最后的蚀刻最好是10微米到300微米左右，这里采用70微米(2盎司)的铜箔。但是，即使在300微米以上10微米以下基本上也是可以的(以上参考图5)。
接着，是把除第二焊接垫块17、布线18、外部取出用电极19、金属模对接区域35、符合标志36、37、图形38、39构成的区域以外的板状体10减薄到比板状体10的10厚度浅的步骤。
这里，把导电覆盖膜11或光刻胶块17作为耐蚀刻掩膜使用，形成比板状体10的厚度浅的所述分离沟40。
本制造方法中具有通过湿蚀刻或干蚀刻被非各向异性的蚀刻，其侧面是粗表面，而且变弯曲的特征。
湿蚀刻时，腐蚀剂一般采用二价铁盐或二价铜盐，所述导电箔被浸入在这个腐蚀剂中或在这个腐蚀剂中被淋湿(showering)。
特别是蚀刻掩膜构成的导电覆盖膜11或光刻胶的下面进行横向的蚀刻，在横向上对更深的部分进行蚀刻。因此，由于从分离沟40的一侧面向上与该位置对应的开口部的口径变小，成为倒锥体结构，构成具有锚定结构的结构。通过淋湿，蚀刻朝着深度方向上进行，为抑制横向的蚀刻，显然要有这个锚定结构。
干蚀刻时，可进行各向异性的、各向同性的蚀刻。现在以反应离子蚀刻来除去Cu是不可能的，但是能除去溅射方法除去。根据溅射的条件可以是各向异性的、各向同性的。
考虑作为导电覆盖膜的材料是Ni,Ag,Au,Pt或Pd等。但是，这些耐蚀性的导电覆盖膜具有能原样用作焊接垫块的特征。
例如，把au细线连接于Ag,Au的导电覆盖膜上。可进行Ni与Al线和超声波焊接。因此，这些导电覆盖膜具有能原样用作焊接垫块的优点。
当然，这里可通过各向异性蚀刻形成凸部(以上参考图6)。
接着，如图7所示，在半导体安装区域14上安装半导体元件15。
作为半导体元件15，是晶体管、二极管IC组件等。厚度变厚，但？型CSP、BGA等的SMD(面朝下的半导体元件)也能安装。
这里，空白的IC芯片15通过绝缘粘结剂32被固定，IC新品15上的第一焊接垫块16和第二焊接垫块17经通过热压的焊接或超声波的线焊接等而固定的金属细线20连接。
如图所示，第二焊接垫块17其尺寸非常小，与板状体30成一体。因此，可把焊接工具17的能量传送到焊接垫块17，提高焊接性。对于焊接后的金属细线的切割，是完全切割金属细线的情况。此时，由于第二焊接垫块17与板状体10成一体，没有焊接垫块17浮起来的现象，提高了完全切割性能(以上参考图7)。
而且，如图8所示，有在分离沟40上附着绝缘树脂20的步骤。这是通过转移膜、注射膜、浸入或涂覆实现。作为树脂材料，环氧树脂等的热固化树脂可以以转移膜实现，液晶聚合物、对聚苯硫等的热塑性树脂可以以注射膜实现。
本实施例调整成使得绝缘树脂21的厚度从金属细线20的顶部算起向上约被覆盖100微米。这种厚度可考虑半导体器件的强度而做得更厚，也可做得更薄。
该步骤的特征是覆盖绝缘树脂21、直到硬度之前，板状体30构成支持衬底。已有的BGA需要韧性层的支持衬底，本发明则不需要。
而且由于在具有弯曲结构的分离沟40中填充绝缘树脂21，这一部分产生锚定效果，所述导电图形22难以从绝缘树脂21剥落。
涂覆这个绝缘树脂21之前，为保持例如半导体芯片、金属细线等的连接部，可以焊接硅树脂等。
图9表示这个模压方法。图9A是表示在金属模100内的腔101内填充绝缘树脂21的状态的剖面图。板状体30的里面与下金属模100A对接，判断出上金属模100B在金属模对接区域35对接。符号V是真空抽取孔。图9B表示在下金属模100A上安装斑板状体30的状态。符号102是在下金属模100A上安装的引导孔，导参102经开口的引导孔从板状体30上露出来。
图9C说明金属模上形成的腔101、浇道103和坩锅(pot)之间的关系。如图所示，数个腔101被排列在横向上，设计成在一个帧中可取出多个半导体器件。以虚线表示的符号105表示板状体的配置区域，例如图11的板状体106通过与原来的引线框架一样地处理来安装。这里多个图6的板状体30一体形成。通过这种板状体制造的半导体器件自身尺寸小，而且一个腔内可有多个，可提高产量，从而有制造成本降低的特征(以上参考图8和图9)。
接着，从金属模取出封装好的板状体30，把从绝缘树脂21里面露出的板状体30拿开，进行分离导电图形22的步骤。
图10A是分离线的平面图，图10B是绝缘树脂21的里面和第二焊接垫块17的里面或绝缘树脂21的里面和布线18以及外部取出用电极19的里面一致的情况。这可通过由研磨装置进行研磨直到分离沟40被露出来来形成。在里面形成焊锡抗蚀剂等的绝缘覆盖膜R，可仅露出点连接必要的部分。
图10表示在中途停止研磨、在外部取出用电极19的另一端11上形成凸部111。在与凸部111对应的部分上形成光刻胶，除此以外的部分可仅是蚀刻。之后，形成绝缘覆盖膜R以使得凸部111露出来。这样作，可防止通过半导体元件15的下面的安装衬底侧的导电体的短路。
最后，把这个模压体配置在切割机上，根据符合标志36,37调整刀刃的位置，沿着以虚线表示的线切割，完成半导体器件。
说明半导体器件的制造方法的第七实施例
接着图12到图14表示在板状体151上安装面朝下型半导体元件150、制造BGA结构的半导体器件。
使用金属细线20时，从半导体装载区域露出导电图形，但是采用面朝下型时，这种露出变少或没有。金属细线20由于其顶部变高，组件的厚度变厚，通过比采用面朝下型可使之变薄。
面朝下型半导体元件采用焊锡球152，也可替代焊锡球152采用焊锡或全凸起。
通过焊锡等的焊料固定半导体元件150时，由于外部取出用电极153以Cu作为主材料，在原来的焊接垫块上不必要在其表面形成导电覆盖膜。但是，为形成遮盖件来产生锚定效果，则是必要的。
由于制造方法与前面的实施例相同，仅作简单说明。
首先如图12所示，准备板状体15，在这个板状体15上固定半导体元件15的焊锡球152。
接着，如图13所示，使用绝缘树脂154来封装。
接着，如图14所示，通过把位于绝缘树脂154的里面的板状体151从里面取出而分离导电图形，沿着以虚线表示的线切割，完成半导体器件。
如图10B、10C所示，组件的里面上覆盖绝缘树脂R，也可以露出与外部取出用电极对应的部分。
对全部实施例而言，在板状体上覆盖蚀刻率小的导电覆盖膜，经这个导电覆盖膜进行半蚀刻，实现了遮盖件和弯曲结构，可具有锚定效果。
例如，在Cu箔上覆盖Ni时，可以以二价铁盐或二价铜盐等一次蚀刻Cu和Ni，适于根据蚀刻率的不同生成遮盖件。
从以上的说明可看到，本发明的板状体具有可经导电覆盖膜或光刻胶进行半蚀刻导电图形的结构。而且可通过施压和蚀刻等形成从外表向里面穿透板状体、中途停止的图形。通过可采用半蚀刻的结构，能把导电图形的间隔加工地狭窄，能形成更细小的BGA结构的半导体器件用的图形。由于第二焊接垫块、布线和外部取出用电极称为一体，可抑制变形、反向等。而且，封装绝缘树脂来完全固定后，通过研磨、蚀刻板状体的里面等加工，可分离导电图形，即使没有位置偏离，也能把导电图形配置在预定位置上，而且BGA结构的半导体器件必须的布线可进行没有任何变形地配置。
通过在树脂封装区域内整个区域导电图形配置，没有已有的类型的引线框架产生的溢料。
通过形成与引导孔相同的图形，以绝缘树脂封装时，作为导销可被开口。通过前面预先使导销开口，可在封装用金属模的引销上设置板状体，可进行位置精度高的树脂封装。
如果板状体以Cu为主材料构成、导电覆盖膜以Ni,Ag,Au或Pd等构成，可被导电覆盖膜用作蚀刻掩膜，而且半蚀刻时，其侧面成弯曲结构，导电图形的表面上可形成导电覆盖膜构成的遮盖件，可产生具有锚定效果的结构。因此，可防止位于绝缘树脂的里面的导电图形的脱落、反向。
以板状体制造的半导体器件以半导体元件、导电图形和绝缘树脂必要的最小限度来形成，产生不浪费资源的半导体器件。可实现大幅度抑制成本的半导体器件。由于没有采用韧性层等的支持衬底，没有支持衬底的热阻，提高了半导体元件的放热性。通过优化绝缘树脂的覆盖膜厚度、导电箔的厚度，可实现非常小的薄型且轻量化的半导体器件。
由于从绝缘树脂露出导电图形的里面，导电图形的里面直接可供与外部的连接，有不需要象原来的结构的韧性层那样的对通孔等进行加工的优点。
本半导体器件分离沟的表面和导电图形的表面结构为具有实际一致的平坦表面，即使把窄的间距QFP等安装在安装衬底上，由于半导体器件自身在其原来的水平方向上可移动，外部取出用电极的偏离的修正可变得非常容易。
由于导电图形的侧面为弯曲结构，而且可在表面上形成遮盖件。因此，能产生锚定效果，能防止导电图形的反向、穿透。
涂覆绝缘树脂之前以板状体支持整体，导电图形的分离、切割，绝缘树脂构成支持衬底。因此，如已有示例说明的那样，不需要支持衬底，具有成本低廉的优点。

Claims (19)

1．一种板状体，具有平坦面构成的第一表面和与所述第一表面相对设置的由平坦面构成的第二表面，其特征在于：
在所述第二表面上形成第一导电覆盖膜，该第一导电覆盖膜具有与下面所述的实质相同的图形：半导体元件装载区域的周围设置焊接垫块、与这个焊接垫块一体地向所述半导体元件装载区域延伸布线以及与该布线一体设置外部取出用电极。
2．一种板状体，具有平坦面构成的第一表面和与所述第一表面相对设置的由平坦面构成的第二表面，其特征在于：
在所述第二表面上形成光刻胶，该光刻胶具有与下面所述的实质相同的图形：半导体元件装载区域的周围设置焊接垫块、与这个焊接垫块一体地向所述半导体元件装载区域延伸布线以及与该布线一体设置外部取出用电极。
3．根据权利要求2的板状体，其特征在于在对应于所述焊接垫块的区域设置导电覆盖膜，形成所述光刻胶以覆盖该导电覆盖膜。
4．根据权利要求1到3的任意一项的板状体，其特征在于在所述板状体的相对的侧边上形成与导销实质相同的图形，或形成插入所述导销的引导孔。
5．根据权利要求1到3的任意一项的板状体，其特征在于所述板状体以导电箔构成，所述导电覆盖膜由与所述导电箔的材料不同的材料构成。
6．一种板状体，具有平坦面构成的第一表面和具有形成预定高度的凸部的、与所述第一表面相对形成的第二表面，其特征在于所述凸部的构成为：
半导体元件装载区域的周围设置的焊接垫块、与这个焊接垫块一体地向所述半导体元件装载区域延伸的布线以及与该布线一体设置外部取出用电极。
7．根据权利要求6的板状体，其特征在于所述凸部的表面设置导电覆盖膜。
8．根据权利要求7的板状体，其特征在于在至少对应于所述焊接垫块的区域设置导电覆盖膜。
9．根据权利要求6到8的任意一项的板状体，其特征在于所述板状体以导电箔构成，所述导电覆盖膜由与所述导电箔的材料不同的材料构成。
10．根据权利要求6到9的任意一项的板状体，其特征在于在所述板状体的相对的侧边上形成与导销实质相同的图形的凸部，或形成插入所述导销的引导孔。
11．根据权利要求6到10的任意一项的板状体，其特征在于在所述板状体上把所述凸部形成的预定图形配置成矩阵状，可大量生产。
12．根据权利要求6的板状体，其特征在于所述板状体由Cu,Al,Fe-Ni合金，Cu-Al集层体或Al-Cu-Al的集层体构成。
13．根据权利要求6的板状体，其特征在于所述凸部的侧面具有锚定结构。
14．根据权利要求6到9的任意一项的板状体，其特征在于所述导电覆盖膜在所述凸部的上面形成遮盖件。
15．根据权利要求14的板状体，其特征在于通过把所述导电覆盖膜由Ni,Au,Ag或Pd构成。
16．一种板状体，具有在对应于树脂封装区域的整个面上逐渐过渡的平坦里面和形成凸部的表面，该凸部以从所述里面开始的预定厚度形成层状，在由与上面的金属模对接的区域所包围的区域中，由在半导体元件装载区域的周围设置的焊接垫块、与这个焊接垫块一体地向所述半导体元件装载区域延伸的布线以及与该布线一体设置外部取出用电极构成，
至少由与所述上面的金属模对接的区域所包围的区域通过所述表面和所述上面金属模构成封闭空间。
17．一种半导体器件的制造方法，其特征在于具有步骤：准备一种板状体，该板状体具有在对应于树脂封装区域的整个面上逐渐过渡的平坦里面和形成凸部的表面，该凸部以从所述里面开始的预定厚度形成层状，由在与上面的金属模对接的区域所包围的区域中设置的焊接垫块、与这个焊接垫块一体地向所述半导体元件装载区域延伸的布线以及与该布线一体设置外部取出用电极构成；
在所述半导体元件装载区域装载半导体元件的同时，电连接所述焊接垫块和所述半导体元件；
把所述板状体装载到金属模中、把树脂填充到所述板状体和所述上面金属模构成的空间中；
取出在所述填充的树脂的里面上露出的板状体，分别把所述凸部分离开。
18．根据权利要求17的制造半导体器件的方法，其特征在于对应于所述树脂封装区域的所述板状体的里面的全部区域与下面金属模对接。
19．根据权利要求18的制造半导体器件的方法，其特征在于所述下面金属模的对接区域分散配置着抽取真空装置。
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100356822C (zh) * 2004-03-24 2007-12-19 三洋电机株式会社 电路装置及其制造方法
CN100372105C (zh) * 2002-04-11 2008-02-27 Nxp股份有限公司 半导体器件
CN100385641C (zh) * 2003-01-15 2008-04-30 先进互联技术有限公司 具有局部预制图形化引线框架的半导体封装及其制造方法
CN101923910A (zh) * 2010-09-10 2010-12-22 中南大学 一种高温抗蚀导电复合材料
CN104756240A (zh) * 2013-03-26 2015-07-01 松下知识产权经营株式会社 半导体封装的制造方法、半导体芯片支撑载体及芯片安装装置
CN105364972A (zh) * 2014-08-12 2016-03-02 东和株式会社 切割装置、吸附机构及使用其的吸附装置、切割系统
CN106298206A (zh) * 2015-06-25 2017-01-04 威华微机电股份有限公司 被动元件的预形体及其量产方法
CN110077657A (zh) * 2018-01-26 2019-08-02 致伸科技股份有限公司 指纹辨识模块包装方法

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4761662B2 (ja) * 2001-07-17 2011-08-31 三洋電機株式会社 回路装置の製造方法
US7001798B2 (en) * 2001-11-14 2006-02-21 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device
JP2003243435A (ja) 2002-02-14 2003-08-29 Hitachi Ltd 半導体集積回路装置の製造方法
JP2005522868A (ja) * 2002-04-11 2005-07-28 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 電子装置の製造方法
US8236612B2 (en) * 2002-04-29 2012-08-07 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6812552B2 (en) * 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US7799611B2 (en) * 2002-04-29 2010-09-21 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US20040058478A1 (en) * 2002-09-25 2004-03-25 Shafidul Islam Taped lead frames and methods of making and using the same in semiconductor packaging
ATE498908T1 (de) * 2003-06-18 2011-03-15 Nxp Bv Verfahren zur herstellung einer halbleitervorrichtung mit einem leiterrahmen und vorrichtung hierzu
WO2005017968A2 (en) * 2003-08-14 2005-02-24 Advanced Interconnect Technologies Limited Semiconductor device package and method for manufacturing same
JP4488733B2 (ja) * 2003-12-24 2010-06-23 三洋電機株式会社 回路基板の製造方法および混成集積回路装置の製造方法。
US7122406B1 (en) * 2004-01-02 2006-10-17 Gem Services, Inc. Semiconductor device package diepad having features formed by electroplating
TW200530655A (en) * 2004-03-05 2005-09-16 Toppoly Optoelectronics Corp Display panel, lead pad structure, lead pad array structure and method of fabricating the same
US7205178B2 (en) * 2004-03-24 2007-04-17 Freescale Semiconductor, Inc. Land grid array packaged device and method of forming same
JP4353853B2 (ja) * 2004-05-20 2009-10-28 三洋電機株式会社 回路装置の製造方法および板状体
JPWO2005114730A1 (ja) * 2004-05-20 2008-03-27 スパンション エルエルシー 半導体装置の製造方法および半導体装置
TWI245392B (en) * 2004-06-29 2005-12-11 Advanced Semiconductor Eng Leadless semiconductor package and method for manufacturing the same
KR100585150B1 (ko) * 2004-07-01 2006-05-30 삼성전자주식회사 신호 전달 특성을 개선시킨 반도체 장치
US7095096B1 (en) * 2004-08-16 2006-08-22 National Semiconductor Corporation Microarray lead frame
TWI249214B (en) * 2004-11-12 2006-02-11 Advanced Semiconductor Eng Assembly process
EP1659628A1 (en) * 2004-11-23 2006-05-24 Optium Care International Tech. Inc. High lead density electronic device
US7589407B2 (en) * 2005-04-11 2009-09-15 Stats Chippac Ltd. Semiconductor multipackage module including tape substrate land grid array package stacked over ball grid array package
US7846775B1 (en) 2005-05-23 2010-12-07 National Semiconductor Corporation Universal lead frame for micro-array packages
US7245009B2 (en) * 2005-06-29 2007-07-17 Motorola, Inc. Hermetic cavity package
CN101807533B (zh) 2005-06-30 2016-03-09 费查尔德半导体有限公司 半导体管芯封装及其制作方法
CN1945822B (zh) * 2005-10-07 2012-05-23 日立麦克赛尔株式会社 半导体器件、半导体模块及半导体模块的制造方法
JP4707548B2 (ja) * 2005-12-08 2011-06-22 富士通セミコンダクター株式会社 半導体装置、及び半導体装置の製造方法
US20070138240A1 (en) * 2005-12-15 2007-06-21 Aleksandra Djordjevic Method for forming leadframe assemblies
US7598122B1 (en) * 2006-03-08 2009-10-06 National Semiconductor Corporation Die attach method and microarray leadframe structure
KR100744146B1 (ko) 2006-08-08 2007-08-01 삼성전자주식회사 연성 접속판을 이용하여 배선 기판과 칩을 연결하는 반도체패키지
CN101601133B (zh) * 2006-10-27 2011-08-10 宇芯（毛里求斯）控股有限公司 部分图案化的引线框以及在半导体封装中制造和使用其的方法
EP2078191A2 (en) * 2006-11-01 2009-07-15 Sensorcon, Inc. Sensors and methods of making the same
JP4956173B2 (ja) * 2006-12-19 2012-06-20 新光電気工業株式会社 フリップチップ実装用基板
EP2137763A2 (en) 2007-04-10 2009-12-30 Nxp B.V. Package, method of manufacturing a package and frame
US20080265445A1 (en) * 2007-04-30 2008-10-30 International Business Machines Corporation Marks for the Alignment of Wafer-Level Underfilled Silicon Chips and Method to Produce Same
GB0721927D0 (en) * 2007-11-08 2007-12-19 Cambridge Silicon Radio Ltd Chip packaging
US8084299B2 (en) 2008-02-01 2011-12-27 Infineon Technologies Ag Semiconductor device package and method of making a semiconductor device package
US8115285B2 (en) 2008-03-14 2012-02-14 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
TWI414048B (zh) * 2008-11-07 2013-11-01 Advanpack Solutions Pte Ltd 半導體封裝件與其製造方法
US7986048B2 (en) * 2009-02-18 2011-07-26 Stats Chippac Ltd. Package-on-package system with through vias and method of manufacture thereof
EP2248161B1 (en) * 2009-03-06 2019-05-01 Kaixin Inc. Leadless integrated circuit package having high density contacts
US8531022B2 (en) * 2009-03-06 2013-09-10 Atmel Corporation Routable array metal integrated circuit package
US8785253B2 (en) 2009-04-03 2014-07-22 Kaixin, Inc. Leadframe for IC package and method of manufacture
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US20100314728A1 (en) * 2009-06-16 2010-12-16 Tung Lok Li Ic package having an inductor etched into a leadframe thereof
CN102576701B (zh) 2009-09-02 2016-08-17 凯信公司 Ic封装件及其制造方法
JP2013138261A (ja) * 2009-09-29 2013-07-11 Renesas Electronics Corp 半導体装置
JP5271949B2 (ja) 2009-09-29 2013-08-21 ルネサスエレクトロニクス株式会社 半導体装置
TWI469289B (zh) * 2009-12-31 2015-01-11 矽品精密工業股份有限公司 半導體封裝結構及其製法
US8455304B2 (en) 2010-07-30 2013-06-04 Atmel Corporation Routable array metal integrated circuit package fabricated using partial etching process
JP5940257B2 (ja) * 2011-08-01 2016-06-29 株式会社三井ハイテック リードフレーム及びリードフレームの製造方法並びにこれを用いた半導体装置
KR101374145B1 (ko) * 2012-04-19 2014-03-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US20140145320A1 (en) * 2012-11-29 2014-05-29 Cambridge Silicon Radio Limited Die package
US8987922B2 (en) 2013-03-11 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for wafer level packaging
KR101665242B1 (ko) 2015-03-20 2016-10-11 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이의 제조 방법
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
JP6380805B2 (ja) * 2015-04-07 2018-08-29 大口マテリアル株式会社 半導体素子搭載用基板、半導体装置及びそれらの製造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052050A (ja) * 1983-08-31 1985-03-23 Dainippon Printing Co Ltd リ−ドフレ−ムの製造方法
JPS6454749A (en) * 1987-08-26 1989-03-02 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JP2781019B2 (ja) * 1989-09-06 1998-07-30 新光電気工業株式会社 半導体装置およびその製造方法
KR100437437B1 (ko) * 1994-03-18 2004-06-25 히다치 가세고교 가부시끼가이샤 반도체 패키지의 제조법 및 반도체 패키지
JP3400877B2 (ja) 1994-12-14 2003-04-28 三菱電機株式会社 半導体装置及びその製造方法
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
JPH09312355A (ja) * 1996-05-21 1997-12-02 Shinko Electric Ind Co Ltd 半導体装置とその製造方法
JP3538290B2 (ja) * 1997-01-09 2004-06-14 株式会社ルネサステクノロジ 配線部材およびこれを有するリードフレーム
WO1998037742A1 (en) * 1997-02-18 1998-08-27 Koninklijke Philips Electronics N.V. Method of providing a synthetic resin capping layer on a printed circuit
JP3877401B2 (ja) 1997-03-10 2007-02-07 三洋電機株式会社 半導体装置の製造方法
JPH10340925A (ja) 1997-06-09 1998-12-22 Matsushita Electron Corp 半導体装置およびその製造方法
JPH113953A (ja) 1997-06-10 1999-01-06 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
JPH1174411A (ja) * 1997-08-29 1999-03-16 Dainippon Printing Co Ltd 樹脂封止型半導体装置とそれに用いられる回路部材
JP3521758B2 (ja) 1997-10-28 2004-04-19 セイコーエプソン株式会社 半導体装置の製造方法
JPH11163024A (ja) 1997-11-28 1999-06-18 Sumitomo Metal Mining Co Ltd 半導体装置とこれを組み立てるためのリードフレーム、及び半導体装置の製造方法
JPH11251505A (ja) * 1998-03-04 1999-09-17 Matsushita Electron Corp 半導体装置及びその製造方法
JP3445930B2 (ja) * 1998-03-12 2003-09-16 松下電器産業株式会社 樹脂封止型半導体装置
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
JP2000022044A (ja) * 1998-07-02 2000-01-21 Mitsubishi Electric Corp 半導体装置とその製造方法
JP2000099678A (ja) * 1998-09-18 2000-04-07 Hitachi Ltd Ｉｃカード及びその製造方法
JP3503502B2 (ja) * 1998-11-11 2004-03-08 松下電器産業株式会社 樹脂封止型半導体装置およびその製造方法
JP2001068586A (ja) * 1999-08-25 2001-03-16 Fujitsu Ltd 半導体装置
US6247229B1 (en) * 1999-08-25 2001-06-19 Ankor Technology, Inc. Method of forming an integrated circuit device package using a plastic tape as a base
CN1265451C (zh) * 2000-09-06 2006-07-19 三洋电机株式会社 半导体装置及其制造方法
US6890835B1 (en) * 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
US6348726B1 (en) * 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100372105C (zh) * 2002-04-11 2008-02-27 Nxp股份有限公司 半导体器件
CN100385641C (zh) * 2003-01-15 2008-04-30 先进互联技术有限公司 具有局部预制图形化引线框架的半导体封装及其制造方法
CN100356822C (zh) * 2004-03-24 2007-12-19 三洋电机株式会社 电路装置及其制造方法
CN101923910A (zh) * 2010-09-10 2010-12-22 中南大学 一种高温抗蚀导电复合材料
CN101923910B (zh) * 2010-09-10 2012-08-15 中南大学 一种高温抗蚀导电复合材料
CN104756240A (zh) * 2013-03-26 2015-07-01 松下知识产权经营株式会社 半导体封装的制造方法、半导体芯片支撑载体及芯片安装装置
CN105364972A (zh) * 2014-08-12 2016-03-02 东和株式会社 切割装置、吸附机构及使用其的吸附装置、切割系统
CN106298206A (zh) * 2015-06-25 2017-01-04 威华微机电股份有限公司 被动元件的预形体及其量产方法
CN106298206B (zh) * 2015-06-25 2019-01-04 威华微机电股份有限公司 被动元件的预形体及其量产方法
CN110077657A (zh) * 2018-01-26 2019-08-02 致伸科技股份有限公司 指纹辨识模块包装方法
CN110077657B (zh) * 2018-01-26 2021-03-09 致伸科技股份有限公司 指纹辨识模块包装方法

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CN1173400C (zh) 2004-10-27
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US20040214374A1 (en) 2004-10-28
US20010045625A1 (en) 2001-11-29
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US6975022B2 (en) 2005-12-13
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