CN100372105C - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN100372105C CN100372105C CNB038081180A CN03808118A CN100372105C CN 100372105 C CN100372105 C CN 100372105C CN B038081180 A CNB038081180 A CN B038081180A CN 03808118 A CN03808118 A CN 03808118A CN 100372105 C CN100372105 C CN 100372105C
- Authority
- CN
- China
- Prior art keywords
- layer
- carrier
- semiconductor device
- semiconductor element
- bonding conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title description 3
- 239000004020 conductor Substances 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims description 10
- 239000000203 mixture Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 3
- 229910002113 barium titanate Inorganic materials 0.000 claims description 2
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- 239000000843 powder Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 17
- 238000005538 encapsulation Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 74
- 239000010949 copper Substances 0.000 description 15
- 238000005530 etching Methods 0.000 description 14
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000004411 aluminium Substances 0.000 description 9
- 239000006210 lotion Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910019142 PO4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- PANJMBIFGCKWBY-UHFFFAOYSA-N iron tricyanide Chemical compound N#C[Fe](C#N)C#N PANJMBIFGCKWBY-UHFFFAOYSA-N 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0361—Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Metallurgy (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
半导体器件(10)包括载体(30)和半导体元件(20),例如集成电路。载体(30)提供有孔(15),由此定义了具有侧面(3)的连接导体(31-33)。凹口(16)存在于侧面(3)中。半导体元件(20)被包围在包层(40)内,所述包层延伸进载体(30)的凹口(16)内。结果,包层(40)被机械地固定在载体(30)中。在包封步骤之后,半导体器件(10)可以在其中的工序中制造,不需要光刻步骤。
Description
技术领域
本发明涉及一种半导体器件,其包括具有彼此相对定位的第一和第二侧面的载体,所述载体在第一侧面上具有第一层,所述第一层根据所期望的图案进行构图,由此定义了多个互相隔离的连接导体,在所述载体的第一侧面上存在有半导体元件,所述半导体元件提供有通过连接装置与所述载体的连接导体导电性地相连的连接区域,所述半导体元件被包封在延伸到所述载体的钝化包层中,在其第二侧面上,接触面限定在所述连接导体中以便为了放置在衬底上。
本发明也涉及一种制造具有彼此相对定位的第一和第二侧面的载体的方法,所述载体包括,在第一侧面上,根据所期望的图案进行构图的第一导电层,由此定义了多个互相隔离的连接导体,所述载体进一步包括第二和第三层。
本发明进一步涉及制造多个半导体器件的方法,所述每个半导体器件包括具有连接区域的半导体元件,所述方法包括下述步骤:在载体的第一侧面上提供半导体元件,通过连接装置在连接区域和载体的连接导体之间形成导电连接;提供钝化包层;和分离所述半导体器件。
背景技术
这种半导体器件和方法由EP-A1160858公知。所述公知半导体器件的载体通过从第一侧面向下蚀刻到一半至所述载体而制造。最终得到的连接导体延伸,使其一部分被所述半导体元件所覆盖,而另一部分没有被覆盖。未被覆盖的部分提供有附加的导电膜,能接合要被连接的线。这些接合线是所述半导体元件与连接导体之间的连接装置。如现有技术文献的图4C中所示,为了定义接触表面,提供了掩模,之后所述载体被蚀刻到一定深度。所述公知的载体包括三层相同的材料,例如铜,铝或镍铁合金,但可选择地包括铝,铜和铝作为所述层。
所述公知的半导体器件的缺点在于包层对于所述载体的附着不充分。
发明内容
因此,本发明的第一个目的是提供一种在开头段落中所提到类型的半导体器件,其具有在载体和包层之间改善的附着。
实现第一个目的是将半导体器件的包层机械地固定在连接导体中,为了该目的,所述连接导体提供有具有凹口的侧面。
在依照本发明的半导体器件中获得的所述机械固定在包层和载体之间提供良好的附着。另外,该机械固定很容易获得,例如,因为除第一层以外,所述载体还包括第二层和第三层,所述第二层包含了能以蚀刻剂被蚀刻的材料,其基本上完整地留下第一和第三层。
对于连接装置,可以使用接合线构成;如果使用接合线,则通过粘合剂将所述半导体元件粘附到所述载体。可选择地,可以使用由各向异性导电粘合剂、凸块或焊料构成。这些连接装置与接合线相比具有优点,即不需要或需要很少装配操作。尤其,凸块是合适的,因为由例如金或金合金构成的凸块可以非常精确地放置,不会导致所述半导体元件连接区域的污染。
所述载体的第一和第三层有利的实施方案中包含Cu,而第二层包含铝或镍铁合金。可选择地,第一和第三层可以包含镍铁合金,第二层可以包含铜。考虑到如果第一和第三层由铝构成是不合适的;铝具有下述缺点,即导致线接合和电镀铝生产率不太令人满意。三层载体比两层载体具有另外的优点,即排除了作为加热步骤结果的载体的热变形。
在另一个实施方案中,所述载体包括电绝缘层,通过从载体第一侧面到第二侧面的通孔实现导电连接。如果可以在这些层中嵌入无源元件,则这种多层衬底的实施方案是尤其有利的。合适的电绝缘层的例子尤其是环氧树脂和氧化硅。
所述半导体元件优选为集成电路,但可选择地为分立的半导体。另外也可以是一个或更多个其它元件和所述半导体元件一起存在于衬底上。这些其它的元件可以是有源和无源元件。
本发明的第二个目的是提供制造载体和多个在开头段落中提到类型的半导体器件,通过所述方法,获得了具有改善的附着的半导体器件。
第二个目的的实现在于,所述第二层在蚀刻剂中被蚀刻,其基本上完整地留下第一和第三层,所述蚀刻导致了所述第一层底蚀(underetching),造成了在连接导体中凹口的形成。
第三个目的的实现在于,使用了利用依照本发明所述的方法而获得的载体,提供钝化包层,使得所述包层延伸进入限定在载体中的凹口。
使用所述方法以简单的方式获得了依照本发明的半导体器件。依照本发明的方法有利的方面是,不必在所述半导体元件被包覆后执行光刻步骤。可以以各种方式实现该优点。
在第一实施方案中,在所述第一层内的图案通过穿孔来定义,由此,形成从所述载体第一侧面延伸到第二侧面的孔。所述连接导体通过导线的方式与载体内的框架保持连接。依靠定义的所述孔,就无需所述载体第三层的图形化。所述第二层可以以湿法化学工艺被有利地蚀刻,其中所述载体被浸入在含有蚀刻剂的浴液(bath)中。当所述载体随后被用于制造所述半导体器件时,所述载体被放置在衬底上,此时提供了包封。在分离的工艺中,所述连接导体与框架之间的导线被切穿。
该实施方案对于工业规模的制造具有几个重要的优点。第一,可以以与由单层铜构成的标准载体相同的方式处理该载体。同时,由此而获得的半导体器件更加优良,因为所述器件更薄,且不具有用于粘附至衬底的横向凸出的导线。第二,含有用于第二层的蚀刻剂的浴液可以添加到一个或多个已经用于载体制造的浴液中,在这种情况下,第二层例如为铝或镍铁合金。这些浴液通过电镀用于在载体的第一侧面上提供NiPd(Au)层。这就具有了接合线可以极好地粘附到其上的优点。然而也可以以不同的方式提供这种粘合层。
依照该实施方案的所述载体优选具有在0.05和0.2mm之间的厚度,优选包括铜的第一和第三层及铝或镍铁合金的第二层;第一、第二和第三层的层厚度是相同的数量级。
载体的所述层,尤其是第二层可以包含任何添加物或杂质,如AC、SI和/或Cu。
为了制造具有依照本发明载体的半导体器件,导线被用作连接装置,因为已经发现当前可利用的技术不允许所述载体与凸块或各向异性导电粘合剂结合。此外,在凸块或各向异性导电粘合剂的情况中,在载体中定义有一个或多个表面,通过粘合剂可以将半导体元件粘附到所述表面上。该表面或这些表面还用作散热片。
在第二实施方案中,载体在第二侧面上提供有蚀刻掩模,所述蚀刻掩模可以抵抗热处理。在提供所述半导体器件和包封之前,通过蚀刻从第一侧面将所述第一层和第二层构图。所述第三层保持不动,以致所述载体不会碎裂。在所述半导体元件已经被放置并包封后,通过蚀刻掩模将第三层或至少其表面进行构图。如此,在第三层的表面处定义了导电接触表面。
附图说明
将参照附图更加详细地解释依照本发明的半导体器件及制造所述载体和半导体器件的方法的这些和其它方面,其中:
图1是所述半导体器件第一实施方案的概略横截面图;
图2是所述半导体器件第二实施方案的概略横截面图;
图3是第二实施方案的概略平面图;
图4是所述半导体器件第三实施方案的概略横截面图;和
图5-9示出了在制造所述载体和半导体器件的方法中的步骤。
具体实施方式
这些图并没有按规定比例画出。相同的参考标记指相同的部分。可选择的实施方案可落在所附权利要求的保护范围内。
图1是半导体器件10的概略横截面图。所述半导体器件10包括存在于载体30上的半导体元件20。所述载体30具有第一侧面1和第二侧面2,并包括多个连接导体31,32,33。具有侧面3的所述连接导体31,32,33通过孔15互相隔离。在连接导体31,32,33与半导体元件20内的连接区域21之间具有连接装置,这里是接合线22。在该例子中,半导体元件20通过粘合层23被粘附到载体30的第一侧面1上。通过包层40包封半导体元件20和接合线22。所述包层40延伸进入载体30的孔15内。
依照本发明,凹口16存在于连接导体31,32,33的侧面3中。这些凹口16被包层40填充,作为其结果,第一层31被包层40部分地夹住。这保证了包层40被机械地固定在载体30中,从而产生极好的附着和机械强度。在这种情况下,不必在载体的第一侧面1上提供改善附着的装置。可以对第一侧面1进行优化以便半导体元件20和接合线22的放置。
在该实施方案中,载体30由第一层11,第二层12和第三层13构成。第一层11和第三层13主要包括铜,第二层12主要包括铝。第二层12中的凹口16通过蚀刻形成,如将参照图5-9所解释的。载体30进一步包括在第一侧面1上的NiPdAU或NiPd的顶层14。希望该顶层14与接合线22有良好的附着。本领域熟练技术人员可以理解到,顶层14也可以包括不同的合适材料。将第三层13进行构图,以通过开口15形成接触面,所述开口延伸到载体30的第二侧面。连接导体32与地相连,用作散热片。
图2是半导体器件10的第二实施方案的概略横截面图。图3是所述第二实施方案的概略平面图,其中线A-A表示图2的横截面。所述半导体器件包括具有第一层11,第二层12,第三层13和顶层14的载体30。从第一侧面将载体30进行构图,在该处理中形成孔15和连接导体31-35。其通过依次蚀刻第一层11和第二层12来获得,由此形成了连接导体31-35的侧面3中的凹口16。随后,具有连接区域21的半导体元件20通过连接装置22,这里是Au凸块,与连接导体31-35相连。为了该目的,使用芯片倒装技术。为了提供良好的接触,在Cu的第一层11上提供Sn的顶层14。随后提供包层40。这就产生了机械固定,因为包层40延伸进载体的凹口16中。随后通过已经存在的蚀刻掩模将第三层13进行构图,尤其是环氧树脂材料,其也以叠层使用。接下来移除蚀刻掩模,作为其结果,孔15从载体30的第一侧面1延伸到第二侧面2。孔15随后也用于分离半导体器件30。其具有另外的优点,即所述机械固定充分地将连接导体31-35包封。半导体器件10的尺寸,例如大约为1×1mm。开口16具有例如40-100μm的宽度。第一,第二和第三层11-13的厚度分别选择为30μm,40μm和30μm。
图4是所述半导体器件10第三实施方案的概略横截面图。第三实施方案大致对应于第二实施方案。这两个实施方案之间的区别在于在第三实施方案中,所述载体30包括无源部件172。为了该目的,载体30除了每个都包含导电材料的第一,第二和第三层11,12,13之外,还包括电绝缘材料的第四层17和导电材料的第五层18。第四层包括根据所希望图案的部分171,所述部分包含具有高介电常数的电介质材料,例如以钛酸钡为基础,具有本领域熟练技术人员公知的特定组分的材料。该材料例如以粉末的形式存在于第四层17中,第四层17还包含,例如,环氧树脂材料。在这种情况下,无源部件172是电容器,但所述部件可选择地是电阻器或线圈。依照所述概略图,无源部件172在接触表面18与半导体元件20之间串行地排列。然而,这不是必须的。代替这里示出的基于叠层或陶瓷材料的载体30,载体30可选择地例如是在硅衬底上的无源网络。
图5-9示出了在依照本发明的方法中的各种步骤,这可以实现图1中所示的半导体器件10的第一实施方案。图5,6和7涉及制造载体30的方法。图8和9涉及制造半导体器件10的方法。这里示出的方法具有下述优点,即在提供包层之后,不需要光刻步骤就可以执行所述方法,同时对包层40的附着极好,在包封步骤之前载体30不会碎裂。
图5显示了第一步骤之后的载体30,其中Cu的第一层11,Al的第二层12和Cu的第三层13彼此粘合。可以使用第二层12作为起始层,在其每个侧面上提供Cu层。可选择地,载体30可以通过把层11,12,13碾压(rolling)在一起来形成,所述技术通常用于形成双层。也可以在两个步骤中执行所述处理。最终形成四层或多层也是可能的。第一,第二和第三层11,12,13在第一个实验中具有70μm的厚度。然而所述厚度可以在1μm和1.0mm之间变化,优选在10μm到50μm之间,第一,第二和第三层11-13的厚度不必相同。如果第一层11相当薄,则优选用作该层的材料具有大的机械强度和硬度,例如镍铁合金。与之相组合,铜可以用作第二层12。
为了改善Cu和Al层彼此之间的附着,在所述层的层压之后可以进行加热步骤。这种加热步骤导致Cu原子扩散进AL中,于是产生了AL-Cu合金的子层。
图6显示了通过穿孔手段提供了从载体30的第一侧面1延伸到第二侧面2的孔15之后的载体30。作为该穿孔操作的结果,定义了具有侧面3的连接导体31-33。所述连接导体借助导线以通常的方式与载体中的框架相连,所述导线没有示出。
图7显示了在多个浴液中处理之后的载体30;首先将载体30在包含浓缩的KOH溶液的浴液中处理3分钟。在所述处理中,蚀刻Al的第二层12,由此形成凹口16。该蚀刻溶液的浓度例如是0.1到2摩尔每升。优选地,可溶的铁氰化物是一部分蚀刻溶液,浓度在sf/e直到饱和的范围内。更优选的,存在由三价或五价的氧化磷衍生的磷助剂的可溶性盐。这种添加物可以用于设置期望量的底切(undercutting)。
在所述三分钟之后,所述凹口具有70μm的宽度。然而,10μm-20μm的宽度就足够获得期望的机械固定。另外,这样的宽度有下述优点,即所述连接导体可以小型化;对于具有大约100μm宽度的连接导体,其中在两个侧面3处提供凹口16,所述凹口的宽度最多可以是大约30μm。随后,在浴液中处理载体30,其中NiPd的顶层14被涂布到载体的第一侧面1上。可以调整所述蚀刻剂的浓度和蚀刻浴液的温度。尤其通过载体30移动穿过用于涂布NiPd顶层14的浴液的速度来决定这些条件。
图8显示了在通过粘合剂23将半导体元件20粘附到所述载体,且在半导体元件20的连接区域21与连接导体31-33之间提供接合线22之后的载体30。
图9显示了在以通常的方式提供包层40之后的载体30,其临时放置在衬底70上。
Claims (7)
1.一种半导体器件,包括具有彼此相对定位的第一和第二侧面的载体,所述载体在第一侧面上具有第一层,所述载体还包括第二层和第三层,所述第二层包括在蚀刻剂中能被蚀刻的材料,所述蚀刻剂保留所述第一和第三层,根据所期望的图案对所述第一、第二和第三层进行构图,由此定义了多个互相隔离的连接导体,
在载体的所述第一侧面上存在有半导体元件,所述半导体元件提供有连接区域,所述连接区域通过连接装置与所述载体的连接导体导电性地相连,所述半导体元件被包封在一个钝化包层中,所述钝化包层延伸得与所述载体一样远,所述钝化包层被机械地固定在所述连接导体中,为了该目的,所述连接导体提供有具有凹口的侧面;
其特征在于所述载体还包括电绝缘材料的第四层和导电材料的第五层,至少一个无源部件被嵌入所述载体中,在所述第二侧面上,接触表面限定在所述导电材料的第五层中以便置于衬底上。
2.如权利要求1所述的半导体器件,其特征在于所述第一层、第二层、第三层中每个层含有导电材料。
3.如权利要求1所述的半导体器件,其特征在于所述无源部件是电容。
4.如权利要求3所述的半导体器件,其特征在于所述电绝缘材料包括具有高介电常数的电介质材料。
5.如权利要求4所述的半导体器件,其特征在于所述电介质材料以粉末形式出现。
6.如权利要求4或5所述的半导体器件,其特征在于所述电介质材料是以钛酸钡为基础的材料。
7.如权利要求1所述的半导体器件,其特征在于从所述载体的第一侧面到第二侧面的导电连接由通孔形成。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02076426.2 | 2002-04-11 | ||
EP02076426 | 2002-04-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1647271A CN1647271A (zh) | 2005-07-27 |
CN100372105C true CN100372105C (zh) | 2008-02-27 |
Family
ID=28685949
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB038081180A Expired - Lifetime CN100372105C (zh) | 2002-04-11 | 2003-04-08 | 半导体器件 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7176582B2 (zh) |
EP (1) | EP1500136A1 (zh) |
JP (1) | JP2005522863A (zh) |
KR (1) | KR100989007B1 (zh) |
CN (1) | CN100372105C (zh) |
AU (1) | AU2003214579A1 (zh) |
WO (1) | WO2003085731A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108702847A (zh) * | 2016-02-18 | 2018-10-23 | 三井金属矿业株式会社 | 印刷电路板制造用铜箔、带载体的铜箔和覆铜层叠板、以及使用它们的印刷电路板的制造方法 |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6826827B1 (en) | 1994-12-29 | 2004-12-07 | Tessera, Inc. | Forming conductive posts by selective removal of conductive material |
US6909178B2 (en) * | 2000-09-06 | 2005-06-21 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP2007508708A (ja) * | 2003-10-15 | 2007-04-05 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 電子装置およびその製造方法 |
US7453157B2 (en) * | 2004-06-25 | 2008-11-18 | Tessera, Inc. | Microelectronic packages and methods therefor |
TW200721426A (en) | 2005-07-25 | 2007-06-01 | Koninkl Philips Electronics Nv | Air cavity package for flip-chip |
WO2007036911A2 (en) | 2005-09-30 | 2007-04-05 | Nxp B.V. | Fine-pitch routing in a lead frame based system-in-package (sip) device |
EP1946369B1 (en) * | 2005-11-01 | 2011-07-20 | Nxp B.V. | Method of packaging semiconductor dies |
EP1946364A1 (en) * | 2005-11-01 | 2008-07-23 | Koninklijke Philips Electronics N.V. | Methods of packaging a semiconductor die and package formed by the methods |
TW200737479A (en) * | 2005-11-03 | 2007-10-01 | Koninkl Philips Electronics Nv | Surface treatments for contact pads used in semiconductor chip packages and methods of providing such surface treatments |
DE102008024704A1 (de) | 2008-04-17 | 2009-10-29 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauteil und Verfahren zur Herstellung eines optoelektronischen Bauteils |
MY163911A (en) * | 2009-03-06 | 2017-11-15 | Shenzhen Standarad Patent & Trademark Agent Ltd | Leadless integrated circuit package having high density contacts |
CN102395981B (zh) | 2009-04-03 | 2014-12-03 | 凯信公司 | Ic封装的引线框架和制造方法 |
US20100314728A1 (en) * | 2009-06-16 | 2010-12-16 | Tung Lok Li | Ic package having an inductor etched into a leadframe thereof |
KR101668141B1 (ko) | 2009-09-02 | 2016-10-20 | 카이씬, 인코포레이티드 | Ic 패키지 및 이의 제조방법 |
EP2337068A1 (en) | 2009-12-18 | 2011-06-22 | Nxp B.V. | Pre-soldered leadless package |
JP5710128B2 (ja) * | 2010-01-19 | 2015-04-30 | 大日本印刷株式会社 | 樹脂付リードフレームの製造方法 |
US9263315B2 (en) | 2010-03-30 | 2016-02-16 | Dai Nippon Printing Co., Ltd. | LED leadframe or LED substrate, semiconductor device, and method for manufacturing LED leadframe or LED substrate |
DE102010044987A1 (de) * | 2010-09-10 | 2012-03-15 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauelement und Verfahren zu dessen Herstellung |
US8933548B2 (en) | 2010-11-02 | 2015-01-13 | Dai Nippon Printing Co., Ltd. | Lead frame for mounting LED elements, lead frame with resin, method for manufacturing semiconductor devices, and lead frame for mounting semiconductor elements |
US9137903B2 (en) | 2010-12-21 | 2015-09-15 | Tessera, Inc. | Semiconductor chip assembly and method for making same |
DE102012201177A1 (de) * | 2012-01-27 | 2013-08-01 | Robert Bosch Gmbh | Kunststoffummantelter Bauelementeträger mit Leiterplatten-Vias |
JP6115836B2 (ja) * | 2015-03-10 | 2017-04-19 | 大日本印刷株式会社 | 樹脂付リードフレーム、リードフレーム、半導体装置および樹脂付リードフレームの製造方法 |
US9595455B1 (en) | 2016-06-09 | 2017-03-14 | Nxp B.V. | Integrated circuit module with filled contact gaps |
US11031350B2 (en) | 2017-12-26 | 2021-06-08 | Stmicroelectronics, Inc. | Leadframe with pad anchoring members and method of forming the same |
US10573583B2 (en) * | 2018-06-20 | 2020-02-25 | Texas Instruments Incorporated | Semiconductor device package with grooved substrate |
KR102260622B1 (ko) * | 2019-10-28 | 2021-06-08 | 주식회사 코스텍시스 | 고방열 큐에프엔 패키지 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1325136A (zh) * | 2000-05-24 | 2001-12-05 | 三洋电机株式会社 | 板状体和半导体器件的制造方法 |
US20010049156A1 (en) * | 2000-01-28 | 2001-12-06 | Advanced Semiconducto Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59208756A (ja) * | 1983-05-12 | 1984-11-27 | Sony Corp | 半導体装置のパツケ−ジの製造方法 |
JPH04328853A (ja) * | 1991-04-30 | 1992-11-17 | Mitsubishi Electric Corp | リードフレーム材料およびリードフレーム |
US5362538A (en) * | 1992-10-21 | 1994-11-08 | Toray Industries, Inc. | Optical recording medium |
US5340771A (en) * | 1993-03-18 | 1994-08-23 | Lsi Logic Corporation | Techniques for providing high I/O count connections to semiconductor dies |
US5656550A (en) * | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
EP0805614B1 (en) * | 1995-11-17 | 2005-04-13 | Kabushiki Kaisha Toshiba | Multilayered wiring board, prefabricated material for multilayered wiring board, process of manufacturing multilayered wiring board, electronic parts package, and method for forming conductive pillar |
JP3171093B2 (ja) * | 1996-01-31 | 2001-05-28 | ソニー株式会社 | リードフレームの製造方法と半導体装置の製造方法 |
JPH1084074A (ja) * | 1996-09-09 | 1998-03-31 | Mitsubishi Electric Corp | 半導体パッケージ |
JP3780122B2 (ja) | 1999-07-07 | 2006-05-31 | 株式会社三井ハイテック | 半導体装置の製造方法 |
US6451627B1 (en) * | 1999-09-07 | 2002-09-17 | Motorola, Inc. | Semiconductor device and process for manufacturing and packaging a semiconductor device |
US6333252B1 (en) * | 2000-01-05 | 2001-12-25 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
US6306685B1 (en) * | 2000-02-01 | 2001-10-23 | Advanced Semiconductor Engineering, Inc. | Method of molding a bump chip carrier and structure made thereby |
US6238952B1 (en) * | 2000-02-29 | 2001-05-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
EP1143509A3 (en) | 2000-03-08 | 2004-04-07 | Sanyo Electric Co., Ltd. | Method of manufacturing the circuit device and circuit device |
SG99939A1 (en) * | 2000-08-11 | 2003-11-27 | Casio Computer Co Ltd | Semiconductor device |
JP3945968B2 (ja) | 2000-09-06 | 2007-07-18 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
-
2003
- 2003-04-08 AU AU2003214579A patent/AU2003214579A1/en not_active Abandoned
- 2003-04-08 EP EP03710159A patent/EP1500136A1/en not_active Withdrawn
- 2003-04-08 KR KR1020047016108A patent/KR100989007B1/ko not_active IP Right Cessation
- 2003-04-08 JP JP2003582815A patent/JP2005522863A/ja active Pending
- 2003-04-08 US US10/510,591 patent/US7176582B2/en not_active Expired - Fee Related
- 2003-04-08 CN CNB038081180A patent/CN100372105C/zh not_active Expired - Lifetime
- 2003-04-08 WO PCT/IB2003/001421 patent/WO2003085731A1/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010049156A1 (en) * | 2000-01-28 | 2001-12-06 | Advanced Semiconducto Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
CN1325136A (zh) * | 2000-05-24 | 2001-12-05 | 三洋电机株式会社 | 板状体和半导体器件的制造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108702847A (zh) * | 2016-02-18 | 2018-10-23 | 三井金属矿业株式会社 | 印刷电路板制造用铜箔、带载体的铜箔和覆铜层叠板、以及使用它们的印刷电路板的制造方法 |
CN108702847B (zh) * | 2016-02-18 | 2021-03-09 | 三井金属矿业株式会社 | 印刷电路板制造用铜箔、带载体的铜箔和覆铜层叠板、以及使用它们的印刷电路板的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20050167794A1 (en) | 2005-08-04 |
KR20040101423A (ko) | 2004-12-02 |
WO2003085731A1 (en) | 2003-10-16 |
EP1500136A1 (en) | 2005-01-26 |
CN1647271A (zh) | 2005-07-27 |
US7176582B2 (en) | 2007-02-13 |
JP2005522863A (ja) | 2005-07-28 |
AU2003214579A1 (en) | 2003-10-20 |
KR100989007B1 (ko) | 2010-10-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100372105C (zh) | 半导体器件 | |
US6818470B1 (en) | Process for producing a thermoelectric converter | |
CN102194717B (zh) | 半导体器件和在半导体管芯周围形成绝缘层的方法 | |
TWI608586B (zh) | 形成不連續的esd保護層於半導體晶粒之間之半導體裝置及方法 | |
KR100728856B1 (ko) | 회로 장치 및 그 제조 방법 | |
US9595453B2 (en) | Chip package method and package assembly | |
TWI397972B (zh) | Semiconductor device manufacturing method | |
US8642389B2 (en) | Method of manufacturing a semiconductor device | |
CN103681607A (zh) | 半导体器件及其制作方法 | |
TW201036104A (en) | Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme | |
WO1996002071A1 (en) | Packaged integrated circuit | |
CN102217063A (zh) | 用于功率器件的晶片级别芯片级封装的半导体管芯结构、使用其的封装及系统、以及其制造方法 | |
CN101416308A (zh) | 使用薄的管芯和金属衬底的半导体管芯封装 | |
KR20170077146A (ko) | 기판 구조들 및 제조 방법들 | |
KR20000057792A (ko) | 반도체 집적 회로의 제조 방법 | |
TWI256715B (en) | Semiconductor device and its manufacturing method | |
KR20080055762A (ko) | 반도체 장치 및 그 제조 방법 | |
US8777638B2 (en) | Wiring board and method of manufacturing the same | |
US9165792B2 (en) | Integrated circuit, a chip package and a method for manufacturing an integrated circuit | |
JP3459234B2 (ja) | 半導体装置およびその製造方法 | |
US7397126B2 (en) | Semiconductor device | |
CN203351587U (zh) | 半导体器件 | |
US20230238294A1 (en) | Semiconductor package including a chip-substrate composite semiconductor device | |
EP1003209A1 (en) | Process for manufacturing semiconductor device | |
JP2569789B2 (ja) | 半導体チップの電極形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20150915 Address after: Delaware Patentee after: III Holdings 6 LLC Address before: Holland Ian Deho Finn Patentee before: NXP B.V. |
|
CX01 | Expiry of patent term |
Granted publication date: 20080227 |
|
CX01 | Expiry of patent term |