KR20000057792A - 반도체 집적 회로의 제조 방법 - Google Patents

반도체 집적 회로의 제조 방법 Download PDF

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Publication number
KR20000057792A
KR20000057792A KR1020000003060A KR20000003060A KR20000057792A KR 20000057792 A KR20000057792 A KR 20000057792A KR 1020000003060 A KR1020000003060 A KR 1020000003060A KR 20000003060 A KR20000003060 A KR 20000003060A KR 20000057792 A KR20000057792 A KR 20000057792A
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layer
forming
copper
aluminum
barrier layer
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KR1020000003060A
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English (en)
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KR100659801B1 (ko
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취티페디사이레쉬
머췐트사이레쉬만신
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루센트 테크놀러지스 인크
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Abstract

본 명세서는 반도체 집적 회로의 구리 배선에 금 도선을 접착하는 기법에 대해서 설명한다. 구리 상부에 장벽층이 형성되고, 그 장벽층의 상부에 알루미늄 접착 패드가 형성된다. 그리고 나서 금 도선은 알루미늄 패드에 열 압착 접착된다.

Description

반도체 집적 회로의 제조 방법{WIRE BONDING TO COPPER}
본 발명은 집적 회로의 제조 방법에 관한 것으로서, 특히, 금 상호 연결 도선을 구리 배선에 접착하기 위한 방법에 관한 것이다.
반도체 제조의 발전에서, 영구적인 기술중 하나는 와이어 본딩(wire bonding)이다. 와이어 본딩은 최초의 IC 칩을 리드 프레임(lead frame)과 상호 연결하여 단일 IC 패키지를 만드는 데 사용되었다. 칩 기술의 개선에 따라서, 다중칩 모듈과 같이 고집적도를 갖는 복합 패키지가 요구되고, 이들 모듈간의 상호 연결 및 이들 모듈과 지원 보드의 상호 연결이 필요하다. TAB 본딩 및 융기(bump) 본딩은 이들 패키지에 대한 효과적인 상호 연결 기술로서 발전했고, 현재 IC 제조에 와이어 본딩 응용이 남아있지만, 와이어 본딩은 여전히 원가 경쟁 기술이다.
IC 상호 연결 기술의 개발에 있어서, 구리는 IC 상호 연결용으로 바람직한 재료라고 인식됐었다. 구리는 전도성이 높고 가격이 저렴하며, 그 야금술이 잘 발달되어 있다. 그러나, 초기에는 구리를 상호 연결 재료로서 사용한 적이 거의 없었다. 구리는 전리가 활발하고 반도체에서 마이그레이션(migration) 문제를 야기한다. 와이어 본딩된 패키지에서, 구리 배선은 금 도선 접착제와 쉽게 합금화되지 않고, Cu-Au 합금은 튼튼하지 못하다. 구리에 대해서 알려진 문제 때문에, 알루미늄이나 하급 전도체가 IC 배선용 재료로 선택된다. 알루미늄 금속 배선의 용인은 종래에 남아있던 다른 취사선택 공정과 마찬가지로 확립되었다.
이미 IC 기술은, 알루미늄의 전도성이 IC 설계를 제한하는 문제점을 개선했다. 이로써 설계자들은 알루미늄을 배선 형성재료로 다시 고려하게 됐다. 다시 사용될만한 유망한 재료는 구리다. 그러나, 구리 야금술을 현재 IC 공정에 도입하려면 종래 문제의 보다 새로운 변형이 필요하다. 이들 중 하나는 금 도선을 구리 배선으로 와이어 본딩하는 것이다.
본 출원인은 금을 구리 배선으로 와이어 본딩하는 공정을 개선했다. 이 개선된 공정에서는 구리 위에 장벽층을 형성하는 공정과 그 장벽층 위에 알루미늄 패드를 형성하는 공정이 수반된다. 그 다음, 금 배선은 열압착으로 알루미늄 패드에 접착된다.
도 1 내지 24는 본 발명에 따른 공정을 구현하는 데 유용한 단계의 개략도이다
도 1을 참조하면, 보다 큰 실리콘 웨이퍼의 일부분을 부분적으로 잘라낸 부분적으로 잘라서 표시한 실리콘 기판(11)이 도시되어 있다. 본 명세서에서 설명하기 편하게, 이들 도면을 실척으로 도시하지 않고 몇몇 특징부 에 대해서는 과장되게 도시한 점에 대해서 유의해야 할 것이다. 실리콘 기판은 전형적으로 필드 산화물인 제 1 산화층(12), 금속 상호 연결 배선층(13) 및 전형적으로 증착된 산화물이나 다른 적절한 유전 재료인 층간 유전층(14)으로 덮인다. 또한, 크세로겔(xerogel)이나 에어로겔(aerogel) 과 같이 저 유전 상수를 갖는 재료도 적합하고, 스핀 온(spin-on) 기법을 사용해서 형성될 수 있다. 이들 원소는 실리콘 IC 기술에서 표준이기 때문에 본 발명의 요소로 되지는 아니다. 기본 구조를 기점으로서 사용해서 본 발명에 대해서 설명하겠지만, 당업자라면 전형적인 집적회로가 서너개의 메탈 층을 구비할 것이라는 사실을 알 것이다. 금속층(13)은 최종 금속층과 인접하게 형성되어야 하고, 일반적으로 다른 층들이 있지만 도시 생략되어 있다.
도 2를 참조하면, 포토리소그래피 마스크(16)를 유전체층(14)에 형성한 다음, 패턴화 해서 층간 상호 연결 배선이 형성될 층간 유전체의 일부를 노출시킨다. 본 설명에서는 포토리소그래피나 포토마스크를 언급하였지만, 엑스레이(x-ray)나 이빔(e-beam)과 같은 다른 리쏘그래피 처리가 대용될 수도 있다. 식각 마스크로서 포토레지스트를 사용하면, 도 3에 도시된 바와 같이 층간 상호 연결용 창(18)이 층간 유전체를 통해서 금속 러너(metal runner)까지 형성된다. 그 다음, 유전체 위와 창 내로 적절한 창 매립 재료를 증착해서 층간 창(18)을 매립한다. 예를 들면, 도 4에서 층(21)과 층(22)으로 표시된 TiN 및 텅스텐의 이중 층이 사용될 수 있다. 그리고 나서, 웨이퍼를 화학 기계적 연마(CMP : chemical mechanical polishing)로 처리하여, 도 5에 도시된 구조체를 생성한다. TiN/W 층의 CMP 기법은 1998년 9월 10일에 출원된 미국 특허 출원 제 09/151,077 호에 개시되어 있다. 이 단계에서, 창은 금속 플러그(23)로 매립되고, 그 구조체는 다음 금속 배선층을 형성하기 위해서 대기한다. 도 5의 CMP 단계에 의해서 원하지 않는 금속을 제거하면 보다 전통적인 마스크 및 식각 처리를 사용해서 원하지 않는 금속을 제거하는 것보다 평탄한 구조체를 생성할 수 있음을 알 수 있을 것이다. 이러한 과정이 몇차례 반복되어 여러 층의 금속층을 형성하는 경우에 특히 더하다. 그러나, 본 발명의 목적에 관해서는, 층간 상호 연결 배선을 형성하기 위한 임의의 적합한 처리가 사용될 수 있다.
그 다음, 도 6을 참조하면, 도시된 바와 같이 층간 유전체 및 층간 창 위의 전면에 식각 정지층(25)을 형성한다. 식각 정지층은 RIE 식각 방법과 같은 전형적인 산화물 식각 처리에 대한 내식성이 강한 실리콘 질화물로 형성되어, 층간 플러그를 보호하는 것이 바람직하다. 식각 정지층의 두께는 전형적으로 500∼1500Å이다.
도 7을 참조하면, 그 구조체 위로 유전체 층(31)을 형성하고, 도 8에 도시된 바와 같은 리쏘그래피 마스크(32)로 마스킹한다. 개구(33)가 형성되도록 마스크를 패턴화하여, 텅스텐 플러그(23) 위로 개구를 형성한다. 도 9에 표시된 바와 같이, 노출된 산화물은 식각―RIE를 사용하는 것이 바람직하다―으로 제거되고, 창(33)의 실리콘 질화물 식각 정지층이 제거되어 도 10의 구조체가 이루어진다.
도 11을 참조하면, 도 11에 도시된 바와 같이 창 내부를 포함한 구조체 위의 전면에 장벽층(41)이 형성된다. 이 층은 집적 회로의 최종(또는 표면) 금속층인 구리 상호 연결 배선을 한정하는 본 명세서에서 설명하는 과정중 제 1 단계이고, 도선 접착이 형성될 층이다. 또한, 다른 구리 금속 배선층이 그 구조체에 존재하지만, 본 발명에서는 도선 접착에 의해서 상호 연결될 최종 금속층에 포함시킨다. 장벽층을 형성하기 위한 재료로는 다른 재료가 사용될 수도 있지만, Ta, TaN, Ti 또는 TiN이 사용되는 것이 바람직하다. 장벽층은 화학적 기상 증착법(CVD : chemical vapor deposition)이나 물리적 기상 증착법(PVD : physical vapor deposition)에 의해서 증착될 수 있다. 장벽층의 두께는 100∼1000Å이 적합하다.
그 다음, 도 12를 참조하면, PVD에 의해서 구리 주조 층(42)이 전면에 형성된다. 구리 주조층의 두께는 단지 전면 전해 증착용 표면 위에 시드층(seed layer)을 제공하기에 충분한 정도(예를 들어, 1000∼2000Å)면 될 것이다. 표준 기법에 의해서 구리 시드층(42)은 구리층(43)을 전해 증착할 수 있다. 구리층(43)의 두께는 도 13에 도시된 바와 같이 도 12에 도시된 개구(33)를 완전히 매립하기에 충분해야 하고, 개구 높이의 1.2∼1.6 배의 두께가 바람직하다. 그 다음 표면을 상술한 방식의 CMP를 사용해서 평탄화해서 도 14에 도시된 바와 같이 장벽층(45)에 의해서 측면과 하부가 둘러싸인 구리 플러그(44)를 구비하는 구조체를 생성한다.
구리 플러그(44)의 표면을 피복하기 위해서, 도 15에 도시된 바와같은 구조체 위의 전면에 제 2 장벽층이 형성된다. 이 장벽층은 본질적으로 장벽층(41)과 동일하고 구리 금속 배선층의 모든 측면을 밀봉해서 집적 회로의 구리 이동을 방지하도록 보장한다.
그 다음 도 16∼20에 도시된 바와 같이 도선 접착이 구리 금속 배선층으로 접촉된다. 도 16을 참조하면, 얇은 장벽층(51)은 두꺼운 알루미늄층(52)으로 덮인다. 알루미늄층(52)은 CVD나 PVD로 증착될 것이고, 0.1∼1.0㎛ 범위 내의 두께를 갖는 것이 바람직할 것이다.
그 다음, 리쏘그래피 마스크(53)가 식각층(51, 52)에 형성되어 도 17에 도시된 바와 같이 알루미늄 접착 패드를 한정하고, 이들 층의 원하지 않는 부분을 전형적인 식각 기법으로 제거하여 도 18에 도시된 바와 같이 장벽층(55)에 의해서 구리 플러그로부터 분리된 접착 패드(56)를 생성한다. 일반적으로, 이 층의 상부에는 다수의 접착 패드(56)가 있을 것이다. 그 다음, 도 19를 참조하면, 통상적인 불활성화층(58)이 형성되어 집적 회로를 피복한다. 피복층은 Si3N4 이나 폴리이미드(polyimide)와 같은 중합체(polymer)일 것이다. 피복층은 감광성 폴리이미드인 것이 바람직할 것이다. 그 다음, 피복층(58)은 패터닝되어( 감광성인 경우에는 마스킹 및 식각되어) 도 19에 도시된 바와 같이 알루미늄 접착 패드(56)의 표면을 노출시킨다. 실리콘 질화물을 패턴화하는 데 표준 포토레지스트 및 식각 기법이 사용될 수 있다. 층(58)이 감광성 폴리머인 경우, 포토레지스트가 생략될 수 있고, 그 층 자신이 노광 및 현상에 의해서 패턴화된다.
도 20을 참조하면, 열압착(TC: thermocompression) 접착에 의해서 도선(61)이 알루미늄 패드(56)로 접착된다. 도선은 금이나 경화용 Au-Be와 같은 적은양의 금속이 추가된 금 합금 등으로 형성하는 것이 바람직하다. 도선의 직경은 일반적으로 0.5∼2[mil]이지만, 1∼1.2[mil]인 것이 바람직하다. 알루미늄 패드의 면적은 일반적으로 1000∼40000[㎛2]이지만, 5000∼25000[㎛2]인 것이 바람직하다. 열압착 작업이 무난하다. 힘은 15∼60[g]이지만, 40∼60[g]이 바람직하다. 초음파 주파수는 40∼200[kHz] 범위내에 있지만 60∼120[kHz]의 범위내에 있는 것이 바람직하고, 전력은 20∼200[mW]의 범위내에 있지만, 50∼100[mW]의 범위 내에 있는 것이 바람직하다. 이들 매개 변수는 K&S 도선 접착기를 포함하는 다양한 접착 수단에 적합하다.
상술한 본 방법의 최종 몇 단계에 대한 다른 실시예가 도 21∼24에 도시되어 있다. 도 14의 구조체에서 시작하면, 피복층(72)이 알루미늄 접착 패드층보다 먼저 형성된다. 도 21에서, 창(71)은 피복층(72)에 도시되어 있다. 창(71)은 구리 금속 배선(44)을 노출시킨다. 도 22에 도시된 바와 같이, 장벽층(73)은 창 내부를 포함한 피복층(72) 위의 전면에 증착되어 구리 금속 배선층과 접촉된다. 도 22에 도시된 바와 같이, 알루미늄층(74)이 마스크(76)로 차폐되고 나서, 층(74, 73)은 식각되어 도 23의 알루미늄 접착 패드(77)를 형성한다. 도 24를 참조하면, 마스크가 제거되고 나서, 금 열접착 도선 접착(78)이 형성되어 상호 연결 배선을 완성한다.
상술한 본 발명의 실시예에 있어서, 최종 금속 패턴이 구리이고, 상술한 바와 같은 장벽층은 구리를 절연하고 하부의 별도 야금 영역으로의 이동(migration)을 방지하기 위한 것이다. 그러나, 하부에 있는 층들도 구리 금속 배선으로 이루어져 있는 경우, 최종층은 금속 배선 층들 간에 도시되어 있는 장벽층을 구비할 필요가 없다. 임의의 경우에 있어서, 최종 구리 접착 영역과 알루미늄 도선 접착 패드 사이에 효과적인 장벽층이 존재하는 것은 여전히 중요하다.
상술한 과정은 실리콘 CMOS 집적 회로용으로 개선된 것이지만 Ⅲ-Ⅴ족 광학 집적 회로와 같이 다른 종류의 반도체 집적 회로에도 동일하게 적용할 수 있다. 일반적으로 이들 집적 회로는 GaAs나 InP 기판과 능동 소자를 형성하는 Ⅲ-Ⅴ족 3원 및/또는 4원 복수층들을 구비한다. 그러나, 상호 연결 배선은 실리콘 IC 기술에서 사용되는 것들과 유사한 소정 응용에서 사용될 수 있다. 또한, 이들 회로는 일반적으로 구리 이동이 명백하게 커지는 초고속으로 동작한다.
오늘날 대부분의 실리콘 집적 회로는 트랜지스터 소자용 폴리실리콘 게이트를 구비해서 제조되고, 제 1 층 금속은 일반적으로 폴리실리콘으로 되어 게이트 및 그들 게이트들에 대한 상호 연결 배선을 형성한다. 제 1 층 다음에 형성되는 금속 상호 연결 배선층은 대개 알루미늄이고, 일반적으로 1 내지 3개의 알루미늄층이 된다. 이들 중에서 하나 이상의 알루미늄층이 상술한 설명에 따른 구리로 대체될 것이다. 적어도 구리층들 중의 하나는, 본 발명에 따라 알루미늄 접착 면적으로 개조되는 도선 접착을 갖는다. 제 1 금속 배선층 및 제 2 금속 배선층의 참조는 집적 회로 구조체에서 반드시 제 1 및 제 2 층으로 되는 것은 아니라고 이해되어야 한다.
당업자라면 본 발명을 다양하게 추가 변형할 수 있을 것이다. 본 분야를 개선하는 본 발명의 원리 및 그와 동등한 원리에 근본적으로 의존하는 본 명세서의 상세한 설명으로부터의 모든 일탈은, 상세한 설명 및 특허청구범위와 같은 본 발명의 사상 범주 내에서 고려되는 것이 바람직하다.
본 발명에 따르면, 구리를 배선 형성 재료로 사용할 수 있다.

Claims (11)

  1. 표면 상호 연결 배선층이 구리로 이루어진 반도체 집적 회로의 제조 방법에 있어서,
    (가)상기 표면 상호 연결 배선층의 선택된 일부분의 상부에 Ta, TaN, Ti, TiN 및 그들의 조합중 어느 하나의 재료로 이루어지는 장벽층을 형성하는 단계와,
    (나) 상기 장벽층의 상부에 알루미늄층을 형성하는 단계와,
    (다)상기 도선 상호 연결 배선을 상기 알루미늄층에 접착하는 단계를 포함하는 반도체 집적 회로의 제조 방법.
  2. 제 1 항에 있어서,
    상기 반도체 집적 회로의 반도체는 실리콘인 반도체 집적 회로의 제조 방법.
  3. 제 2 항에 있어서,
    상기 도선은 금으로 이루어지고 열 압착 접착 기법을 사용해서 접착되는 반도체 집적 회로의 제조 방법.
  4. 제 1 항에 있어서,
    상기 반도체 집적 회로의 제조 방법은,
    상기 (가) 단계 이전에, 상기 표면 상호 연결 배선층의 상부에 피복층을 형성하는 단계와, 상기 피복층에 창을 형성하는 단계를 더 포함하여, 상기 (가) 내지 (다) 단계와 함께 처리되는 반도체 집적 회로의 제조 방법.
  5. 제 1 항에 있어서,
    상기 반도체 집적 회로의 제조 방법은,
    (다)단계 전에 상기 표면 상호 연결 배선층의 상부에 피복층을 형성하는 단계와, 상기 피복층에 창을 형성하여 상기 알루미늄층의 일부분을 노출시키는 단계를 더 포함하여 상기 (다 )단계와 함께 처리되는 반도체 집적 회로의 제조 방법.
  6. 반도체 집적 회로의 제조 방법에 있어서,
    (가)반도체 기판의 상부에 구리 상호 연결 배선층을 형성하는 단계와,
    (나)상기 구리 상호 연결 배선층의 상부에 유전체층을 형성하는 단계와,
    (다)상기 유전체층의 다수개의 개구를 형성해서 상기 구리 상호 연결 배선층의 일부분을 노출된 상태로 남기는 단계와,
    (라)상기 구리 상호 연결 배선층의 상기 노출된 부분의 상부 및 상기 유전체 층의 상부에 장벽층을 형성하는 단계와,
    (마)상기 장벽층의 상부에 알루미늄층을 형성하고, 상기 장벽층 및 상기 알루미늄층의 선택된 일부분을 식각으로 제거하여 상기 제 2 도전성 상호 연결 배선층의 상기 노출된 부분의 상부에 장벽층 패드와 알루미늄층 패드를 남기는 단계와,
    (바)열 압착에 의해서 도선을 상기 알루미늄 패드로 접착하는 단계를 포함하는 반도체 집적 회로의 제조 방법.
  7. 제 6 항에 있어서,
    상기 장벽층은,
    Ta, TaN, Ti, TiN 및 그들의 조합중 어느 하나의 재료로 이루어지는 반도체 집적 회로의 제조 방법.
  8. 반도체 장치의 제조 방법에 있어서,
    (가) 반도체 기판의 상부에 제 1 상호 연결 배선 형상을 갖는 제 1 도전성 상호 연결 배선층을 형성하는 단계와,
    (나)상기 제 1 도전성 상호 연결 배선 층의 상부에 제 1 유전체층을 형성하는 단계와,
    (다)상기 제 1 유전체층에 적어도 하나의 층간 개구를 형성해서 상기 제 1 상호 연결 배선의 일부분을 노출시키는 단계와,
    (라)상기 층간 개구의 내부를 포함한 상기 제 1 유전체층의 상부에 제 1 장벽층을 형성하는 단계와,
    (마)상기 제 1 장벽층의 상부에 상기 층간 개구를 충분히 충진할 수 있는 정도의 두께를 갖는 구리 층을 도금하는 단계와,
    (바)상기 제 1 장벽층 및 상기 구리층의 일부분을 제거해서 상기 장벽층과 상기 층간 개구를 충진하는 구리 플러그를 남기는 단계와,
    (사)상기 제 1 유전체 층의 상부 및 사이 플러그의 상부에 장벽층을 형성하고, 상기 장벽층의 상부에 알루미늄을 형성하는 단계와,
    (아)상기 장벽층 및 상기 알루미늄층중의 선택된 일부분을 식각으로 제거해서 상기 구리 플러그의 상부에 장벽층 패드 및 알루미늄층 패드를 남기는 단계와,
    (자)도선을 상기 알루미늄 패드로 열압착 접착하는 단계를 포함하는 반도체 집적 회로의 제조 방법.
  9. 제 8 항에 있어서,
    상기 장벽층은,
    Ta, TaN, Ti, TiN 및 그들의 조합중 어느 하나의 재료로 이루어지는 반도체 집적 회로의 제조 방법.
  10. 반도체 집적 회로의 제조 방법에 있어서,
    (가)반도체 기판의 상부에 구리 상호 연결 배선층을 형성하는 단계와,
    (나)상기 구리 상호 연결 배선층의 선택된 일부분의 상부에 장벽층을 형성하는 단계와,
    (다)상기 장벽층의 상부에 알루미늄층을 형성하는 단계와,
    (라)상기 반도체 기판 위에 절연 피복층을 형성하는 단계와,
    (마)상기 절연 피복층의 선택된 일부분을 제거하여 상기 알루미늄층의 일부분을 노출시키는 단계와,
    (바)도선을 상기 알루미늄 패드로 열압착 접착하는 단계를 포함하는 반도체 집적 회로의 제조 방법.
  11. 제 10 항에 있어서,
    상기 장벽층은,
    Ta, TaN, Ti, TiN 및 그들의 조합중 어느 하나의 재료로 이루어지는 반도체 집적 회로의 제조 방법.
KR1020000003060A 1999-01-23 2000-01-22 반도체 집적 회로 제조 방법 KR100659801B1 (ko)

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