JP2000216191A - 半導体集積回路の製造方法 - Google Patents

半導体集積回路の製造方法

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Publication number
JP2000216191A
JP2000216191A JP7951A JP2000007951A JP2000216191A JP 2000216191 A JP2000216191 A JP 2000216191A JP 7951 A JP7951 A JP 7951A JP 2000007951 A JP2000007951 A JP 2000007951A JP 2000216191 A JP2000216191 A JP 2000216191A
Authority
JP
Japan
Prior art keywords
layer
copper
aluminum
barrier layer
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7951A
Other languages
English (en)
Other versions
JP3575676B2 (ja
Inventor
Sailesh Chittipeddi
チッジペッジ サイレッシュ
Sailesh M Merchant
マンシン マーチャント サイレッシュ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22889365&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP2000216191(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of JP2000216191A publication Critical patent/JP2000216191A/ja
Application granted granted Critical
Publication of JP3575676B2 publication Critical patent/JP3575676B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

(57)【要約】 【課題】 金製のワイヤを銅製の金属化層にボンディン
グする方法を提供すること。 【解決手段】 本発明の方法は、銅の金属化層４４の上
にバリア層５５を形成し、このバリア層５５の上にアル
ミ製パッド５６を形成する。金製のワイヤ６１をその後
このアルミ製パッド５６の上に熱圧縮接合をする。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、集積回路の製造方
法に関し、特に金製のワイヤ相互接続物を銅製の金属化
層に接合する方法に関する。
【０００２】
【従来の技術】半導体の製造技術の進展に伴い、依然と
して問題となっている技術はワイヤボンディングであ
る。ワイヤボンディングを用いてＩＣチップをリードフ
レームに接続してＩＣパッケージを製造している。チッ
プ技術が開発されるにつれて、より高次のチップ集積を
具備する複雑なパッケージ例えばマルチチップモジュー
ルが必要とされ、そしてこれらのモジュールを互いに接
続して基板をサポートする技術が必要とされている。
【０００３】ＴＡＢボンディングとバンプボンディング
はこれらのパッケージを相互接続する技術として十分開
発しつくされているが、ワイヤボンディングは依然とし
てコスト競争力がある技術でありワイヤボンディングの
アプリケーションは現在のＩＣマニュファクチャにおい
て生き残るものである。
【０００４】ＩＣ相互接続技術の開発にともない銅はＩ
Ｃ相互接続の有力な候補として早くから認識されてい
た。銅は高電導性で安価で銅の冶金的特徴は十分に開発
しつくされている。しかし銅を相互接続材料として用い
る昔の経験は十分なものではない 銅は電気的に非常に
活性な材料であり、これにより半導体中にマイグレイシ
ョン（移動）の問題を引き起こす。ワイヤボンディング
されたパッケージにおいては銅の金属化を用いることが
できない。その理由は銅は金製のワイヤボンドと合金を
造りやすく、そしてＣｕ−Ａｕ合金は頑強なものではな
いからである。銅ではこのような問題があるためにアル
ミおよび、より性能の劣化した導体がＩＣ金属化の材料
となっている。アルミの金属化がその地位をかためるつ
れて他のオプションは取り残されてしまっている。
【０００５】ＩＣ技術はアルミの導電率がＩＣ設計の限
界的要素となるような点まで現在進んでいる。これによ
りＩＣの相互接続の設計者は金属化材料を再び選択する
ような事態に陥っている（アルミでは限界にきてい
る）。将来そこで有望な材料として再び脚光を浴びたも
のが銅である。しかし銅および銅合金を現在のＩＣプロ
セスに組み込むには古くて新しい問題を引き起こす。こ
れらの問題のひとつは金製のワイヤを銅製の金属化層に
ワイヤ接合することである。
【０００６】
【発明が解決しようとする課題】本発明の目的は金製の
ワイヤを銅製の金属化層にボンディングする方法を提供
することである。
【０００７】
【課題を解決するための手段】本発明の方法は、銅の上
にバリア層を形成し、このバリア層の上にアルミ製パッ
ドを形成する。金製のワイヤをその後このアルミ製のパ
ッドの上に熱圧縮接合をする。
【０００８】
【発明の実施の形態】図１において、シリコン基板１１
は大きなシリコン製ウエハーの一部切りかけ断面図であ
る。このシリコン基板１１はフィールド酸化物と称する
第一酸化物層１２と金属製相互接続レベル１３と堆積酸
化物であるレベル間誘電体層１４あるいは他の適宜の誘
電体材料製のレベル間誘電体層１４により覆われてい
る。
【０００９】誘電率εの低い有機材料たとえば xeroge
l、aerogel等はスピオン技術を用いて塗布するのに適し
た材料である。これらの要素はシリコン製ＩＣ技術の標
準的なものであり、本発明の重要な部分を構成するもの
ではない。これらの構造体を用いて本発明のスタート点
を説明するが当業者は通常の集積回路は３個あるいは４
個の金属レベルを有することは理解するであろう。金属
製相互接続レベル１３は他のレベルが通常存在しない場
合でも次の金属レベルあるいは最後の金属レベルとして
見ることもできる。
【００１０】図２において光リソグラフマスク１６をレ
ベル間誘電体層１４の上に形成し、パターン化してレベ
ル間誘電体の一部を露出する。その一部等はレベル間相
互接続が行われる部分である。本明細書において光リソ
グラフあるいは光マスク等を例に説明しているが、他の
リソグラフプロセス例えばＸ線リソグラフ、電子ビーム
リソグラフ等も用いることができる。フォトレジストを
エッチングマスクとして用いてウィンドウ１８をレベル
間誘電体層を貫通して形成し、金属製ランナー１５への
レベル間相互接続を形成する。
【００１１】次にレベル間のウィンドウ１８を誘電体層
の上とウィンドウ１８内に適宜のウインドウプラグ材料
を堆積することにより充填する。例えばＴｉＮ層２１，
Ｗ層２２のような二重の層を用いることができる（図
４）。その後ウエハーを化学機械研磨（chemical mecha
nical polishing：ＣＭＰ）で処理して図５に示す構造
体を生成する。ＴｉＮ／Ｗ層のＣＭＰ技術は米国特許出
願第０９／１５１，０７７（出願日；０９／１０／９
８）に記載されている。このウィンドウ１８は金属製プ
ラグ２３で現在充填されておりこの構造体は次の金属化
層を堆積する準備ができている。前述したように図５の
ＣＭＰステップにより不要な金属を除去すると従来のマ
スクとエッチングプロセスを用いて生成されるよりもよ
り平坦な構造体が得られる。とくにこのシーケンスを複
数回繰り返すことにより複数の金属レベルを形成する場
合にはそうである。しかし、本発明ではレベル間相互接
続を形成する適宜のプロセスを用いることができる。
【００１２】図６においてエッチング停止層２５をレベ
ル間誘電体層とレベル間ウィンドウの上にブランケット
堆積をして形成する。この適宜のエッチング停止層２５
は窒化シリコン製で通常の酸化物エッチングプロセス、
例えばＲＩＥエッチング方法に対し耐性を有し形成する
さいにレベル間プラグを保護する。このエッチング停止
層２５の厚さは通常５００〜１５００Åである。
【００１３】図７において誘電体層３１をこの構造体の
上に堆積し図８に示すようにリソグラフマスク３２でマ
スクする。リソグラフマスク３２をパターン化して金属
製プラグ２３の上に開口３３を形成する。図９に示すよ
うに露出した酸化物をエッチングで除去し、好ましくは
ＲＩＥを用いて除去し、開口３３内の窒化シリコン製の
エッチストップ層を除去して図１０の構造体を形成す
る。
【００１４】図１１を参照するとバリア層４１は構造体
の表面とウィンドウ内にブランケット堆積をする。この
層は銅製の相互接続層を規定する第１ステップで、ここ
に示した順においてはＩＣ内の最後のあるいは上部の金
属製の層でそこにワイヤボンディングが行われる層であ
る。他の銅製の金属化レベルもこの構造体の中に示され
ているが本発明は相互接続がワイヤボンディングを用い
て行われる最後の金属製レベルに関連している。このバ
リア層４１の好ましい材料は、Ｔａ，ＴａＮ，Ｔｉ，Ｔ
ｉＮであるが他の材料も用いることができる。バリア層
４１はＣＶＤまたはＰＶＤにより堆積することができ
る。１００〜１０００Å厚さの層が最適である。
【００１５】図１２を参照すると銅シード層４２がその
後ＰＶＤによりブランケット堆積される。この銅シード
層４２の厚さはブランケット電解堆積により表面上のシ
ード層を提供するのに十分な厚さで例えば１０００〜２
０００Åである。この銅シード層４２により銅製層４３
は標準技術により電解堆積が可能となる。銅製層４３の
厚さは図１３に示すように開口３３を完全に充填する程
度であり好ましくは開口３３の深さの１．２〜１．６倍
が好ましい。次にこの表面を前述の方法によりＣＭＰを
用いて平坦化して図１４に示すような構造体を得、そし
て銅製プラグ４４がバリア層４５により側面と底部で包
囲されている。
【００１６】銅製プラグ４４の上部をカプセル化するた
めに第２バリア層５１が図１５の構造体の上にブランケ
ット堆積される。この第２バリア層５１はバリア層４１
と同様な構成を有し、これにより銅製の金属化層の全て
の側がシールされてＩＣ内の銅のマイグレーションを阻
止する。
【００１７】ワイヤボンド接続がその後この銅製の金属
化層に行われる（図１６〜２０）。図１６において薄い
第２バリア層５１が厚いアルミ製層５２でカバーされ
る。このアルミ製層５２はＣＶＤまたはＰＶＤにより堆
積されその厚さは０．２〜１．０μｍの範囲である。
【００１８】図１７に示すようにアルミ製ボンディング
パッドを形成するために第２バリア層５１，アルミ製層
５２をエッチングするためにリソグラフマスク５３をそ
の後形成し、そしてこれらの層の不要な部分を従来の技
術でもってエッチングして除去してバリア層５５による
銅製のプラグから分離されたボンディングパッド５６を
生成する。通常このレベルの上に多くのボンディングパ
ッド５６が形成されある。図１９におて従来の不動態層
５８をその後形成してＩＣのキャップを形成する。
【００１９】キャッピング層はＳｉ3Ｎ4（ＳＩＮＣＡＰ
Ｓ）あるいはポリイミドのようなポリマー材料製であ
る。このキャップ層は光で規定可能なポリイミド製であ
る。不動態層５８を光で規定可能な場合にはその後パタ
ーン化してあるいはマスクしてエッチングしてウィンド
ウ５９を形成し、ボンディングパッド５６の表面を露出
させる。（図１９）標準のフォトレジストとエッチング
技術を用いて窒化シリコンをパターン化する。不動態層
５８が光で規定可能なポリマー製の場合にはフォトレジ
ストを省き、層そのものを露出と現像によりパターン化
できる。
【００２０】図２０においてワイヤ６１をボンディング
パッド５６に熱圧縮（thermocompression：ＴＣ）ボン
ディングにより接合する。このワイヤ６１は金あるいは
硬度を上げるために少量の添加物を含有する金合金、例
えばＡｕ−Ｂｅである。ワイヤの直径は０．５〜２ミル
（ ０．０１２７ｍｍ〜０．５０８ｍｍ ）で好ましくは
１〜１．２ミル（ ０．０２５４ｍｍ〜０．０３０４８
ｍｍ ）である。アルミ製ボンディングパッドの表面積
は１０００〜４００００μｍ2 で好ましくは５０００〜
２５０００μｍ2 である。このＴＣボンディングの操作
は標準的なものである。力は１５〜６０g 好ましくは４
０〜６０ｇである。かけられる超音波周波数は４０〜２
００ｋＨｚ好ましくは６０〜１２０ｋＨｚで、パワーは
２０〜２００ｍＷ好ましくは５０〜１００ｍＷである。
これらのパラメーターはK&S Wire bonderを含む様々な
ボンディングツールに適したものである。
【００２１】上記に記載した最後の数ステップの別のア
プローチを図２１〜２４に示す。図１４の構造体から始
まってキャップ層７２がアルミボンディングパッド層の
前に形成される。図２１においてウィンドウ７１はキャ
ップ層７２内に示されている。ウィンドウ７１はバリア
層４４を露出させる。バリア層７３とアルミ製層７４は
キャップ層７２の上にブランケット堆積され（図２
２）、さらにウィンド内にもブランケット堆積されて銅
製の金属化層に接触する。その後アルミ製層７４をマス
ク７６でマスクして（図２２）、アルミ製層７４とその
後バリア層７３をエッチングして、図２３に示すように
アルミ製ボンディングパッド７７を形成する。図２４に
おいてこのマスクを除去して金製ＴＣワイヤボンド７８
を形成して相互接続を完了させる。
【００２２】上記した本発明の一実施例においては最後
の金属パターンは銅であり、バリア層は銅を隔離して異
なる金属材料の領域内にマイグレーションがおこるのを
阻止している。しかし下に形成されたレベルが銅製の金
属化層を含む場合には図に示した最後のレベルは金属化
レベル間にバリア層を有する必要はない。有効なバリア
層が最後の銅製ボンディング領域とアルミ製ワイヤボン
ディングパッドとの間に存在する場合にはそれは依然と
して重要である。
【００２３】本明細書に記載したプロセスはシリコン製
のＣＭＯＳ集積回路用に開発されたものであるが、例え
ばＩＩＩ−Ｖの光集積回路等の他の種類の半導体集積回
路にも等しく適用できるものである。これらの集積回路
はＧａＡｓ又はＩｎＰの基板を有し、基板と活性デバイ
スを形成するＩＩＩ−Ｖの三層および／又は四層の複数
のレベル等を含む。しかし相互接続はある種のアプリケ
ーションにおいてはシリコンＩＣ技術を用いる相互接続
に類似すものである。これらの回路はまた銅の金属化が
あきらかに有利なような超高速で通常動作する。
【００２４】現在製造されている多くのシリコン製集積
回路はトランジスタデバイス用にポリシリコンゲートを
有し、そして第１レベルの金属は通常ポリシリコンであ
りこれでゲートを形成し、またこれらのゲート間の相互
接続を形成する。第１レベルのあとに形成される金属製
の相互接続レベルは通常アルミ製であり、１ないし３の
アルミ製レベルが一般的である。本発明によれば、これ
らのアルミ製レベルのひとつ、あるいは複数のものは銅
で置換することができる。少なくとも一つの銅製のレベ
ルはワイヤボンディングサイトを有し、そこは本発明に
よりアルミ製のボンディングサイトに替えることができ
る。第１金属化レベルあるいは第２金属化レベルは第１
あるいは第２レベルとして示されものであり、必ずしも
ＩＣ構造の第１レベルまたは第２レベルを表ものではな
い。
【図面の簡単な説明】
【図１】本発明の第１実施例の方法を実行する第１ステ
ップを表す図。
【図２】本発明の第１実施例の方法を実行する第２ステ
ップを表す図。
【図３】本発明の第１実施例の方法を実行する第３ステ
ップを表す図。
【図４】本発明の第１実施例の方法を実行する第４ステ
ップを表す図。
【図５】本発明の第１実施例の方法を実行する第５ステ
ップを表す図。
【図６】本発明の第１実施例の方法を実行する第６ステ
ップを表す図。
【図７】本発明の第１実施例の方法を実行する第７ステ
ップを表す図。
【図８】本発明の第１実施例の方法を実行する第８ステ
ップを表す図。
【図９】本発明の第１実施例の方法を実行する第９ステ
ップを表す図。
【図１０】本発明の第１実施例の方法を実行する第１０
ステップを表す図。
【図１１】本発明の第１実施例の方法を実行する第１１
ステップを表す図。
【図１２】本発明の第１実施例の方法を実行する第１２
ステップを表す図。
【図１３】本発明の第１実施例の方法を実行する第１３
ステップを表す図。
【図１４】本発明の第１実施例の方法を実行する第１４
ステップを表す図。
【図１５】本発明の第１実施例の方法を実行する第１５
ステップを表す図。
【図１６】本発明の第１実施例の方法を実行する第１６
ステップを表す図。
【図１７】本発明の第１実施例の方法を実行する第１７
ステップを表す図。
【図１８】本発明の第１実施例の方法を実行する第１８
ステップを表す図。
【図１９】本発明の第１実施例の方法を実行する第１９
ステップを表す図。
【図２０】本発明の第１実施例の方法を実行する第２０
ステップを表す図。
【図２１】本発明の方法を実行する他の第２実施例、第
１ステップを表す図。
【図２２】本発明の方法を実行する他の第２実施例、第
２ステップを表す図。
【図２３】本発明の方法を実行する他の第２実施例、第
３ステップを表す図。
【図２４】本発明の方法を実行する他の第２実施例、第
４ステップを表す図。
【符号の説明】
１１ シリコン基板 １２ 第一酸化物層 １３ 金属製相互接続レベル １４ レベル間誘電体層 １５ 金属製ランナー １６ 光リソグラフマスク １８ ウィンドウ ２１ ＴｉＮ層 ２２ タングステン層 ２３ 金属製プラグ ２５ エッチング停止層 ３１ 誘電体層 ３２ リソグラフマスク ３３ 開口 ４１，４５ バリア層 ４２ 銅シード層 ４３ 銅製層 ４４ 銅製プラグ ５１ 第２バリア層 ５２ アルミ製層 ５３ リソグラフマスク ５５ バリア層 ５６ ボンディングパッド ５８ 不動態層 ５９，７１ ウィンドウ ６１ ワイヤ ７２ キャップ層 ７３ バリア層 ７４ アルミ製層 ７６ マスク ７７ アルミ製ボンディングパッド ７８ 金製ＴＣワイヤボンド
───────────────────────────────────────────────────── フロントページの続き (71)出願人 596077259 600 Ｍｏｕｎｔａｉｎ Ａｖｅｎｕｅ, Ｍｕｒｒａｙ Ｈｉｌｌ， Ｎｅｗ Ｊｅ ｒｓｅｙ 07974−0636Ｕ．Ｓ．Ａ. (72)発明者 サイレッシュ マンシン マーチャント アメリカ合衆国、32835 フロリダ、オー ランド、バインランド オークス ブール バード 8214

Claims (11)

    【特許請求の範囲】
  1. 【請求項１】 上部の相互接続レベルが銅を含む半導体
    集積回路の製造方法において （ａ）上部の相互接続レベルの選択された領域上にバリ
    ア層（４５）を堆積するステップと前記バリア層の材料
    は、Ｔａ，ＴａＮ，Ｔｉ，ＴｉＮからなるグループから
    選択された材料またはその組み合わせであり （ｂ）前記バリア層の上にアルミ製層（５６）を堆積す
    るステップと （ｃ）前記アルミ製層に導電性ワイヤ（６１）を接合す
    るステップとからなることを特徴とする半導体集積回路
    の製造方法。
  2. 【請求項２】 前記半導体集積回路の半導体は、シリコ
    ンであることを特徴とする請求項１記載の方法。
  3. 【請求項３】 前記ワイヤは、金を含有し熱圧縮接合に
    より接合されることを特徴とする請求項２記載の方法。
  4. 【請求項４】 前記（ａ）のステップの前に （ｄ）前記上部相互接続レベル上にキャップ層を堆積
    し、前記キャップ層内にウィンドウを形成するステップ
    を有することを特徴とする請求項１記載の方法。
  5. 【請求項５】 前記（ｃ）のステップの前に （ｅ）前記上部相互接続レベル上にキャップ層を堆積
    し、前記キャップ層内にウィンドウを形成して前記アル
    ミ製層の一部を露出させるステップを有することを特徴
    とする請求項１記載の方法。
  6. 【請求項６】 （ａ）半導体基板上に銅製の相互接続層
    を形成するステップと （ｂ）前記銅製の相互接続層の上に誘電体層を堆積する
    ステップと （ｃ）前記銅製の相互接続層の一部を露出させる為に、
    前記誘電体層に複数の開口を形成するステップと （ｄ）前記誘電体層の上と前記銅製の相互接続層の露出
    部分にバリア層を堆積するステップと （ｅ）前記バリア層の上にアルミ製層を堆積するステッ
    プと （ｆ）前記バリア層のパッドとアルミ製層のパッドを第
    ２導電性相互接続層の露出部分の上に形成するために、
    前記バリア層と前記アルミ製層の一部をエッチングで除
    去するステップと （ｇ）導電性ワイヤを前記アルミ製パッドに熱圧縮接合
    するステップとを有することを特徴とする半導体集積回
    路の製造方法。
  7. 【請求項７】 前記バリア層の材料は、Ｔａ，ＴａＮ，
    Ｔｉ，ＴｉＮからなるグループから選択された材料およ
    びその組み合わされた材料であることを特徴とする請求
    項６記載の方法。
  8. 【請求項８】 （ａ）半導体基板上に第１導電性相互接
    続層を形成するステップと前記第１導電性相互接続層は
    第１相互接続パターンを有し （ｂ）前記第１導電性相互接続層の上に第１誘電体層を
    堆積するステップと （ｃ）前記第１導電性相互接続層の一部を露出させるた
    めに前記第１誘電体層に少なくとも一つのレベル間開口
    を形成するステップと （ｄ）前記第１誘電体層上と前記レベル間開口内に第１
    バリア層を堆積するステップと （ｅ）前記第１バリア層上に銅製層を電気メッキするス
    テップと前記銅製層はレベル間開口を充填するのに十分
    な厚さを有し （ｆ）バリア層と銅製プラグが前記レベル間開口を充填
    するように前記第１バリア層と前記銅製層の一部を除去
    するステップと （ｇ）前記第１誘電体層と前記銅製プラグ上にバリア層
    を堆積するステップと （ｈ）前記バリア層の上にアルミ製層を堆積するステッ
    プと （ｉ）バリア層とバリア層パッドとアルミ製層パッドを
    前記銅製プラグ上に残すように前記バリア層と前記アル
    ミ製層の一部をエッチングで除去するステップと （ｊ）導電性ワイヤを前記アルミ製パッドに熱圧縮接合
    するステップとを有することを特徴とする半導体集積回
    路の製造方法。
  9. 【請求項９】 上部の相互接続レベルの選択された領域
    上にバリア層を堆積するステップであり前記バリア層の
    材料は、Ｔａ，ＴａＮ，Ｔｉ，ＴｉＮからなるグループ
    から選択された材料およびその組み合わせであることを
    特徴とする請求項８記載の方法。
  10. 【請求項１０】 （ａ）半導体基板上に銅製相互接続層
    を形成するステップと （ｂ）前記銅製相互接続層の一部の上にバリア層を形成
    するステップと （ｃ）前記バリア層の上にアルミ製層を形成するステッ
    プと （ｄ）前記半導体基板の上に絶縁性キャップ層を堆積す
    るステップと （ｅ）前記アルミ製層の一部を露出させるために前記絶
    縁性キャップ層の一部を除去するステップと （ｆ）導電性ワイヤを前記アルミ製パッドに熱圧縮接合
    するステップとからなることを特徴とする半導体集積回
    路の製造方法。
  11. 【請求項１１】 前記バリア層の材料は、Ｔａ，Ｔａ
    Ｎ，Ｔｉ，ＴｉＮからなるグループから選択された材料
    およびその組み合わせであることを特徴とする請求項１
    ０記載の方法。
JP2000007951A 1999-01-23 2000-01-17 半導体集積回路の製造方法 Expired - Lifetime JP3575676B2 (ja)

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US20010036716A1 (en) 2001-11-01
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