TW426980B - Wire bonding to copper - Google Patents

Wire bonding to copper Download PDF

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Publication number
TW426980B
TW426980B TW088120537A TW88120537A TW426980B TW 426980 B TW426980 B TW 426980B TW 088120537 A TW088120537 A TW 088120537A TW 88120537 A TW88120537 A TW 88120537A TW 426980 B TW426980 B TW 426980B
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TW
Taiwan
Prior art keywords
layer
copper
barrier layer
aluminum
depositing
Prior art date
Application number
TW088120537A
Other languages
English (en)
Inventor
Sailesh Chittipeddi
Sailesh Mansinh Merchant
Original Assignee
Lucent Technologies Inc
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Publication of TW426980B publication Critical patent/TW426980B/zh

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    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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Description

'五、發明說明(1) 一 發明範圍_ 本發明係關於製造積體電路,尤其是關於將金線互士 合到銅金屬敷層之方法。 Ί !發明背景 在半導體製造的發展中,持久性技術之一為線結合(弓丨 線鍵合或絲焊)。線結合用於將最早期積體電路站片互連 到引線框架(基座)上,以製造單個積體電路包(組合件)。 在芯片技術發展的同時,亦需要具有更高層次芯片積體的 ;更復雜包’如多片模塊,且需要將此等模塊彼此互連及支 持(電路)板。TAB結合及巨塊結合有效地用作此等包的互 丨連工藝’而線結合應用仍保持在普通I C (積體電路)製造 ;中。 ; 在IC互連技術發展_,早期銅被認定為1C互連的所需候 I選物。銅具有高導電性,亦為廉價,且銅的冶金發展良 好。但銅作為互連材料有早期不良經歷,銅電解性活躍, 且在半導體中產生遷移問題。在經線結合的包中,由於銅 易於與金線結合〉ttl合成合金,且銅—金合金使用不良,所 |以不犯使用銅金屬敷。由於鋼、紹的已知問題,所以次級 丨導體成為I c金屬敷的材料選擇。在此確立紹金屬,其它選 丨擇保留於背景中。 i 現在’ I c技術已推進到鋁導電性為丨c設計限制因素的程 度上°這使方法設計者拒絕金屬材料選擇。重又許可使用 的一種為銅。然而,將鋼冶金積成普通1(:處理為舊問題的 !重新翻版’此等之一為將結合金線結合到銅金屬敷。 —4269 b ο 五'發明說明(2) ' '— 發明概沭 我們開發了將金線結合到鋼金屬敷之方法,其包括在銅 上形成阻擋層,在該阻擋層上形成鋁襯墊。然後將金線熱 壓結合到鋁襯墊上。 μ 繪圖簡述 圖1 -24為進行本發明製程所用步驟之圖解說明。 發明詳述 爹号圖1,所示矽晶片丨1被部分切開,表明其為較大矽 晶片的一部分。應懂得,這些繪圖不成比例,為便於說 明’僅顯示了某些特徵口該矽材係用第一氧化層丨2 (一般 稱為場氧化膜)、金屬互連層13及中間介電層14 ( 一般為X 經沈積氧化物或其它適用的介電材料)覆蓋。低有機性材 料(如乾凝膠或氣凝膠)亦適用。且可使用旋上技術塗上。 此等要素為標準矽IC技術’不構成本發明部分。本發明將 用4基礎結構作為起始點描述’但熟諳此藝者將認識到,· 般積體電路具有三或四層金屬。金屬層13應認作與最 的金屬層鄰接’即使一般有其它層出現(未顯示)。 參考圖2,在該圖中,光刻掩蔽物1 6被加到介電層1 4 上’且以圖形形式暴露部分層間介電層,以製造中間互連 2。應僅得,雖然在此提到光刻或光刻掩蔽物,但可用其 匕刻製技術替代,如使用X-射線或電子束刻製。用抗光蝕 劑作為蝕刻掩蔽物,通過層間介電層形成窗丨8,以層間互 連金屬塊(15),如圖8所示。下一步,以適用的窗塞曰材3料 沈積到電介質及進入窗中,將層間窗1 8插塞。例如,在圖
第5頁 ‘498〇 五、發明說明(3) 4中,可使用雙層(如T i N和鎢),以層2 1和2 2表示。然後將 該晶片用化學機械研磨法(CMP)處理,以產生圖5所示之結 構。TiN/W層之CMP所用之技術描述於美國專利申請案序列 號第09/151,077號,該申請案歸檔於0 9/10/98。現在用金 屬塞23塞入窗中,使該結構物用於沈積下一個金屬敷層。 應瞭解,用圖5之CMP步驟除去不需要的金屬比使用更習用 之掩蔽物及蝕刻處理產生了更平面化的結構物,尤其是按 次序重複數次形成多重金屬層之情形《然而為實現本發明 意圖,可使用任何形成層間互連的的適用方法。 隨後,將蝕刻中斷層25覆蓋式沈積到層間電介質及層間 窗上。適用的蝕刻中斷層為四氮化三矽,該層一般能經受 氧化蝕刻處理(如R IE蝕刻方法),在形成時保護層間塞。 蝕刻中斷層之厚度一般為500-1500埃(Angst roms)。 在圖7中,介電層3 1被沈積到該結構物上,且以光刻掩 蔽物3 2掩蔽,如圖8所示。掩蔽物3 2經形成圖形在鶴塞2 3 上形成窗口 3 3。如圖9所示。較佳用RI E將經暴露氧化物餘 離,使窗3 3中的四氮化三矽蝕刻中斷物移開圖1 〇之結構 物。 在圖1 1中,阻擋層41被覆蓋式沈積到該結構物之表面 上,且進入所示之窗中。該層為界定銅互連層的第一步 驟,按次序描述,該層為1C中的最後或上部金屬層,且為 線結合欲製造的層次。在該結構物中亦可存在其它銅金屬 敷層,但本發明適合於最後金屬層,對該層經線結合製造 互連。阻擋層4 1所用之較佳材料為钽(Ta)、氮化纽
第6頁 4^69Q〇 五、發明說明(4) ! . ! (TaN)、鈦(Ti )或氬化鈦(TiN),亦可使用其它材料。該阻 擋層可通過化學氣相沈積(CVD)或物理氣相沈積(PVD)洗 積。適於使用100-1000埃層。 I 隨後經PVD覆蓋式沈積銅接觸層42,如圖1 2所示。鋼接 觸層之厚度可恰好足以提供用於覆蓋式電解性沈積表面上 之晶種層。如1 0 0 0 -2 0 0 0埃。該銅晶種層42使得能夠經標 準技術電解性沈積銅層4 3。層4 3之厚度應足以完全將窗口 (33)(圖12)塞住,如圖13所示,且較佳為窗口高度的 1. 2-1. 6倍。下一步,用前述CMP方法將表面平面化,以產
生圖1 4所示之結構物,該結構物具有側部和底部由阻擒層 i 45包圍的銅塞44。 S
J 為封閉銅塞4 4的頂部,在圖1 5所示之結構物上覆蓋式.、尤 積第二阻擋層51。該阻擋層基本具有與阻擋層41相同的規 定,並保證封閉銅金屬敷層的所有側面,防止銅在丨c中遷 移。 然後對銅金屬敷層進行線結合接觸,如圖丨6 — 2 〇所示。 在圖16中’薄阻擋層51由厚鋁層52覆蓋。該鋁層52可經 i CVD或PVD沈積,且較佳具有〇· n 〇微米之厚度。 、二 ! 然後使光刻掩蔽物5 3覆於银刻層5 1和5 2上,以界定紹钟 合襯墊,如圖1 7所示。此等層的不需要部分用習用技術^ 蝕分離,以產生結合襯墊5 6,該襯墊5 6與銅塞經阻擋層5 5 隔離,如圖18所示。在該層上通常有很多結合襯墊,隨後 |以習用鈍化層58覆蓋IC。該覆蓋層可以為四氮化三矽 (SINCAPS)或聚合物(如聚醯亞胺)。該覆蓋層較佳為可光
!' " "— -------------------- i五、發明說明(5) —---—-- ;界定性聚醯亞胺。如果為光界定性’那麼使 圖:,或者掩蔽及浸"成窗59,且暴露…襯塾f6 之表面,如圖丨9所示。可用標準抗光触 γ ,, s蜊及Ίά刻技術使四 亂化二矽形成圖形。如果層58為光界定性,可省略抗光蝕 劑’使該層經曝光及顯影自身形成圖形。 在圖20中,線61經熱壓(TC)結合結合到鋁襯墊“上。該 線較佳為金’或具有少量金屬添加劑之合金,以利於硬化 等,如使用金-鈹。該線之直徑一般為〇, 5 —2密耳(mi丨), 較佳1-1.2密耳。該铭結合概替之面積一般為1〇〇〇 4〇〇〇〇 平方微求’較佳50 00-2500 0平方微米。標準使用TC結合操 作。用力可以為15-60克’較佳40-60克。超聲頻率為 *' 40-20 0千赫茲(kHz),較佳為60- 1 2 0千赫茲,電源為 20-20 0毫伏’較佳50- 1 00毫伏,此等參數適用於不同的結 合工具’如K&S線結合裝置。 對上述製程最後數步的一種替代性方法顯示於圖 2卜24。以圖14之結構起始,覆蓋層72在鋁結合襯墊層之 前覆上。在圖21中’窗71顯示於覆蓋層72中。窗71暴露了 ;銅金屬敷層44。如圖22所示,阻擋層73及鋁層74被覆蓋式 I沈積到覆蓋層72上,且進入窗中與銅金屬敷層接觸。然後 !如圖22所示,用掩蔽物76掩蔽鋁層74,將層74和73浸蝕, I形成圊23所示的鋁結合襯墊77。在圖24中,掩蔽物被移 I去,且施加金TC (熱壓)線結合物7 8,完成互連。 I在上述發明之具體實施例仲,最後金屬圖形為銅,所述 阻擋層用於將銅隔離,並防止其遷移到下面的不同冶金學
第8頁 Q q —----- ^ ------- --- '-, 五、發明說明(6) 區域。然而’如果位於下方的層亦包括以銅金屬敷化的最 後層,那麼圖中所示層不需在金屬敷層之間具有阻擋層。 但有時在最後銅結合區域及紹線結合概塾之間存在有效的 阻播仍很重要。 雖然上述方法被開發用於石夕C Μ 0 S (互補型-金屬-氧化物 I -半導體)積體電路’但亦可同樣用於其它類型的積體電 i路,如ΠΙ-ν光性積體電路。此等積體電路一般具有砷化 鎵(GaAs)或磷化銦(InP)基片及多層III-V三元和/或四元 層形成的有源器件。但某些應用中,其互連可與石夕積體電 |路技術相似。此等電路一般在很高速度下操作,為銅金屬 j敷帶來清晰的益處。 i I 今天製造的大多數矽積體電路具有晶體管器件所用的多 晶發柵,該第一層金屬一般為多晶矽,以形成柵及形成這 些柵所用之互連。在第一層後形成的金屬互連層一般為 铭,且一般使用一至三層鋁。其中的一層或多層可用本發 明上述教示方法以銅替代。至少有一層銅層具有線結合部 位’以根據本發明轉變為鋁結合部位.引用第一金屬敷層 或第二金屬敷層應懂得,所述第一層或第二層不必為I c結 構中的第一層或第二層。 | 热請此藝者可對本發明作出各種其它改進。根據基本原 理及等價方法對技藝所作改進對該說明書具體教示方法產 生的偏差,應合理認作在本發明描述及申請之範圍内。
第9頁

Claims (1)

  1. 六、申請專利範圍 _ 1. 一種製造半導體積體電路之方法’其中該上部互連層 包括銅,該方法包括: a)將阻擋層沈積到該上部互連層之經選擇部分上 該阻擋層為選自钽(Ta)、氮化钽(TaN)、鈦(Ti)或氮化鈦 (T i N )及其組合之群之材料; b) 將鋁層沈積到該阻擋層上,及 c) 將導電性線互連結合到該鋁層上。 2.根據申請專利範圍第1項之方法,其中該半導體積體 電路之半導體為矽。 3.根據申請專利範圍第2項之方法,其中該線包括金, ;且用熱壓結合方法結合。 ; 4.根據申請專利範圍第1項之方法,其在步驟a)前包括 !附加步驟,該附加步驟將覆蓋層沈積到該上部互連層,在 I該覆蓋層中形成窗,然後進行步驟a)至c )。 5.根據申請專利範圍第1項之方法,其在步驟c)前包括 ;附加步驟,該附加步驟將覆蓋層沈積到該上部互連層,在 該覆蓋層中形成窗,以暴露該部分鋁層,.然後進行步驟 c) ° 6, —種製造半導體積體電路之方法,其包括以下步驟: a) 在半導體基材上形成銅互連層; b) 將介電層沈積到該銅互連層上; c) 在該介電層上形成多重窗口 ,以留下該銅互連層 ί之經暴露部分; j I d)將阻擋層沈積到該介電層上以及該銅互連層之經 六、申名分 曝露部 e) 將鋁層沈積到該阻擋層上; f) 浸蝕分離該阻擋層及該鋁層之經選擇部分,以將 丨阻擋層襯墊及鋁襯墊留在該第二導電性互連層之經暴露部 !分上: g) 將導線熱壓結合到該鋁襯墊上。 7. 根據申請專利範圍第6項之方法,其中該阻擋層包括 選自鈕(Ta)、氮化鈕(TaN)、鈦(Ti)、氮化鈦(TiN)及其組 合之群之材料。 8. —種製造半導體積體電路之方法,其包括以下步驟: a) 在半導體基材上形成第一導電性互連層,其中該 第一導電性互連層具有第一互連圖形; b) 將第一介電層沈積到該第一導電性互連層上; i c)在該第一介電層形成至少一個層間窗口,以暴露 I 一部分該第一導電性互連層; d) 將第一阻擋層沈積到該第一介電層上,且進入該 層間窗口; e) 將銅層電鍍到該第一阻擋層上,該銅層具有足夠 I厚度,以填充該層間窗口; I ! f)除去部分該第一阻擋層及該銅層,留下阻擋層及 I填充該層間窗口之銅塞; g) 將阻擋層沈積到該第一介電層及該銅塞上; h) 將鋁層沈積到該阻擋層上;
    第11頁
    第12頁
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EP1022776A3 (en) 2000-09-13
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KR100659801B1 (ko) 2006-12-19
US6472304B2 (en) 2002-10-29
KR20000057792A (ko) 2000-09-25
US20010036716A1 (en) 2001-11-01
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DE60039800D1 (de) 2008-09-25
EP1022776A2 (en) 2000-07-26

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