WO2022133756A1

WO2022133756A1 - Method of forming tsv-last interconnect in wafer assembly and method of forming the wafer assembly

Info

Publication number: WO2022133756A1
Application number: PCT/CN2020/138451
Authority: WO
Inventors: Philippe Muller; Weihua Zhu; Ran He; Jeffrey Junhao Xu
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2020-12-23
Filing date: 2020-12-23
Publication date: 2022-06-30
Also published as: EP4233090A4; EP4233090A1

Abstract

A method of forming a through-substrate-via in a wafer assembly with a bottom and a top wafer. Each of the bottom wafer and the top wafer comprises a backside and a frontside. The backside comprises a substrate, and the frontside comprises a plurality of layers and a top layer. The frontside of the bottom wafer comprises one or more metal pads and are bonded to the substrate of the top wafer through a dielectric bonding layer. The method comprises forming an opening from the frontside of the top wafer to the dielectric bonding layer. The method further comprises cladding the opening with an electrically non-conductive material, extending the opening and filling the extended opening with a metal, the metal of the opening being different from the metal of a landing pad. The method avoids the Cu resputtering and diffusion of the resputtered Cu into the substrate of the top wafer.

Description

METHOD OF FORMING TSV-LAST INTERCONNECT IN WAFER ASSEMBLY AND METHOD OF FORMING THE WAFER ASSEMBLY

TECHNICAL FIELD

The present disclosure relates generally to the field of semiconductor devices and more specifically, to a method of forming Through-Substrate-Via (TSV) last interconnect in a stacked wafer assembly, and a method for forming the stacked wafer assembly.

BACKGROUND

Generally, a stacked wafer assembly is defined as an assembly of multiple wafers (or semiconductor wafers) , where multiple wafers are stacked on top of each other by use of a wafer-to-wafer back-to-face (B2F) fusion bonding technology. The multiple wafers used in the stacked wafer assembly can be housed within a single semiconductor package, also termed as an integrated circuit (IC) or a three-dimensional IC. An interconnection or a direct contact between multiple wafers of a conventional stacked wafer assembly is realized using a conventional method of forming a through-substrate-via (TSV) . In the conventional method of forming the TSV, etching of the TSV causes a metal resputtering of a conventioal landing pad of a wafer (e.g. a bottom wafer) of the conventional stacked wafer assembly. The conventional landing pad of the wafer (i.e. the bottom wafer) is made up of copper (Cu) therefore, the metal resputtering corresponds to the Cu resputtering. The resputtered Cu gets diffused into a substrate (which is made up of silicon (Si) ) of a wafer (e.g. a top wafer) which further results into a lower breakdown voltage and a higher leakage current of the conventional TSV.

Currently, certain attempts have been made to manufacture the TSV while avoiding diffusion of the resputtered Cu into the silicon substrate of the wafer (i.e. the top wafer) . A conventional method is based on deposition of a double oxide liner and an embedded barrier in a conventional TSV to avoid the resputtered Cu to get diffused into the silicon substrate of the wafer (i.e. the top wafer) . However, the conventional method of deposition of the double oxide liner and the embedded barrier in the conventional TSV require a high deposition temperature, for example, 400℃ which is incompatible with active devices (e.g. dynamic random access memory (DRAM) ) fabricated on the wafer (i.e. the top wafer) . The reason of incompatibility with active devices is that the active devices, such as dynamic random access memory (DRAM) manifests a temperature (or a thermal budget) less than 230℃. In addition, a low temperature physical vapour deposition (PVD) and a plasma-enhanced chemical vapor deposition (PECVD) deposition are also incompatible with fine pitch and high aspect ratio features of the double oxide liner and the embedded barrier due to step-coverage constrains. Thus, there exists a technical problem of the Cu resputtering and diffusion of the resputtered Cu into the silicon substrate of the wafer (i.e. the top wafer) of the conventional stacked wafer assembly.

Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional approaches of TSV manufacturing in the conventional stacked wafer assembly.

SUMMARY

The present disclosure provides a method of forming a through-substrate-via (TSV) in a stacked wafer assembly. The present disclosure further provides a method of forming the stacked wafer assembly with one or more TSVs. The present disclosure provides a solution to the existing problem of the Cu resputtering and diffusion of the resputtered Cu into the silicon substrate of the wafer of the conventional stacked wafer assembly. An objective of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in the prior art and provides an improved method of forming a TSV in a stacked wafer assembly and further an improved method of forming the stacked wafer assembly with the one or more TSVs.

One or more objectives of the present disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.

In one aspect, the present disclosure provides a method of forming a through-substrate-via (TSV) in a stacked wafer assembly. The stacked wafer assembly comprising a bottom wafer and a top wafer, each of the bottom wafer and the top wafer comprising a backside and a frontside. The backside comprises a substrate, the frontside is located above the backside and comprises a plurality of layers formed above the substrate and comprises a top layer. The top layer of the plurality of layers of the frontside of the bottom wafer comprises one or more metal pads and are bonded to the substrate of the top wafer through a dielectric bonding layer. The method comrpises forming an opening from a surface of the top layer of the plurality of layers of the frontside of the top wafer to the dielectric bonding layer, through the substrate of the backside of the top wafer. The opening having an inner surface. The method further comprises cladding the inner surface of the opening with an electrically non-conductive material. The method further comprises extending the opening to a landing pad amongst the metal pads in the top layer of the plurality of layers of the frontside of the bottom wafer, through the electrically non-conductive material that has been clad onto the inner surface of the opening and through the dielectric bonding layer. The method further comprises filling the extended opening with a metal so as to form a metallic connection between the landing pad in the top layer of the plurality of layers of the frontside of the bottom wafer and a landing pad in the top layer of the plurality of layers of the frontside of the top wafer, the metal of the metallic connection being different from the metal of the landing pad.

The disclosed method of forming the TSV in the stacked wafer assembly avoids the Cu resputtering and diffusion of the resputtered Cu into the substrate of the backside of the top wafer. Additionally, the disclosed method of forming the TSV in the stacked wafer assembly avoids the need of a double oxide liner and an embedded barrier in contrast to a conventional method. The conventional method is based on deposition of the double oxide liner and the embedded barrier in a conventional TSV to avoid the resputtered Cu to get diffused into a silicon substrate therefore, requires high thermal budget which is not preferable. The disclosed method provides a low thermal budget of forming the TSV in the stacked wafer assembly. Moreover, the disclosed method provides a low cost TSV integration in the stacked wafer assembly with enhanced reliability and with a reduced number of steps of forming the TSV.

In an implementation form, a sputter rate, in atoms/ion, of the metal of the metallic connection is higher than the sputter rate, in atoms/ion, of the metal of the landing pad.

By virtue of using the metal of the metallic connection with higher sputter rate, thermal budget of forming the TSV in the stacked wafer assembly get reduced.

In a further implementation form, the metal of the metallic connection is Cu, or Au, or Ag, and the metal of the landing pad is one of, or contains one or more of, W, Ti, Ta, Cr, Al, Pt, Ta, Ru, Co, Ni.

It is advantageous to use different metals for the metal of the metallic connection and the metal of the landing pad to avoid the metal resputtering of the landing pad.

In a further implementation form, the inner surface of the opening comprises a lateral inner surface and a bottom inner surface. The lateral inner surface extends from the surface of the top layer of the top wafer to the bottom inner surface. The bottom inner surface is an upper surface of a portion of the dielectric bonding layer.

The lateral inner surface and the bottom inner surface of the opening provides a more reliable formation of the TSV in the stacked wafer assembly.

In a further implementation form, cladding the inner surface of the opening comprises cladding the lateral inner surface and the bottom inner surface of the opening.

It is advantageous to clad the lateral inner surface and the bottom inner surface of the opening in order to isolate the opening from the substrate of the backside of the top wafer.

In a further implementation form, forming the opening comprises patterning and etching.

The use of patterning and etching for forming the opening provides a low manufacturing cost.

In a further implementation form, cladding the inner surface of the opening comprises oxide chemical vapour deposition, plasma enhanced chemical vapour deposition, sub- atmospheric chemical vapour deposition, laser ablation deposition, dual ion beam sputtering deposition or atomic layer deposition.

It is advantageous to use any of aforementioned processes to deposit a small thickness (e.g., upto 200nm) of the electrically non-conductive material on the inner surface of the opening.

In a further implementation form, extending the opening comprises etching.

By virtue of using etching, the cost of extending the opening is reduced.

In a further implementation form, before extending the opening by etching, a protective layer is deposited, preferably by chemical vapor deposition or physical vapor deposition of a SiN layer, on the edges of the single-lined opening at surface of the top layer of the top wafer.

It is advantageous to use the protective layer of the silicon nitride (SiN) in order to protect the top edges of the inner surface of the opening as well as the frontside of the top wafer during etching of the opening.

In a further implementation form, filling the extended opening with metal so as to form a metallic connection comprises depositing a metal diffusion barrier and a metal seed layer by physical vapor deposition or atomic layer deposition or dual ion beam sputtering, and then by electrochemical deposition and metal sintering.

The metal diffusion barrier and the metal seed layer are deposited in the extended opening to avoid diffusion into the silicon substrate of the plated metal, such as Cu, in the TSV .

In another aspect, the present disclosure provides a method of forming a stacked wafer assembly with one or more through-substrate-via (TSV) . The stacked wafer assembly comprises a bottom wafer and a top wafer, each of the bottom wafer and the top wafer comprises a backside and a frontside. The backside comprises a substrate, the frontside is located above the backside and comprises a plurality of layers formed above the substrate and comprises a top layer. The top layer of the bottom wafer comprises one or more metal pads. The method comprises depositing a first dielectric layer on the top layer of the bottom wafer and a second dielectric layer under the substrate of the top wafer. The method further comprises bonding the first and the second dielectric layers together so as to bond the backside of the top wafer on the frontside of the bottom wafer, and forming one or more TSV, from a surface of the top layer of the top wafer to one or more landing pads amongst the metal pads of the top layer of the bottom wafer.

The disclosed method proposes a simple integration process of forming the stacked wafer assembly with one or more TSV. The disclosed method avoids the need of the conventional double oxide liner and the conventional embedded barrier and replaces the metal of the landing pad of the top wafer as well as of the bottom wafer by low sputter-yield materials to avoid the metal resputtering and the metal diffusion into the substrate of the top wafer and into the first dielectric layer and the second dielectric layer. The disclosed method relaxes the step coverage constraints related to the conventional double oxide liner and the conventional embedded barrier and also provides the reduced thermal budget of manufacturing the stacked wafer assembly with one or more TSV. Moreover, the disclosed method provides the stacked wafer assembly with one or more TSV with enhanced reliability, low manufacturing cost and with a reduced number of steps of forming the TSV.

In an implementation form, the method further comprises before depositing the first and second dielectric layers and bonding them together, forming the landing pad by depositing a landing metal layer in the top layer of the bottom wafer.

The landing pad is formed to connect the top wafer and the bottom wafer through the metal of the metallic connection in the stacked wafer assembly. The landing pad also provides a reduced size of the stacked wafer assembly.

In a further implementation form, forming the landing pad comprises depositing the landing metal layer on top of an existing metal pad formed in the same metal as the metal of the metallic connection.

Since the metal of the existing metal pad is same as that of the metal of the metallic connection, therefore, thermal budget of manufacturing the stacked wafer assembly is reduced.

In a further implementation form, depositing the landing pad layer comprises a damascene deposition process using chemical mechanical polishing.

By virtue of using the damascene deposition process, it is feasible to deposit the landing pad layer of the metal which ischemical mechanical polishing (CMP) treatable, for example, tantalum (Ta) , titanium (Ti) , titanium nitride (TiN) , tantalum nitride (TaN) , titanium-tungsten (TiW) , tungsten (W) or cobalt (Co) . The CMP of the metal of the landing pad layer is realized to remove excess metal deposited on the one or more metal pads and to obtain a suitable roughness of the landing pad layer.

In a further implementation form, forming the landing pad comprises a semi-additive metal patterning process.

It is advantageous to use the semi-additive metal patterning process in a case where the metal of the landing pad layer can not be treated with CMP.

In a further implementation form, forming the landing pad comprises a metal etching deposition process.

In a further implementation form, forming the landing pad comprises a lift-off deposition process.

In a further implementation form, the method further comprises forming a redistribution layer on the top layer of the top wafer. The redistribution layer comprises one or more metal pads, one or more of these metal pads are connected with the metallic connection in the opening.

By virtue of using the redistribution layer (RDL) with one or more metal pads, structural complexity of the stacked wafer assembly is reduced, because one or more metal pads of the RDL are directly connected with the metallic connection (or TSV) in the opening.

In a further implementation form, the top layer of the top wafer comprises one or more metal pads, one or more of these metal pads are connected with the one or more metal pads of the redistribution layer connected with the metallic connection in the opening.

The one or more metal pads of the RDL provides an interconnection between the top wafer and the bottom wafer through the one or more metal pads comprised by the top wafer and the bottom wafer, respectively.

In a further implementation form, the method further comprises forming a landing pad, in the same metal as the metal of the landing pad in the top layer of the bottom wafer, on top of the one or more metal pads of the redistribution layer connected with the metallic connection in the opening.

It is advantageous to form the landing pad on top of the one or more metal pads of the RDL with the same metal as that of the landing pad in the top layer of the bottom wafer in order to stack multiple wafers in addition to the top wafer and the bottom wafer.

It is to be appreciated that all the aforementioned implementation forms can be combined.

It has to be noted that all devices, elements, circuitry, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.

Additional aspects, advantages, features and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.

Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:

FIG. 1 is a flowchart of a method of forming a through-substrate-via (TSV) in a stacked wafer assembly, in accordance with an embodiment of the present disclosure;

FIG. 2 is a flowchart of a method of forming a stacked wafer assembly with one or more TSV, in accordance with an embodiment of the present disclosure;

FIGs. 3A and 3B collectively is an illustration that depicts steps of reliable landing metal deposition on a bottom wafer using a damascene deposition process, in accordance with an embodiment of the present disclosure;

FIGs. 4A and 4B collectively is an illustration that depicts steps of reliable landing metal deposition on a bottom wafer using a metal etching deposition process, in accordance with an embodiment of the present disclosure;

FIGs. 5A and 5B collectively is an illustration that depicts steps of reliable landing metal deposition on a bottom wafer using a lift-off deposition process, in accordance with an embodiment of the present disclosure;

FIG. 6 is an illustration that depicts steps of manufacturing a top wafer, in accordance with an embodiment of the present disclosure; and

FIGs. 7A-7E collectively is an illustration that depicts steps of forming one or more TSV in a stacked wafer assembly, in accordance with an embodiment of the present disclosure.

In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non-underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.

DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible.

FIG. 1 is a flowchart of a method of forming a through-substrate-via (TSV) in a stacked wafer assembly, in accordance with an embodiment of the present disclosure. With reference to FIG. 1, there is shown a flowchart of a method 100 of forming a through-substrate-via (TSV) in a stacked wafer assembly. The method 100 includes

steps

102, 104, 106, and 108. The method 100 is executed by a stacked wafer assembly described in detail, for example, in FIGs. 7A-7E.

The method 100 of forming a through-substrate-via (TSV) in a stacked wafer assembly, the stacked wafer assembly comprises a bottom wafer and a top wafer, each of the bottom wafer and the top wafer comprises a backside and a frontside. The backside comprises a substrate, the frontside is located above the backside and comprises a plurality of layers formed above the substrate and comprises a top layer. The top layer of the plurality of layers of the frontside of the bottom wafer comprises one or more metal pads and are bonded to the substrate of the top wafer through a dielectric bonding layer. In the stacked wafer assembly, multiple wafers are stacked over each other, such as the top wafer and the bottom wafer. The stacked wafer assembly may also be referred as a wafer-level packaging, a wafer to wafer assembly, a die stacking, a chip stacking, and the like. The stacked wafer assembly is generally used in processors, memory, or any other portable or non-portable electronic device. The through-substrate-via (TSV) refers to a via (or opening) which is filled with a metal and passes through the substrate of the top wafer of the stacked wafer assembly to electrically connect the top wafer and the bottom wafer. The TSV may also be referred as a through-silicon via, through-chip via, vertical connection via, and the like. The TSV is used as an alternative of a conventional wire-bond and a conventional flip-chip used in semiconductor packages, because the TSV manifests a simple structure, high-density, high-functionality, and an improved form-factor as compared to the conventional wire-bond and the conventional flip-chip. In general, the TSV-last approach corresponds to formation of the TSV after (or during) a back end of line (BEOL) processing of each wafer. The BEOL is a layer amongst the plurality of layers of the frontside of each of the top wafer and the bottom wafer, where a plurality of transistors (and other circuit elements) are interconnected. The backside of each of the top wafer and the bottom wafer includes the substrate, such as a silicon substrate. Similarly, the frontside of each of the top wafer and the bottom wafer includes the top layer, where the top layer further includes the plurality of layers, such as the BEOL layer with one or more metal pads, or landing pads (or contact pads) and the like. An example of the metal pads and the landing pads is described in detail, for example, in FIGs. 3A, 3B, 4A, 4B, 5A and 5B. In general, the frontside and the backside are two opposite sides of each of the top wafer and the bottom wafer. The frontside of each of the top wafer and the bottom wafer is a three-dimensional (3D) region and includes actives devices, such as transistors, diodes, voltage sources, current sources, and the like. The method 100 of forming the TSV in the stacked wafer assembly includes the deposition of the dielectric bonding layer on the backside (i.e., the substrate) of the top wafer and also on the frontside (i.e., on the top layer) of the bottom wafer. Examples of the dielectric bonding layer include, but are not limited to, a silicon dioxide (SiO2) layer, silicon nitride (SiN) layer, silicon carbon nitride (SiCN) layer, silicon oxycarbon nitride (SiOCN) layer, etc. The dielectric bonding layer is used to obtain a high bond strength along with a void-free bonding of the one or more metal pads arranged in the top layer of the plurality of layers of the frontside of the bottom wafer with the substrate of the top wafer. The bonding of the backside of the top wafer to the frontside of the bottom wafer through the dielectric bonding layer may also be referred as a wafer to wafer back to face (B2F) fusion bonding. An exemplary scenario of forming the through-substrate-via (TSV) in the stacked wafer assembly is described in detail, for example, in FIGs. 7A-7E.

At step 102, the method 100 comprises forming an opening from a surface of the top layer of the plurality of layers of the frontside of the top wafer to the dielectric bonding layer, through the substrate of the backside of the top wafer. The opening comprises an inner surface. The opening (which further acts as the TSV) is formed for example, by etching from the surface of the top layer of the plurality of layers of the frontside of the top wafer to the dielectric bonding layer. The dielectric bonding layer is arranged at the substrate of the backside of the top wafer and at the frontside of the bottom wafer. The opening comprises the inner surface which extends from the surface of the top layer of the plurality of layers of the frontside of the top wafer to the dielectric bonding layer that is arranged in between the top wafer and the bottom wafer.

At step 104, the method 100 further comprises cladding the inner surface of the opening with an electrically non-conductive material. In an implementation, the inner surface of the opening is clad with the electrically non-conductive material, for example a single lining of an oxide (e.g. a metal oxide) is deposited on the inner surface of the opening. Alternatively stated, a single oxide lining (or a oxide liner) is deposited on the inner surface of the opening. The thickness of the non-conductive material may range up to 200 nanometer (nm) . Beneficially, in comparison with a conventional double oxide liner, the single oxide lining (or the oxide liner) relaxes the step coverage constrains related to the conventional double oxide liner and a conventional embedded barrier.

At step 106, the method 100 further comprises extending the opening to a landing pad amongst the metal pads in the top layer of the plurality of layers of the frontside of the bottom wafer, through the electrically non-conductive material that has been clad onto the inner surface of the opening and through the dielectric bonding layer. The opening is extended to the landing pad amongst the metal pads in the top layer of the plurality of layers of the frontside of the bottom wafer, through the electrically non-conductive material that has been clad onto the inner surface of the opening and through the dielectric bonding layer by etching of the electrically non-conductive material that has been clad onto the inner surface (e.g. bottom side) of the opening along with a portion of the dielectric bonding layer that lies beneath the inner surface (i.e. bottom side) of the opening.

At step 108, the method 100 further comprises filling the extended opening with a metal so as to form a metallic connection between the landing pad in the top layer of the plurality of layers of the frontside of the bottom wafer and a landing pad in the top layer of the plurality of layers of the frontside of the top wafer, the metal of the metallic connection is different from the metal of the landing pad. The extended opening is filled with the metal to form the metallic connection between the landing pad of the bottom wafer and the landing pad of the top wafer. The extended opening is filled with the metal up to the top layer of the plurality of layers of the frontside of the top wafer. In an implementation, bottom-up filling of the extended opening with the metal is realized by using an electrochemical deposition (ECD) process. In general, the electrochemical deposition (ECD) process is used for deposition of one metal on a surface of another metal by use of an electric field.

Conventionally, copper (Cu) is used as the metal of the landing pad which causes the Cu resputtering and diffusion of the resputtered Cu into silicon substrate of a wafer of a conventional stacked wafer assembly. This further leads to a lower breakdown voltage and a high leakage current of a conventional TSV and hence, not preferred. Therefore, the metal of the metallic connection is different from the metal of the landing pad of each of the bottom wafer and the top wafer to limit resputtering of the metal of the landing pad and avoid the diffusion of the resputtered metal into the substrate (i.e. silicon substrate) of the top wafer and the dielectric bonding layer. Therefore, the metal of the landing pad (i.e. the landing pad of the top wafer and the landing pad of the bottom wafer) is chosen from low sputter-yield materials. The low sputter-yield materials (or metals) relax the step coverage constrains related to the conventional double oxide liner and of the conventional embedded barrier which are required in a conventional TSV. The low sputter-yield materials provide a very low diffusion of the metal of the landing pad into the substrate of the top wafer as well as into the dielectric bonding layer. The low sputter-yield materials also provide a reduced thermal budget of forming the TSV in the stacked wafer assembly. The method 100 can be repeated in order to stack one or more wafers in addition to the top wafer and the bottom wafer by forming the TSV.

In accordance with an embodiment, a sputter rate, in atoms/ion, of the metal of the metallic connection is higher than the sputter rate, in atoms/ion, of the metal of the landing pad. Generally, the sputter rate in atoms/ion represents an average number of metal atoms which are removed from a target surface of a metal per incident ion. The metal of the metallic connection manifests higher sputter rate than the metal of the landing pad to avoid resputtering of the metal of the landing pad and diffusion of the resputtered metal into the substrate (i.e. silicon substrate) of the top wafer and the dielectric bonding layer. Additionally, a thermal budget of forming the TSV in the stacked wafer assembly also get reduced.

In accordance with an embodiment, the metal of the metallic connection is Cu, or Au, or Ag, and the metal of the landing pad is one of, or contains one or more of, W, Ti, Ta, Cr, Al, Pt, Ta, Ru, Co, Ni. The metal of the metallic connection is either a copper (Cu) metal, or a gold (Au) metal, or a silver (Ag) metal that manifests the higher sputter rate than the metal of the landing pad. Moreover the metal of the landing pad is one of, or contains one or more of tungsten (W) , titanium (Ti) , tantalum (Ta) , chromium (Cr) , aluminium (Al) , platinum (Pt) , ruthenium (Ru) , cobalt (Co) , nickel (Ni) , and the like, that manifests the lower sputter rate. The metal of the landing pad may also be an alloy of aforementioned metals, such as titanium tungsten (TiW) , titanium nitride (TiN) , and the like. It is advantageous to use different metals for the metal of the metallic connection and the metal of the landing pad to avoid the metal resputtering of the landing pad.

In accordance with an embodiment, the inner surface of the opening comprises a lateral inner surface and a bottom inner surface. The lateral inner surface extends from the surface of the top layer of the top wafer to the bottom inner surface, and the bottom inner surface is an upper surface of a portion of the dielectric bonding layer. The lateral inner surface of the opening extends from the surface of the top layer of the plurality of layers of the frontside of the top wafer to the bottom inner surface. The lateral inner surface of the opening may also be referred as an inner wall (or a vertical inner surface) of the opening. The bottom inner surface of the opening is the upper surface of the portion of the dielectric bonding layer that is arranged at the substrate of the backside of the top wafer and at the frontside of the bottom wafer. The bottom inner surface may also be referred to as a bottom wall (or a horizontal inner surface) of the opening.

In accordance with an embodiment, cladding the inner surface of the opening comprises cladding the lateral inner surface and the bottom inner surface of the opening. In an implementation, the lateral inner surface and the bottom inner surface of the opening are clad by using an electrically non-conductive material, such as deposition of an oxide liner. Alternatively stated, the oxide liner, or a single-lining of oxide is deposited on the lateral inner surface and the bottom inner surface of the opening. In an example, the thickness of the non-conductive material (i.e. the oxide liner, or the single-lining of oxide) is up to 200nm. The lateral inner surface and the bottom inner surface of the opening are clad for isolation purpose, such as to isolate the opening from the substrate of the backside of the top wafer.

In accordance with an embodiment, forming the opening comprises patterning and etching. In an example, before forming the opening, the front side of the top wafer is coated with a thick hard mask layer of silicon dioxide (SiO2) , silicon nitride (SiN) , or amorphous carbon patternable film (APF) by use of chemical vapour deposition (CVD) . The silicon dioxide (SiO2) layer is further covered with a photoresist (PR) material, which acts as a mask (i.e. for patterning) and used for etching the BEOL and the substrate of the top wafer. The photoresist material (e.g., a positive photoresist or a negative photoresist) is a light sensitive material which is used to form a pattern after etching the PR mask, the BEOL, and the substrate from a selected surface (or portion) of the top wafer, for example using photolithography, and the like. The etching of the substrate of the top wafer stops at the dielectric bonding layer (or bond-dielectric) that is arranged at the substrate of the backside of the top wafer and at the frontside of the bottom wafer and hence, the opening is formed from the front side of the top wafer upto the front side of the bottom wafer.

In accordance with an embodiment, cladding the inner surface of the opening comprises oxide chemical vapour deposition, plasma enhanced chemical vapour deposition, sub-atmospheric chemical vapour deposition, laser ablation deposition, dual ion beam sputtering deposition or atomic layer deposition. The oxide liner, or the single-lining of oxide is deposited on the inner surface of the opening by use of any one of chemical vapour deposition (CVD) , plasma-enhanced chemical vapor deposition (PECVD) , sub-atmospheric chemcical vapour deposition (SACVD) , laser ablation deposition (LAD) , dual ion beam sputtering deposition (DIBSD) , atomic layer deposition (ALD) (or low temperature ALD) , and the like, processes. These processes are useful in order to provide a thin layer (e.g. with a thickness of 200nm) of the oxide liner on the inner surface of the opening.

In accordance with an embodiment, extending the opening comprises etching. The etching is performed to remove the non-conductive material (i.e., the oxide liner) from the bottom inner surface of the opening and the portion of the dielectric bonding layer that lies beneath the bottom inner surface of the opening, which results in a low cost extension of the opening. The etching of the portion of the dielectric bonding layer is stopped at the landing pad in the top layer of the plurality of layers of the frontside of the bottom wafer, where the landing pad is one of the amongst metal pads of the bottom wafer.

In accordance with an embodiment, before extending the opening by etching, a protective layer is deposited, preferably by chemical vapor deposition or physical vapor deposition of a silicon nitride (SiN) layer, on the edges of the opening at surface of the top layer of the top wafer. In an implementation, before etching the bottom inner surface of the opening and the portion of the dielectric bonding layer, the surface of the top layer of the plurality of layers of the frontside of the top wafer is covered with the protective layer (i.e. the silicon nitride (SiN) layer) . The protective layer (i.e. the silicon nitride layer) is deposited to protect the top edges of the inner surface of the opening as well as the frontside of the top wafer during etching of the opening. The protective layer (i.e. the silicon nitride layer) is deposited by use of any one of the processes, such as chemical vapour deposition (CVD) , or physical vapour deposition (PVD) .

In accordance with an embodiment, extending the opening is then realized by plasma etching. The top SiN layer is removed during the operation allowing the top-TSV liner oxide to be protected. The plasma etching stops on the landing pad. Since the landing pad metal is a low-sputter yield and low diffisivity material, reduced metal ions will deposit to the TSV oxide liner, or a single-lining of oxide that is deposited on the lateral inner surface. This resputtered metal will not be able to diffuse though the oxide liner since no Cu, Au or Ag is present in the landing pad.

In accordance with an embodiment, filling the extended opening with metal so as to form a metallic connection comprises depositing a metal diffusion barrier and a metal seed layer by physical vapor deposition or atomic layer deposition or dual ion beam sputtering, and then by electrochemical deposition and metal sintering. In other words, filling the extended opening with the metal to form the metallic connection between the top wafer and the bottom wafer includes the deposition of the metal diffusion barrier and the metal seed layer. The metal diffusion barrier is formed either of titanium (Ti) metal, or titanium nitride (TiN) metal alloy, or tantalum nitride (TaN) metal alloy, or tantalum (Ta) metal, and the like. The metal seed layer is a thin layer of metal (e.g. Cu) , which is deposited for electrical conduction within the extended opening (or the TSV) . The metal diffusion barrier and the metal seed layer are deposited by using one of the physical vapor deposition (PVD) , atomic layer deposition (ALD) , dual ion beam sputtering (DIBS) , electrochemical deposition (ECD) , and the metal sintering. Optionally, seed repair step comprising an alkaline electro chemical deposition (ECD) or an electroless deposition (ELD) of the metal seed layer (e.g. Cu seed layer) can be realized to restore the discontinuities of the metal seed layer (i.e. Cu seed layer) , where the ELD is an auto-catalytic technique, which is generally used to deposit metals (or to deposit high-resolution metal patterns) on different wafers (or substrates) of the stacked wafer assembly.

Thus, the method 100 proposes a simple integration process of forming the TSV in the stacked wafer assembly by avoiding the need of the conventional double oxide liner and the conventional embedded barrier. The method 100 is further configured to replace the metal of the landing pad of the top wafer as well as of the bottom wafer by the low sputter-yield materials to avoid the metal resputtering and diffusion of the resputtered metal into the substrate (or silicon) of the top wafer as well as into the dielectric layer. The method 100 relaxes the step coverage constrains related to the conventional double oxide liner and the conventional embedded barrier and also provides a reduced thermal budget of manufacturing the TSV in the stacked wafer assembly.

The

steps

102, 104, 106, and 108 are only illustrative and other alternatives can also be provided where one or more steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein.

FIG. 2 is a flowchart of a method of forming a stacked wafer assembly with one or more TSV, in accordance with an embodiment of the present disclosure. FIG. 2 is described in conjunction with elements from FIG. 1. With reference to FIG. 2, there is shown a flowchart of a method 200 of forming a stacked wafer assembly. The method 200 includes steps 202 to 206. The method 200 is executed by a stacked wafer assembly described in detail, for example, in FIGs. 7A-7E.

The method 200 of forming a stacked wafer assembly with one or more through-substrate-via (TSV) . The stacked wafer assembly comprises a bottom wafer and a top wafer, each of the bottom wafer and the top wafer comprises a backside and a frontside. The backside comprises a substrate, the frontside is located above the backside and comprises a plurality of layers formed above the substrate and comprises a top layer. The top layer of the bottom wafer comprises one or more metal pads. In the stacked wafer assembly, each of the top wafer and the bottom wafer includes the frontside and the backside, where the frontside and the backside are two opposite sides of each other. The backside of each of the top wafer and the bottom wafer includes the substrate, such as a silicon substrate. Similarly, the frontside of each of the top wafer and the bottom wafer includes the top layer, where the top layer further includes the plurality of layers such as a back end of line (BEOL) layer, one or more metal pads and the like. An exemplary scenario of forming the stacked wafer assembly with one or more through-substrate-via (TSV) is described in detail, for example, in FIGs. 7A-7E.

At step 202, the method 200 comprises depositing a first dielectric layer on the top layer of the bottom wafer and a second dielectric layer under the substrate of the top wafer. In an implementation, the first dielectric layer and the second dielectric layer may also be referred as a dielectric bonding layer. Examples of the first dielectric layer and the second dielectric layer include, but are not limited to, a silicon dioxide (SiO2) layer, a silicon nitride (SiN) layer, a silicon carbon nitride (SiCN) layer, a silicon oxycarbon nitride (SiOCN) layer, and the like. The first dielectric layer is deposited at the frontside of the bottom wafer, and the second dielectric layer is deposited at the backside of the top wafer. The second dielectric layer of the top wafer manifests a roughness similar to that of the first dielectric layer of the bottom wafer. In certain implementation scenarios, chemical mechanical polishing (CMP) is required before deposition of the first dielectric layer and the second dielectric layer for smoothing of the frontside of the bottom wafer and the backside of the substrate of the top wafer.

At step 204, the method 200 further comprises bonding the first and the second dielectric layers together so as to bond the backside of the top wafer on the frontside of the bottom wafer. After deposition of the first dielectric layer and the second dielectric layer, the backside of the top wafer is bonded on the frontside of the bottom wafer through the first dielectric layer and the second dielectric layer. Therefore, the first dielectric layer and the second dielectric layer bond to each other. The first dielectric layer and the second dielectric layer are used to obtain a high bond strength along with void-free bonding. Moreover, the CMP of the first dielectric layer and the second dielectric layer is required before fusion bonding (or direct bonding) of the top wafer and the bottom wafer.

At step 206, the method 200 further comprises forming one or more TSV from a surface of the top layer of the top wafer to one or more landing pads amongst the metal pads of the top layer of the bottom wafer. After bonding the top wafer and the bottom wafer, annealing is performed to strengthen the bonding. The one or more TSV (or opening) are formed using patterning and etching from the frontside of the top wafer up to the second dielectric layer of the top wafer, and the first dielectric layer of the bottom wafer. Each of the one or more TSV (or opening) includes an inner surface which further includes a lateral inner surface and a bottom inner surface. The lateral inner surface extends from the surface of the top layer of the plurality of layers of the frontside of the top wafer to the bottom inner surface. The bottom inner surface is an upper surface of a portion of the second dielectric layer of the top wafer, and the first dielectric layer of the bottom wafer. The lateral inner surface and the bottom inner surface of each of the one or more TSV (or opening) are clad with an electrically non-conductive material. For example, a single lining of an oxide is deposited on the lateral inner surface and the bottom inner surface of each of the one or more TSV (or opening) . Thereafter, each of the one or more TSV (or opening) is extended to the landing pad amongst the metal pads in the top layer of the plurality of layers of the frontside of the bottom wafer. The each of the one or more TSV (or opening) is extended by etching of the electrically non-conductive material that has been clad onto the lateral inner surface and the bottom inner surface of each of the one or more TSV (or opening) along with the portion of the dielectric bonding layer that lies beneath the bottom inner surface of each of the one or more TSV (or opening) . The one or more TSV (or extended opening) is filled with the metal (e.g., copper (Cu) metal) up to the top layer of the plurality of layers of the frontside of the top wafer, to form the metallic connection between the landing pad of the bottom wafer and the landing pad of the top wafer. The metal of the metallic connection is different from the metal of the landing pad of the bottom wafer as well as from the metal of the landing pad of the top wafer to avoid metal resputtering and diffusion of the resputtered metal into the substrate of the top wafer as well as into the first dielectric layer, and the second dielectric layer. Therefore, the metal of the landing pad of the top wafer and the landing pad of the bottom wafer is chosen from low sputter-yield materials. The low sputter-yield materials also provides a very low diffusion of the metal of the landing pad into the substrate of the top wafer as well as into the first dielectric layer, and the second dielectric. Thus, the low sputter-yield materials reduces the thermal budget of forming the stacked wafer assembly with one or more TSV by avoiding the double liner and embedded barrier method. The method 200 can be repeated in order to stack one or more wafers in addition to the top wafer and the bottom wafer through the one or more TSV.

In accordance with an embodiment, before depositing the first and second dielectric layers and bonding them together, forming the landing pad by depositing a landing metal layer in the top layer of the bottom wafer. The landing pad is formed in the top layer of the frontside of the bottom wafer by depositing the landing metal layer of low sputter yield materials. The landing metal layer is deposited using one of physical vapour deposition (PVD) , electron Beam (e-Beam) evaporation, chemical vapour deposition (CVD) , or via atomic layer deposition (ALD) . The metal of the landing metal layer deposited using a metal deposition process on the top layer of the bottom wafer is either a CMP treatable metal (e.g. a damascene metal deposition process) or a CMP non-treatable metal (e.g. a metal etching deposition process, or a lift-off metal deposition process) . Examples of the CMP treatable metal include, but is not limited to, tantalum (Ta) , titanium (Ti) , titanium nitride (TiN) , tantalum nitride (TaN) , titanium-tungsten (TiW) , tungsten (W) , or cobalt (Co) and the like. The landing pad also provides a reduced size of the stacked wafer assembly.

In accordance with an embodiment, forming the landing pad comprises depositing the landing metal layer on top of an existing metal pad formed in the same metal as the metal of the metallic connection. The landing metal layer is deposited on top of the existing metal pad that is comprised by the BEOL of the frontside of the bottom wafer. The metal of the existing metal pad on the BEOL of the frontside of the bottom wafer is same as that of the metal of the metallic connection. However, the metal of the existing metal pad on the BEOL of the frontside of the bottom wafer is different from the metal of the landing pad which further results, into a low thermal budget (or temperature) of forming one or more TSV in the stacked wafer assembly.

In accordance with an embodiment, depositing the landing pad layer comprises a damascene deposition process using chemical mechanical polishing. The damascene metal deposition process is used when the metal of the landing metal layer is CMP treatable. Examples of the CMP treatable metal include, but is not limited to, tantalum (Ta) , titanium (Ti) , titanium nitride (TiN) , tantalum nitride (TaN) , titanium-tungsten (TiW) , tungsten (W) , or cobalt (Co) and the like. After deposition of the landing metal layer, the CMP of the landing metal layer is realized to clear an excess metal of landing metal layer deposited in between the one or more metal pads of the bottom wafer. The CMP of the landing metal layer provides a suitable roughness of the landing metal layer and also leads to formation of the landing pad in the bottom wafer. Additionally, in the damascene metal deposition process, the landing metal layer is deposited after an oxide patterning on the frontside of the top wafer. The damascene metal deposition process is described in detail, for example, in FIGs. 3A and 3B.

In accordance with an embodiment, forming the landing pad comprises a semi-additive metal patterning process. The semi-additive metal patterning process is used when the metal of the landing metal layer can not be treated with CMP. In the semi-additive metal patterning process, the landing metal layer is directly deposited on the frontside of the top wafer without any oxide patterning. The deposition of the landing metal layer on the frontside of the top wafer without the oxide patterning makes the semi-additive metal patterning process different from the damascene metal deposition process.

In accordance with an embodiment, forming the landing pad comprises a metal etching deposition process. The deposition of the landing metal layer on the frontside of the top wafer can be realized before or after a photoresist (PR) patterning. In a case, if the PR patterning is realized after the deposition of the landing metal layer, then in such a case, either a wet or a dry chemistry is used to remove an excess metal of landing metal layer deposited in between the one or more metal pads of the bottom wafer. The process of using either the wet or the dry chemistry for removal of the excess metal of landing metal layer deposited in between the one or more metal pads of the bottom wafer is termed as the metal etching deposition process. The metal etching deposition process is described in detail, for example, in FIGs. 4A and 4B.

In accordance with an embodiment, forming the landing pad comprises a lift-off deposition process. In another case, if the wet or the dry chemistry is not available for removal of the excess metal of landing metal layer deposited in between the one or more metal pads of the bottom wafer, then in such a case, the PR patterning is realized before the deposition of the landing metal layer. In such a case, the landing metal layer is deposited on the frontside of the bottom wafer as well as on the PR material. Thereafter, the excess metal of the landing metal layer is removed by use of a solvent, or a stripper, or any other chemical that also dissolves the PR material deposited under the metal of the landing metal layer, and further leads to the formation of the landing pad on the bottom wafer. The process of using the solvent, or the stripper, or the other chemical for removal of the excess metal of the landing metal layer and the PR material deposited under the metal of the landing metal layer is termed as the lift-off deposition process. The lift-off deposition process is described in detail, for example, in FIGs. 5A and 5B.

In accordance with an embodiment, the method 200 further comprises forming a redistribution layer on the top layer of the top wafer. The redistribution layer comprises one or more metal pads, one or more of these metal pads being connected with the metallic connection in the opening. The redistribution layer (RDL) is formed, for example, using the damascene metal deposition process, on the frontside of the top wafer. The RDL includes the one or metal pads and the one or more of these metal pads are directly connected with the metallic connection in the opening (or TSV) because of composing the same metal. In general the RDL is created for providing an interconnection between the top wafer and the bottom wafer.

In accordance with an embodiment, the top layer of the top wafer comprises one or more metal pads, one or more of these metal pads being connected with the one or more metal pads of the redistribution layer connected with the metallic connection in the opening. The top layer, such as the BEOL of the top wafer includes the one or more metal pads, which are connected with the one or more metal pads of the RDL. In this way, the one or more metal pads of the BEOL of the top wafer get connected with the metallic connection in the opening and hence, provides an improved interconnection between the top wafer and the bottom wafer.

In accordance with an embodiment, the method 200 further comprises forming a landing pad, in the same metal as the metal of the landing pad in the top layer of the bottom wafer, on top of the one or more metal pads of the redistribution layer connected with the metallic connection in the opening. The landing pad is formed on top of the one or more metal pads of the redistribution layer (RDL) . The landing pad of the RDL is formed in the same metal as the metal of the landing pad of the bottom wafer, to reduce the metal resputtering in the substrate of the top wafer. The landing pad of the RDL is connected with the metallic connection in the opening through the one or more metal pads of the RDL. Moreover, the landing pad of the RDL may be further used to stack one or more wafers on the frontside of the top wafer by use of the back-to-face (B2F) wafer bonding technology. The landing pad of the RDL may also be referred as the landing pad of the top wafer.

Thus, the method 200 proposes a simple integration process of forming the stacked wafer assembly with one or more TSV. The method 200 avoids the need of the conventional double oxide liner and the conventional embedded barrier and replaces the metal of the landing pad of the top wafer as well as of the bottom wafer by low sputter-yield materials to avoid the metal resputtering and the metal diffusion into the substrate of the top wafer and into the first dielectric layer and the second dielectric layer. The method 200 relaxes the step coverage constraints related to the conventional double oxide liner and the conventional embedded barrier and also provides the reduced thermal budget of manufacturing the stacked wafer assembly with one or more TSV. Moreover, the method 200 provides the stacked wafer assembly with one or more TSV with enhanced reliability, low manufacturing cost and with a reduced number of steps of forming the TSV.

The

steps

202, 204, and 206 are only illustrative and other alternatives can also be provided where one or more steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein.

FIGs. 3A and 3B collectively is an illustration that depicts steps of reliable landing metal deposition on a bottom wafer using a damascene deposition process, in accordance with an embodiment of the present disclosure. FIGs. 3A and 3B are described in conjunction with elements from FIGs. 1 and 2. With reference to FIGs. 3A and 3B, there is shown a metal deposition process 300 that includes a cross-sectional view of a bottom wafer 304, which is subjected to reliable landing metal deposition using a damascene deposition process. The bottom wafer 304 represents a single wafer of a stacked wafer assembly.

In the FIGs. 3A and 3B, the cross-sectional view of the bottom wafer 304 includes a backside 304A and a frontside 304B. The backside 304A includes a substrate 306. The frontside 304B includes a plurality of layers such as a back end of the line (BEOL) 308, a metal pad 310, and a passivation layer 312. The bottom wafer 304 is generally made up of a semiconductor material. The bottom wafer 304 may also be referred as a die or a slice. In an implementation, the bottom wafer 304 may also be referred as an actuator wafer. The substrate 306 is a thin slice made up of semiconductor materials (e.g. silicon (Si) ) . The substrate 306 acts as a supporting base for the bottom wafer 304. The back end of line (BEOL) 308 is a portion of the bottom wafer 304, where a plurality of devices, such as transistors, capacitors or resistors, and the like are interconnected. The BEOL 308 of the bottom wafer 304 includes a plurality of bonding (or contact) sites for interconnections with another wafer. The metal pad 310 is arranged in the BEOL 308 and used for electrical conduction purposes. The metal of the metal pad 310 is one of a copper (Cu) metal, or a gold (Au) metal, or a silver (Ag) metal. In an implementation, the bottom wafer 304 may include one or more metal pads. The metal deposition process 300 includes steps 302A to 302F (steps 302A-302C of the metal deposition process 300 are shown in FIG. 3A and steps 302D-302F are shown in FIG. 3B) .

With reference to FIG. 3A, at step 302A, the passivation layer 312 is deposited over the BEOL 308 of the frontside 304B of the bottom wafer 304. The passivation layer 312 is used to prevent oxidation of the frontside 304B and edges of the bottom wafer 304. Alternatively stated, the passivation layer 312 acts as a shield for the frontside 304B of the bottom wafer 304. For example, the passivation layer 312 is deposited on the frontside 304B of the bottom wafer 304 using thermal oxidation.

At step 302B, a dielectric layer 314 is deposited on the passivation layer 312 of the bottom wafer 304. The dielectric layer 314 is generally composed of oxides, such as silicon oxide (SiO) , silicon nitride (SiN) , silicon carbide (SiC) , silicon carbo oxide layer (SiCO) or any other oxide with a low dielectric constant (k) . The thickness of the dielectric layer 314 may range from 10 nanometer (nm) to 100 nanometer (nm) . Further, the chemical mechanical polishing (CMP) of the dielectric layer 314 is required to achieve a suitable low surface roughness and a good planarity of the dielectric layer 314. Generally, in the chemical mechanical polishing a combination of chemical and mechanical forces is used to reduce roughness of a dielectric bonding layer and also for smoothing of the dielectric bonding layer (e.g. the dielectric layer 314) .

At step 302C, a photoresist (PR) material is deposited over the dielectric layer 314 and thereafter, and the PR material is exposed to light (e.g., ultraviolet light) to remove the PR material from a selected area. Thereafter, the etching is performed to remove the dielectric layer 314 and the passivation layer 312. The etching of the dielectric layer 314 and the passivation layer 312 stops at the metal pad 310 of the bottom wafer 304, that leads to the formation of a patterned area 314A.

Now, referring to FIG. 3B, at step 302D, a landing metal layer 316 is deposited over the patterned area 314A as well as over the dielectric layer 314. The landing metal layer 316 is formed from one of, or contains one or more of CMP treatable metals, such as tungsten (W) , titanium (Ti) , tantalum (Ta) , chromium (Cr) , aluminium (Al) , platinum (Pt) , ruthenium (Ru) , cobalt (Co) , nickel (Ni) , and the like. The landing metal layer 316 is deposited by use of one of the physical vapour deposition (PVD) , electron beam (e-Beam) evaporation, chemical vapour deposition (CVD) , or atomic layer deposition (ALD) .

At step 302E, after deposition of the landing metal layer 316, the CMP of the landing metal layer 316 is realized to clear the excess metal of the landing metal layer 316 deposited in between the metal pad 310 of the bottom wafer 304. The CMP of the landing metal layer 316 leads to the formation of a landing pad 316A in the frontside 304B of the bottom wafer 304. The landing pad 316A is used for interconnection of multiple wafers in a stacked wafer assembly.

At step 302F, a bonding oxide layer 318 is deposited on the landing pad 316A of the bottom wafer 304. The bonding oxide layer 318 is generally composed of metallic oxides, such as silicon dioxide (SiO2) , silicon nitride (SiN) , silicon carbon nitride (SiCN) , silicon oxycarbon nitride (SiOCN) and the like. After deposition of the bonding oxide layer 318, the CMP of the bonding oxide layer 318 is realized to achieve a suitable roughness (e.g. an average roughness (Ra) less than 1 nanometer) of the bonding oxide layer 318.

FIGs. 4A and 4B collectively is an illustration that depicts steps of reliable landing metal deposition on a bottom wafer using a metal etching deposition process, in accordance with an embodiment of the present disclosure. FIGs. 4A and 4B are described in conjunction with elements from FIGs. 1, 2, 3A, and 3B. With reference to FIGs. 4A and 4B, there is shown a metal deposition process 400 that includes a cross-sectional view of the bottom wafer 304, which is subjected to reliable landing metal deposition using a metal etching deposition process.

In the FIGs. 4A and 4B, the cross-sectional view of the bottom wafer 304 includes the backside 304A and the frontside 304B. The backside 304A includes the substrate 306. The frontside 304B includes the plurality of layers such as the back end of the line (BEOL) 308, the metal pad 310, and the passivation layer 312. The metal deposition process 400 includes steps 402A to 402E (steps 402A-402C of the metal deposition process 400 are shown in FIG. 4A and steps 402D-402E are shown in FIG. 4B) .

With reference to FIG. 4A, at step 402A, the passivation layer 312 is deposited over the BEOL 308 of the frontside 304B of the bottom wafer 304.

At step 402B, the landing metal layer 316 is directly deposited on the frontside 304B of the bottom wafer 304. The metal etching deposition process is used when the metal of the landing metal layer 316 is not treatable with the CMP. Therefore, the landing metal layer 316 is directly deposited on the frontside 304B of the bottom wafer 304 without any oxide patterning. The landing metal layer 316 is deposited by use of one of the physical vapour deposition (PVD) , electron beam (e-Beam) evaporation, chemical vapour deposition (CVD) , or atomic layer deposition (ALD) . The landing metal layer 316 can be deposited on the frontside 304B of the bottom wafer 304 before or after a photoresist (PR) patterning. In this implementation, the landing metal layer 316 is deposited on the frontside 304B of the bottom wafer 304 before the PR patterning.

At step 402C, a photoresist (PR) material 404 is deposited on the landing metal layer 316 for the PR patterning. The PR material 404 is generally of two types, such as a positive PR material and a negative PR material. In a casee, if the PR material 404 is a positive PR material, then a particular region of the PR material 404 becomes soluble in a developer solution when exposed to the light (of a particular wavelength) , and an unexposed region of the PR material 404 remains insoluble (i.e. remains in a solid state) in the developer solution. In another case, if the PR material 404 is a negative PR material, then the particular region of the PR material 404 remain insoluble in the developer solution when exposed to the light, and the unexposed region of the PR material 404 becomes soluble in the developer solution. Thereafter, lithography (or photolithography) of the deposited PR material 404 is realized to etch the PR material 404 from a chosen surface of the landing metal layer 316 that further leads to the formation of the landing pad 316A. After the PR patterning, the excess metal of the landing metal layer 316 is removed from top edges of the frontside 304B either by using a wet chemistry (e.g. wet plasma etching) or a dry chemistry (e.g., dry plasma etching) . In a case, if neither the wet chemistry nor the dry chemistry is available for removal of the excess metal of the landing metal layer 316, then in such a case, the PR patterning (or lithography) is realized before the deposition of the landing metal layer 316 on the frontside 304B of the bottom wafer 304. An example of such kind of a case is described in detail, for example, in FIGs. 5A and 5B.

Now, referring to FIG. 4B, at step 402D, the landing pad 316A is embedded into a dielectric layer such as the dielectric layer 314. Further, the chemical mechanical polishing (CMP) of the dielectric layer 314 is performed to obtain a suitable roughness of the dielectric layer 314.

At step 402E, the bonding oxide layer 318 is deposited on the frontside 304B of the bottom wafer 304. Alternatively stated, the bonding oxide layer 318 is deposited on the landing pad 316A as well as on the dielectric layer 314. Further, the CMP of the bonding oxide layer 318 is performed to obtain a suitable roughness of the bonding oxide layer 318.

FIGs. 5A and 5B collectively is an illustration that depicts steps of reliable landing metal deposition on a bottom wafer using a lift-off deposition process, in accordance with an embodiment of the present disclosure. FIGs. 5A and 5B are described in conjunction with elements from FIGs. 1, 2, 3A, 3B, 4A, and 4B. With reference to FIGs. 5A and 5B, there is shown a metal deposition process 500 that includes a cross-sectional view of the bottom wafer 304, which is subjected to reliable landing metal deposition using a lift-off deposition process.

In the FIGs. 5A and 5B, the cross-sectional view of the bottom wafer 304 includes the backside 304A and the frontside 304B. The backside 304A includes the substrate 306. The frontside 304B includes the plurality of layers such as the back end of the line (BEOL) 308, the metal pad 310, and the passivation layer 312. The metal deposition process 500 includes steps 502A to 502E (steps 502A-502C of the metal deposition process 500 are shown in FIG. 5A and steps 502D-502E are shown in FIG. 5B) .

With reference to FIG. 5A, at step 502A, the passivation layer 312 is deposited over the BEOL 308 of the frontside 304B of the bottom wafer 304.. In the lift-off deposition process, the photoresist (PR) material 404 is deposited before the deposition of the landing metal layer 316 on the frontside 304B of the bottom wafer 304.

At step 502B, the photoresist (PR) material 404 is initially deposited over the frontside 304B of the bottom wafer 304, thereafter lithography is realized to remove the PR material 404 from a selected portion of the frontside 304B of the bottom wafer 304, that results in a PR patterned area 404A.

At step 502C, the passivation layer 312 is removed from the PR patterned area 404A from the frontside 304B of the bottom wafer 304 by use of dry etching. Thereafter, the landing metal layer 316 is deposited in the PR patterned area 404A and also on the active area of the PR material 404 (i.e. on top of the PR material 404) .

Now, referring to FIG. 5B, at step 502D, a solvent or a stripper or any other chemical is used that removes excess metal of the landing metal layer 316 as well as dissolves the PR material 404 deposited below the landing metal layer 316 from top edges of the frontside 304B of the bottom wafer 304 and this process is named as the lift-off process. The removal of excess metal of the landing metal layer 316 from top edges of the frontside 304B leads to the formation of the landing pad 316A in the frontside 304B of the bottom wafer 304. Thereafter, the landing pad 316A is embedded into a dielectric layer such as the dielectric layer 314. Further, the chemical mechanical polishing (CMP) of the dielectric layer 314 is performed to obtain a suitable roughness of the dielectric layer 314.

At step 502E, the bonding oxide layer 318 is deposited on the frontside 304B of the bottom wafer 304. Alternatively stated, the bonding oxide layer 318 is deposited on the landing pad 316A as well as on the dielectric layer 314. Further, the CMP of the bonding oxide layer 318 is performed to obtain a suitable roughness of the bonding oxide layer 318.

FIG. 6 is an illustration that depicts steps of manufacturing a top wafer, in accordance with an embodiment of the present disclosure. FIG. 6 is described in conjunction with elements from FIGs. 1 and 2. With reference to FIG. 6, there is shown a manufacturing process 600 that includes a cross-sectional view of a top wafer 604. The top wafer 604 represents another single wafer of a stacked wafer assembly.

In the FIG. 6, the cross-sectional view of the top wafer 604 includes a backside 604A and a frontside 604B. The backside 604A includes a substrate 606. The frontside 604B includes a plurality of layers such as a back end of the line (BEOL) 608, a metal pad 610, and a passivation layer 612. The manufacturing process 600 includes steps 602A to 602C. The substrate 606 of the backside 604A of the top wafer 604 corresponds to the substrate 306 of the backside 304A of the bottom wafer 304 (of FIGs. 3A and 3B) . Similarly, the back end of line (BEOL) 608, the metal pad 610, and the passivation layer 612 of the frontside 604B of the top wafer 604 corresponds to the back end of line (BEOL) 308, the metal pad 310, and the passivation layer 312 of the frontside 304B of the bottom wafer 304 (of FIGs. 3A and 3B) , respectively.

At step 602A, the passivation layer 612 is deposited over the BEOL 608 of the frontside 604B of the bottom wafer 604.

At step 602B, a temporary carrier wafer 614 is bonded on the frontside 604B of the top wafer 604. Thereafter, grinding of the backside 604A of the top wafer 604 is carried out to thin down the substrate 606 of the backside 604A of the top wafer 604.

At step 602C, after thinning down the substrate 606 of the backside 604A of the top wafer 604, the CMP of the backside 604A of the top wafer 604 is carried out to achieve a suitable roughness of the backside 604A of the top wafer 604. After then, a bonding oxide layer 616 is deposited on the backside 604A of the top wafer 604. Examples of the bonding oxide layer 616 include, but are not limited to, a silicon dioxide (SiO2) layer, a silicon nitride (SiN) layer, a silicon carbon nitride (SiCN) layer, a silicon oxycarbon nitride (SiOCN) layer and the like. In an implementation, the bonding oxide layer 616 may also be referred as a dielectric bonding layer. After deposition of the bonding oxide layer 616 the CMP of the bonding oxide layer 616 is realized to achieve a suitable roughness (e.g. average roughness (Ra) ) of the bonding oxide layer 616. The roughness of the bonding oxide layer 616 deposited on the backside 604A of the top wafer 604 is considered same as that of the roughness of the bonding oxide layer 318 deposited on the frontside 304B of the bottom wafer 304 (e.g. the bottom wafer 304 of FIGs. 3A, 3B, 4A, 4B, 5A, and 5B) .

FIGs. 7A-7E collectively is an illustration that depicts steps of forming one or more TSV in a stacked wafer assembly, in accordance with an embodiment of the present disclosure. FIGs. 7A-7E are described in conjunction with elements from FIGs. 1, 2, 3A, 3B, 4A, 4B, 5A, 5B, and 6. With reference to FIGs. 7A-7E, there is shown a cross-sectional view of a stacked wafer assembly 700 which is subjected to one or more TSV formation.

In the FIGs. 7A-7B, the cross-sectional view of the stacked wafer assembly 700 includes the bottom wafer 304 and the top wafer 604. The one or more TSV are formed in the stacked wafer assembly 700 in steps 702A to 702I (

steps

702A and 702B of the one or more TSV formation in the stacked wafer assembly 700 are shown in FIG. 7A, steps 702C and 702D are shown in FIG. 7B, steps 702E and 702F are shown in FIG. 7C, steps 702G and 702H are shown in FIG. 7D, and step 702I is shown in FIG. 7E) .

With reference to FIG. 7A, at step 702A, the top wafer 604 and the bottom wafer 304 are bonded together by use of a back-to-face (B2F) wafer bonding technology. In the B2F wafer bonding technology, the backside 604A of the top wafer is bonded on the frontside 304B of the bottom wafer 304. In this implementation, the bonding oxide layer 318 (of FIGs. 3A and 3B) deposited on the frontside 304B of the bottom wafer 304 is termed as a first dielectric layer and the bonding oxide layer 616 (of FIG. 6) deposited on the backside 604A of the top wafer 604 termed as a second dielectric layer. In the B2F bonding of the top wafer 604 and the bottom wafer 304, the first dielectric layer of the bottom wafer 304 and the second dielectric layer of the top wafer 604 are bonded together and hence, results into formation of a dielectric bonding layer 704 between the top wafer 604 and the bottom wafer 304. Examples of the dielectric bonding layer 704 include, but are not limited to, a silicon dioxide (SiO2) layer, silicon nitride (SiN) layer, silicon carbon nitride (SiCN) layer, silicon oxycarbon nitride (SiOCN) layer, etc.

At step 702B, annealing of the bonded top wafer 604 and the bottom wafer 304 is carried out to strengthen the bonding of the top wafer 604 and the bottom wafer 304. Moreover, the temporary carrier wafer 614 is removed from the frontside 604B of the top wafer 604.

Now, referring to FIG. 7B, at step 702C, a thick oxide layer 706 (e.g. a silicon dioxide (SiO2) layer) is deposited on the frontside 604B of the top wafer 604. Thereafter, a photoresist (PR) material 708 is also deposited on the thick oxide layer 706. Further, the PR material 708 is exposed to light for PR patterning. The expose of the PR material 708 to light causes removal of the PR material 708 as well as the thick oxide layer 706 from a selected portion of the frontside 604B of the top wafer 604 and leads to the formation of a PR patterned area 708A on the frontside 604B of the top wafer 604.

At step 702D, an opening 710 (or a TSV) is formed in the PR patterned area 708A of the frontside 604B of the top wafer 604. The opening 710 is formed by etching of the passivation layer 612, the BEOL 608 and the substrate 606 of the top wafer 604 from the frontside 604B. The opening 710 includes a lateral inner surface 712A and a bottom inner surface 712B. The lateral inner surface 712A extends from the frontside 604B of the top wafer 604 to the bottom inner surface 712B. The lateral inner surface 712A of the opening 710 may also be referred to as an inner wall (or a vertical inner surface) of the opening 710. The bottom inner surface 712B of the opening 710 is an upper surface of a portion of the dielectric bonding layer 704 arranged in between the top wafer 604 and the bottom wafer 304. The etching of the substrate 606 of the top wafer 604 is stopped at the dielectric bonding layer 704, therefore, the opening 710 is formed upto the dielectric bonding layer 704.

Now, referring to FIG. 7C, at step 702E, an electrically non-conductive material 714 (e.g., a single lining of an oxide, or an oxide liner) is clad on the lateral inner surface 712A and the bottom inner surface 712B of the opening 710 (i.e. the TSV) . The thickness of the electrically non-conductive material 714 (i.e. the oxide liner) may range up to 200 nanometer (nm) . In an implementation, such a small thickness of the electrically non- conductive material 714 (i.e. the oxide liner) is deposited by use of one of the processes, such as chemical vapor deposition (CVD) , plasma-enhanced chemical vapor deposition (PECVD) , sub-atmospheric chemical vapour deposition (SACVD) , laser ablation deposition (LAD) , dual ion beam sputtering deposition (DIBSD) , atomic layer deposition (ALD) (or low-temperature atomic layer deposition (ALD) , and the like. Beneficially, in comparison with the conventional double oxide liner, the electrically non-conductive material 714 (i.e. the oxide liner) relaxes the step coverage constrains related to the conventional double oxide liner and the conventional embedded barrier.

At step 702F, a protective layer 716 (e.g. a silicon nitride (SiN) layer) is deposited on top edges of the opening 710 at the frontside 604B of the top wafer 604 by use of the chemical vapor deposition (CVD) , or plasma-enhanced chemical vapor deposition (PECVD) and the like. The protective layer 716 is deposited to protect top edges of the electrically non-conductive material 714 (i.e. the oxide liner) of the opening 710 during etching of the dielectric bonding layer 704, and the electrically non-conductive material 714 from the bottom inner surface 712B of the opening 710.

Now, referring to FIG. 7D, at step 702G, the opening 710 is extended to the landing pad 316A amongst one or more metal pads at the frontside 304B of the bottom wafer 304. The opening 710 is extended by etching of the electrically non-conductive material 714 that has been clad onto the lateral inner surface 712A and on the bottom inner surface 712B of the opening 710, along with the portion of the dielectric bonding layer 704 that lies beneath the bottom inner surface 712B of the opening 710. Therefore, after etching, an extended opening 710A is formed. The extended opening 710A stops at the landing pad 316A of the frontside 304B of the bottom wafer 304. The metal of the landing pad 316A manifests a low sputter rate and therefore, provides low metal resputtering and hence, low diffusion into the substrate 606 of the top wafer 604.

At step 702H, a metal 718 (e.g. Cu) is filled within the extended opening 710A to form a metallic connection. The bottom up filling of the extended opening 710A with the metal 718 (i.e. Cu) is achieved by use of the ECD process. The metal 718 (i.e. Cu) of the metallic connection manifests a higher sputter rate (in atoms/ion) than the sputter rate of the metal of the landing pad 316A. Therefore, the metal 718 of the metallic connection is different from the metal of the landing pad 316A. For example, the metal 718 of the metallic connection is either a copper (Cu) metal, a gold (Au) metal, or a silver (Ag) metal. The metal of the landing pad 316A is one of, or contains one or more of, W, Ti, Ta, Cr, Al, Pt, Ta, Ru, Co, Ni metals. Additionally, before filling the extended opening 710A with the metal 718 includes deposition of a metal diffusion barrier and a metal seed layer. The metal diffusion barrier is a thin layer of a metal, and formed either of titanium (Ti) metal, or titanium nitride (TiN) metal alloy, or tantalum nitride (TaN) metal alloy, or tantalum (Ta) metal, and the like. The metal diffusion barrier is deposited in order to minimize the diffusion of metal 718 (e.g., copper diffusion) into the substrate 606 (e.g. silicon substrate) of the top wafer 604. Similarly, the metal seed layer is a thin layer of metal (e.g., copper (Cu) ) , which is deposited for electrical conduction within the extended opening 710A (i.e. the TSV) . The metal diffusion barrier and the metal seed layer are deposited by using one of the processes such as, physical vapor deposition (PVD) , atomic layer deposition (ALD) , dual ion beam sputtering (DIBS) , electrochemical deposition (ECD) , and metal sintering. Optionally, a seed repair step comprising an alkaline electro chemical deposition (ECD) or electroless deposition (ELD) of the metal seed layer (e.g. Cu seed layer) may be realized to restore the discontinuities of the metal seed layer (i.e. Cu seed layer) , where the ELD is an auto-catalytic technique, which is generally used to deposit a metal (or to deposit high-resolution metal patterns) on different wafers (or substrates) . After bottom up filling of the extended opening 710A with the metal 718 (i.e. Cu) , the CMP of the metal 718 (i.e. Cu) is realized to obtain a suitable roughness of the metal 718 (i.e. Cu) .

Now, referring to FIG. 7E, at step 702I, a redistribution layer (RDL) 720 is deposited using the damascene metal process, described in detail, for example, in FIGs 3A and 3B. The RDL 720 includes a metal pad 722 and a landing pad 724, which are used for interconnection between the top wafer 604 and the bottom wafer 304 in the stacked wafer assembly 700. The landing pad 724 is formed on the top of the metal pad 722 of the RDL 720. The landing pad 724 and the metal pad 722 of the RDL 720 are further connected with the metal 718 (i.e. Cu) of the extended opening 710A, to form the metallic connection between the landing pad 724 of the RDL of the top wafer 604, and the landing pad 316A of the bottom wafer 304. The metal pad 722 of the RDL 720 is formed with the same metal as the metal of the metal pad 310 of the bottom wafer 304, and the metal pad 610 of the top wafer 604. Similarly, the metal of the landing pad 724 of the RDL 720 of the top wafer 604 is same as the metal of the landing pad 316A of the bottom wafer 304. In this way, the top wafer 604 and the bottom wafer 304 are interconnected through the metal 718 of the extended opening 710A (also termed as the TSV) in the stacked wafer assembly 700 by avoiding the Cu resputtering and diffusion of the resputtered Cu into the substrate 606 of the backside 604A of the top wafer 604. Similar to the top wafer 604 and the bottom wafer 304, another wafer or a plurality of wafers may be interconnected through the metal 718 of the extended opening 710A (also termed as the TSV) in the stacked wafer assembly 700.

Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including" , "comprising" , "incorporating" , "have" , "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration" . Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments" . It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.

Claims

A method (100) of forming a Through-Substrate-Via TSV in a stacked wafer assembly (700) , the stacked wafer assembly (700) comprising a bottom wafer (304) and a top wafer (604) , each of the bottom wafer (304) and the top wafer (604) comprising a backside (304A, 604A) and a frontside (304B, 604B) , the backside (304A, 604A) comprising a substrate (306, 606) , the frontside (304B, 604B) being located above the backside (304A, 604A) and comprising a plurality of layers formed above the substrate (306, 606) and comprising a top layer, the top layer of the plurality of layers of the frontside (304B) of the bottom wafer (304) comprising one or more metal pads (310) and being bonded to the substrate (606) of the top wafer (604) through a dielectric bonding layer (704) , the method (100) comprising:

forming an opening (710) from a surface of the top layer of the plurality of layers of the frontside (604B) of the top wafer (604) to the dielectric bonding layer (704) , through the substrate (606) of the backside (604A) of the top wafer (604) , the opening (710) having an inner surface,

cladding the inner surface of the opening (710) with an electrically non-conductive material (714) ,

extending the opening (710) to a landing pad (316A) amongst the metal pads (310) in the top layer of the plurality of layers of the frontside (304B) of the bottom wafer (304) , through the electrically non-conductive material (714) that has been clad onto the inner surface of the opening (710) and through the dielectric bonding layer (704) ,

filling the extended opening (710A) with a metal (718) so as to form a metallic connection between the landing pad (316A) in the top layer of the plurality of layers of the frontside (304B) of the bottom wafer (304) and a landing pad (724) in the top layer of the plurality of layers of the frontside (604B) of the top wafer (604) , the metal (718) of the metallic connection being different from the metal of the landing pad (316A, 724) .
The method (100) according to claim 1, wherein a sputter rate, in atoms/ion, of the metal (718) of the metallic connection is higher than the sputter rate, in atoms/ion, of the metal of the landing pad (316A, 724) .
The method (100) according to any of claims 1 and 2, wherein the metal (718) of the metallic connection is Cu, or Au, or Ag, and the metal of the landing pad (316A, 724) is one of, or contains one or more of, W, Ti, Ta, Cr, Al, Pt, Ta, Ru, Co, Ni.
The method (100) according to any of claims 1 to 4, wherein the inner surface of the opening (710) comprises a lateral inner surface (712A) and a bottom inner surface (712B) , the lateral inner surface (712A) extending from the surface of the top layer of the top wafer (604) to the bottom inner surface (712B) and the bottom inner surface (712B) being an upper surface of a portion of the dielectric bonding layer (704) .
The method (100) according to claim 4, wherein cladding the inner surface of the opening (710) comprises cladding the lateral inner surface (712A) and the bottom inner surface (712B) of the opening (710) .
The method (100) according to any of claims 1 to 5, wherein forming the opening (710) comprises patterning and etching.
The method (100) according to any of claims 1 to 6, wherein cladding the inner surface of the opening (710) comprises oxide chemical vapour deposition, plasma enhanced chemical vapour deposition, sub-atmospheric chemical vapour deposition, laser ablation deposition, dual ion beam sputtering deposition or atomic layer deposition.
The method (100) according to any of claims 1 to 7, wherein extending the opening (710) comprises etching.
The method (100) according to claim 8, wherein, before extending the opening (710) by etching, a protective layer (716) is deposited, preferably by chemical vapor deposition or physical vapor deposition of a SiN layer, on the edges of the single-lined opening at surface of the top layer of the top wafer (604) .
The method (100) according to any of claims 1 to 9, wherein filling the extended opening (710A) with metal (718) so as to form a metallic connection comprises depositing a metal diffusion barrier and a metal seed layer by physical vapor deposition or atomic layer deposition or dual ion beam sputtering, and then by electrochemical deposition and metal sintering.
A method (200) of forming a stacked wafer assembly (700) with one or more Through-Substrate-Via TSV, the stacked wafer assembly (700) comprising a bottom wafer (304) and a top wafer (604) , each of the bottom wafer (304) and the top wafer (604) comprising a backside (304A, 604A) and a frontside (304B, 604B) , the backside (304A, 604A) comprising a substrate (306, 606) , the frontside (304B, 604B) being located above the backside (304A, 604A) and comprising a plurality of layers formed above the substrate (306, 606) and comprising a top layer, the top layer of the bottom wafer (304) comprising one or more metal pads (310) , the method (200) comprising:

depositing a first dielectric layer on the top layer of the bottom wafer (304) and a second dielectric layer under the substrate (606) of the top wafer (604) ,

bonding the first and the second dielectric layers together so as to bond the backside (604A) of the top wafer (604) on the frontside (304B) of the bottom wafer (304) , and

forming one or more TSV according to the method (100) of any of claims 1 to 10, from a surface of the top layer of the top wafer (604) to one or more landing pads (316A) amongst the metal pads (310) of the top layer of the bottom wafer (304) .
The method (200) according to claim 11, further comprising, before depositing the first and second dielectric layers and bonding them together, forming the landing pad (316A) by depositing a landing metal layer (316) in the top layer of the bottom wafer (304) .
The method (200) according to claim 12, wherein forming the landing pad (316A) comprises depositing the landing metal layer (316) on top of an existing metal pad (310) formed in the same metal as the metal (718) of the metallic connection.
The method (200) according to any of claims 12 and 13, wherein depositing the landing metal layer (316) comprises a damascene deposition process using chemical mechanical polishing.
The method (200) according to any of claims 12 and 13, wherein forming the landing pad (316A) comprises a semi-additive metal patterning process.
The method (200) according to claim 15, wherein forming the landing pad (316A) comprises a metal etching deposition process.
The method (200) according to claim 15, wherein forming the landing pad (316A) comprises a lift-off deposition process.
The method (200) according to any of claims 11 to 17, further comprising forming a redistribution layer (720) on the top layer of the top wafer (604) , said redistribution layer (720) comprising one or more metal pads (722) , one or more of these metal pads (722) being connected with the metallic connection in the opening (710) .
The method (200) according to claim 18, the top layer of the top wafer (604) comprising one or more metal pads (610) , one or more of these metal pads (610) being connected with the one or more metal pads (722) of the redistribution layer (720) connected with the metallic connection in the opening (710) .
The method (200) according to any of claims 18 and 19, further comprising forming a landing pad (724) , in the same metal as the metal of the landing pad (316A) in the top layer of the bottom wafer (304) , on top of the one or more metal pads (722) of the redistribution layer (720) connected with the metallic connection in the opening (710) .