CN100356822C - 电路装置及其制造方法 - Google Patents
电路装置及其制造方法 Download PDFInfo
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- CN100356822C CN100356822C CNB2005100558019A CN200510055801A CN100356822C CN 100356822 C CN100356822 C CN 100356822C CN B2005100558019 A CNB2005100558019 A CN B2005100558019A CN 200510055801 A CN200510055801 A CN 200510055801A CN 100356822 C CN100356822 C CN 100356822C
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- conductive pattern
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- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
- H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
Abstract
一种电路装置及其制造方法,成本低,导电图案的位置精度高。本实施例的电路装置的制造方法包括:准备导电箔(10)的工序;通过在导电箔(10)的表面形成分离槽(12),将导电图案(13)形成凸状的工序;利用树脂膜(15)覆盖导电箔(10)的表面,将覆盖分离槽(12)的树脂膜(15)的厚度形成得比覆盖导电图案(13)上面的树脂膜(15)的厚度厚的工序;通过除去树脂膜(15),使所述导电图案的上面从树脂膜(15)露出的工序;电连接从树脂膜(15)露出的导电图案(13)和电路元件的工序;形成密封树脂(20),以密封电路元件的工序;除去导电箔(10)的背面直至将导电图案(13)相互之间分离的工序。
Description
技术领域
本发明涉及电路装置及其制造方法,特别是涉及可提高导电图案的露出部的位置精度的电路装置及其制造方法。
背景技术
目前,由于置于电子设备中的电路装置在手机、笔记本电脑等中使用,而要求小型化、薄型化及轻量化。
例如,以半导体装置为例说明电路装置,最近,正在开发称为CSP(芯片尺寸封装)的、和芯片的尺寸同等大小的电路装置。
但是,通常的CSP将玻璃环氧树脂衬底作为插装件(インタ-ポ-ザ)使用,这阻碍了CSP的小型化及薄型化。为解决该问题,本申请人开发了图13和图14所示的不需要安装衬底的电路装置的制造方法(例如参照专利文献1)。
参照图13及图14说明所述的电路装置的制造方法。参照图13(A),准备导电箔110,在其表面上将抗蚀膜111构图为规定的形状。然后,参照图13(B),通过进行半蚀刻,在导电箔110的表面形成分离槽112。然后,如图13(C)所示,在将抗蚀膜111剥离后,在导电箔的表面涂敷树脂膜115。然后,参照图13(D),在导电图案113的表面形成开口部130。该开口部130的形成可通过激光或刻蚀工艺等除去方法进行。在此,考虑形成开口部130时的误差,开口部130的周边部和导电图案113的周边部以规定的距离α分开。
参照图14(A),将半导体元件116及片状元件117电连接在导电图案113上后,进行密封树脂120的形成。接着,参照图14(B),通过除去导电箔110的背面,将各导电图案113电分离。然后,参照图14(C),在导电图案113的背面形成外部电极121,形成被覆树脂122。利用以上的工序可形成现有型的电路装置。
专利文献1:特开2003-155591号公报
但是,上述的电路装置及其制造方法具有以下这样的问题。
参照图13(D),由于进行了考虑形成开口部130时的误差的冗长设计,导电图案113的平面大小很大,形成所需尺寸以上的大小。这导致了电路装置整体的大型化。另外,为在正确的位置形成开口部130,需要精度高的昂贵的曝光机及激光照射器。这导致制造成本提高。
另外,由于在树脂膜130的开口部形成有用于粘接片状元件117等的粘接剂,故粘接剂的形状形成峰腰状的形状。这阻碍了应对热应力的可靠性。
发明内容
本发明是鉴于所述问题点而开发的,本发明的主要目的在于,提供一种低成本且导电图案的位置精度高的电路装置及其制造方法。
本发明的电路装置具有如下特征,其包括:导电图案;电路元件,其与所述导电图案电连接;树脂膜,其形成于所述导电图案相互之间,覆盖所述导电图案的侧面;粘接剂,其具有导电性,并且与所述导电图案的上面及侧面接触,将所述电路元件和所述导电图案固定;密封树脂,其密封所述电路元件。
本发明的电路装置具有如下特征,所述粘接剂是导电性或绝缘性粘接剂。
本发明的电路装置具有如下特征,所述粘接剂的侧面描绘成圆滑的曲面。
本发明的电路装置具有如下特征,所述导电图案具有多层配线结构。
另外,本发明的电路装置具有如下特征,所述电路元件是利用倒装法安装的半导体元件。
本发明电路装置的制造方法具有如下特征,其包括:构成导电图案的工序;覆盖所述导电图案形成树脂膜的工序;从所述树脂膜露出所述导电图案的上面及自所述上面连续的侧面的一部分的工序;通过与所述导电图案的上面及自所述上面连续的侧面的一部分接触的粘接剂将电路元件电连接到所述导电图案上的工序;通过密封树脂覆盖所述电路元件的工序。
本发明电路装置的制造方法具有如下特征,其包括:准备导电箔的工序;通过在所述导电箔的表面形成分离槽,将导电图案形成凸状的工序;利用树脂膜覆盖所述导电箔的表面,使覆盖所述分离槽的所述树脂膜的厚度形成得比覆盖所述导电图案的上面的所述树脂膜厚的工序;通过除去所述树脂膜,使所述导电图案的上面及自所述上面连续的侧面的一部分从所述树脂膜露出的工序;通过与从所述树脂膜露出的导电图案的上面及自所述上面连续的侧面的一部分接触的粘接剂将电路元件电连接到所述导电图案上的工序;密封所述电路元件形成密封树脂的工序;除去所述导电箔的背面直至使所述导电图案相互之间分离的工序。
本发明电路装置的制造方法具有如下特征,通过均匀地蚀刻所述树脂膜,使所述导电图案的上面及侧面的一部分从所述树脂膜露出。
本发明电路装置的制造方法具有如下特征,所述电路元件包括利用倒装法安装的半导体元件。
本发明电路装置的制造方法具有如下特征,所述导电图案的背面构成外部电极。
本发明电路装置的制造方法具有如下特征,在进行所述树脂膜的曝光后,除去所述树脂膜。
本发明电路装置的制造方法具有如下特征,所述树脂膜的形成通过将薄膜状的所述树脂利用真空压力机层积在所述导电箔上来进行。
本发明电路装置的制造方法具有如下特征,所述树脂膜的形成通过在所述导电箔的表面涂敷液状或半固体状的树脂来进行。
另外,本发明电路装置的制造方法具有如下特征,除去所述树脂膜直至所述导电图案的侧面部分地露出。
根据本发明的电路装置,由于可将粘接剂的侧面形成圆滑的曲面形状,故可提高该粘接剂相对热应力的可靠性。
根据本发明电路装置的制造方法,可省去现有这样的露出部的形成,使导电图案部分地露出。因此,可迅速提高露出的部分的导电图案的位置精度。另外,可不使用曝光机或激光照射器,使导电图案部分地露出。由此,可减低电路装置的制造成本。
附图说明
图1(A)-(C)是说明本发明电路装置的制造方法的剖面图;
图2(A)-(C)是说明本发明电路装置的制造方法的剖面图;
图3(A)-(B)是说明本发明电路装置的制造方法的剖面图;
图4(A)-(B)是说明本发明电路装置的制造方法的剖面图;
图5(A)-(C)是说明本发明电路装置的制造方法的剖面图;
图6(A)-(D)是说明本发明电路装置的制造方法的剖面图;
图7(A)-(C)是说明本发明电路装置的制造方法的剖面图;
图8(A)是利用本发明电路装置的制造方法制造的电路装置之一例的平面图,图8(B)是其剖面图;
图9(A)-(D)是说明本发明电路装置的制造方法的剖面图;
图10(A)-(D)是说明本发明电路装置的制造方法的剖面图;
图11(A)-(B)是说明本发明电路装置的制造方法的剖面图;
图12(A)-(C)是说明本发明电路装置的制造方法的剖面图;
图13(A)-(D)是说明现有电路装置的制造方法的剖面图;
图14(A)-(C)是说明现有电路装置的制造方法的剖面图。
符号说明
9 电路装置
10 导电箔
11 抗蚀剂
12 分离槽
13 导电图案
14 树脂片
15 树脂膜
16 半导体元件
17 片状元件
18 焊料
19 金属细线
20 密封树脂
具体实施方式
第一实施例
参照图1~图5说明本实施例的电路装置的制造方法。本实施例的电路装置的制造方法包括:准备导电箔10的工序;通过在导电箔10的表面形成分离槽12,将导电图案13形成凸状的工序;利用树脂膜15覆盖导电箔10的表面,使覆盖分离槽12的树脂膜15的厚度形成得比覆盖导电图案13的上面的树脂膜15厚的工序;通过除去树脂膜15,使所述导电图案的上面从树脂膜15露出的工序;电连接从树脂膜15露出的导电图案13和电路元件的工序;形成密封电路元件的密封树脂20的工序;除去导电箔19的背面直至使导电图案13相互之间分离的工序。下面,作为所述电路元件之一例采用半导体元件16和片状元件17的组合。下面详细叙述这样的各工序。
如图1所示,本实施例的第一工序是准备导电箔10,通过在导电箔10的表面形成分离槽12凸状形成导电图案13。
在本工序中,首先,如图1(A),准备片状的导电箔10。该导电箔10考虑焊料的粘附性、接合性、镀敷性选择其材料。例如,采用以Cu为主材料的导电箔、以Al为主材料的导电箔或由Fe-Ni等合金构成的导电箔等。导电箔的厚度考虑之后的蚀刻优选10μm~300μm左右。
然后,在导电箔10的表面形成耐蚀刻掩膜即抗蚀膜11。然后,对抗蚀膜11构图,使除去作为导电图案13的区域外的导电箔10露出。
参照图1(B),提高进行蚀刻形成分离槽12。利用蚀刻形成的分离槽12的深度例如为50μm,由于其侧面形成粗糙面,故之后的工序中密封树脂20或树脂膜15的粘接性提高。在此使用的蚀刻剂主要采用氯化铁或氯化铜,导电箔10被浸渍于该蚀刻剂中,或利用该蚀刻剂喷射。在此,由于湿式蚀刻通常被各向异性蚀刻,故侧面形成弯曲结构。另外,参照图1(C),结束蚀刻后,将抗蚀膜11剥离除去。
本实施例的第二工序如图2所示,利用树脂膜15将导电箔10的表面覆盖,使覆盖分离槽12的树脂膜15的厚度形成得比覆盖导电图案13上面的树脂膜15的厚度厚。
在导电箔10的表面形成树脂膜15的方法可考虑两个方法。第一方法是通过使片状的树脂片14附着在导电箔10的表面,形成树脂膜15的方法。第二方法是在导电箔10的表面涂敷液状或半固体状树脂材料后,通过使该树脂材料硬化形成树脂膜15的方法。任何一方法都可以形成树脂膜15,在此,说明使用树脂片14的方法。
参照图2(A),在导电箔10的表面压装树脂片14。具体地说,通过从上下方向加压交替层积的导电箔10和树脂片14,使两者粘附。该粘附可以通过在接近真空的氛围气下进行加压的真空加压来进行。另外,也可以在树脂15的形成结束后,通过进行曝光或加热进行树脂的硬化或稳定化。
参照图2(B)说明利用所述方法在其表面形成树脂膜15的导电箔10的剖面。在此,分离槽12也包括在内的导电箔10表面的实质上整个区域被树脂膜15覆盖。
参照图2(C),详细说明形成的树脂膜15。形成于分离槽12的位置的树脂膜15的厚度形成得比覆盖导电图案13的上面的树脂膜15厚。另外,也可以使覆盖分离槽12下部的树脂膜15的厚度形成得比覆盖分离槽12上部的树脂膜15厚。无论是上述的使用树脂片13的方法还是使用液状树脂材料的方法,都可以加厚形成于分离槽12的位置的树脂膜15。在使用树脂片13的树脂膜15的形成方法中,通过对树脂片14加压,使树脂片集中在分离槽12的位置,来加厚覆盖分离槽12的树脂膜15。另外,在使用液状树脂材料的方法中,通过使树脂材料优先到达分离槽12的位置,将覆盖分离槽12的树脂膜15加厚。
本实施例的第三工序在于,通过除去树脂膜15,使所述导电图案13的上面从树脂膜15露出。
具体地说,参照图3(A),通过实质上整面除去形成于导电箔10表面的树脂膜15,使导电图案13的上面从树脂膜15露出。在此,不使用激光或刻蚀工艺,通过进行整面的树脂膜15的蚀刻,使导电图案13的上面从树脂膜15露出。如上所述,覆盖导电图案13上面的树脂膜15形成得比覆盖分离槽12的树脂膜15薄。因此,在不使用掩膜同样进行树脂膜15的蚀刻时,树脂膜15形成得薄的导电图案13的上面优选露出。在本实施例中,在导电图案13的上面露出的蚀刻,停止树脂膜15的蚀刻。由此,可使分离槽12的区域残留有树脂膜15,而导电图案13的上面从树脂膜15露出。蚀刻树脂膜15的蚀刻剂采用与树脂膜15进行化学反应,而不与导电箔10的材料反应的化学药品。具体地说,可采用强碱性药品作为该蚀刻剂。
参照图3(B)说明露出导电图案13后的剖面。也可以通过进行树脂膜1 5的蚀刻,使导电图案13上面露出,同时,分离槽12的上部侧面也从树脂膜15露出。这样,通过进行蚀刻,直至分离槽12的上部侧面从树脂膜15露出,即使在进行蚀刻时存在误差,也可以可靠地露出导电图案13上面。
本实施例的第四工序在于,如图4所示,将从树脂膜15露出的导电图案13和电路元件电连接。
参照图4(A),在此,作为电路元件之一例,采用半导体元件16和片状元件17。半导体元件16介有焊料18固定在导电图案13的上面,并介由金属细线19将半导体元件16和导电图案13电连接。片状元件17两端的电极介由焊料18固定在导电图案13上。在此,电路元件可全部采用无源元件和有源元件。另外,可采用树脂密封型封装或CSP作为电路元件。
参照图4(B)说明介由焊料18连接的片状元件17的安装结构。形成焊料18,使其覆盖导电图案13的上面及侧面的一部分。另外,焊料18的侧面呈现连续圆滑的曲面。与现有例相比,由于没有图13(D)所示的开口部130那样的台阶状,故本实施例的焊料18的侧面形状圆滑地形成。通过圆滑地形成焊料18的侧面,可提高焊料18相对于热应力的强度。另外,焊料18部分地覆盖导电图案13的侧面部,故可提高焊料18和导电图案13的连接强度。另外,由于分离槽12被树脂膜15覆盖,故可抑止焊料18过度地扩散导致的导电图案13相互之间的短路。
本实施例的第五工序在于,如图5所示,形成密封树脂20,使其密封电路元件,除去导电箔10的背面直至导电图案13相互之间分离。
参照图5(A),密封树脂20覆盖电路元件及多个导电图案13,在导电图案13间的分离槽12内填充密封树脂12。而且,密封树脂20支承导电图案13。本工序可通过传递膜模制、注入膜模制或浸渍实现。作为树脂材料,环氧树脂等热硬性树脂可通过传递膜模制实现,聚酰亚胺树脂、聚苯亚硫酸酯等热塑性树脂可通过注入膜模制实现。
本工序的优点是,在覆盖密封树脂20之前,构成导电图案13的导电箔10形成支承衬底。目前,采用本来不需要的支承衬底形成导电路,但在本实施例中,作为支承衬底的导电箔10是作为导电材料必要的材料。因此,具有可极其节省构成材料而操作的优点,也可以降低成本。
参照图5(B),除去导电箔10的背面直至填充于分离槽12内的密封树脂20露出,进行各导电图案13的分离。本工序是化学及/或物理地除去导电箔10的背面,分离为导电图案13的工序。该工序通过研磨、研削、蚀刻、激光的金属蒸发等进行。
参照图5(C),利用被覆树脂22覆盖从密封树脂20露出的导电图案13的背面,在所希望的位置形成外部电极21。另外,通过沿切割线23切割形成矩阵状的各电路装置边界部的密封树脂20,分割成各个电路装置。经由上述工序制造本实施例的电路装置。
第二实施例
在本实施例中,参照图6和图7说明采用面朝下的半导体元件作为内装的电路元件时的电路装置的制造方法。由于本实施例电路装置的基本制造方法和所述的第一实施例的方法相同,故以不同点为中心进行以下的说明。
首先,参照图6(A)及图6(B),通过在导电箔10的表面形成分离槽12,使导电图案13构成凸状。在此,导电图案13主要形成和通过面朝下接合法配置的元件连接的连接焊盘。在分离槽12的形成结束后,将抗蚀膜11剥离。
其次,参照图6(C),在导电箔10的表面形成树脂膜15,通过蚀刻树脂膜15,使导电图案13的上面从树脂膜15露出。该方法的详细操作和第一实施例相同。
其次,参照如6(D),通过面朝下接合法配置半导体元件24。半导体元件的电极和导电图案13介由焊料18电连接。在此,由于焊锡18的侧面也构成连续圆滑的曲面,故焊料18的相对于热应力的强度较强。如上所述,由于导电图案13的位置精度非常高,故也可以对应具有微细间距的多个端子的半导体元件24。也可以在半导体元件24的固定结束后,在半导体元件24的下方填充由树脂构成的不充满(アンダ-フイル)材料。另外,参照图7(A),利用密封树脂20进行半导体元件24的覆盖。
其次,参照图7(B),除去导电箔10的背面直至使各导电图案13分离。在此,在导电箔10的背面选择性地形成抗蚀膜25,进行蚀刻。利用本工序的蚀刻分离的导电图案13的背面露出面形成附着用于安装电路装置的焊料的电极。因此,露出到装置外部的导电图案13的下面的面积比从树脂膜15露出的导电图案13上面的面积大。
其次,参照图7(C),利用被覆树脂22部分覆盖在背面露出的导电图案13,在导电图案13的背面形成由焊料构成的外部电极21。通过以上的工序制造内装由面朝下接合法配置的半导体元件24的电路装置。
第三实施例
本实施例是上述实施例可制造的电路装置之一例。图8(A)是电路装置9的平面图,图8(B)是其剖面图。在该图所示的电路装置9中内装有多个电路元件,各电路元件通过金属细线19或导电图案13电连接。
导电图案13构成埋入密封树脂20内但使背面露出的结构,其通过分离槽12电分离。在露出到外部的导电图案13的背面设有由焊锡等焊料构成的外部电极21。另外,装置背面未设置外部电极21的位置利用被覆树脂22覆盖。
参照图8(A)进一步说明导电图案13的平面形状。在同图中,实线表示导电图案的上面13A,虚线表示导电图案的下面13B。导电图案的上面13A形成安装电路元件的小片焊盘的区域和金属细线连接的接合焊盘的区域。如上所述,本中请的导电图案13的位置精度非常高。因此,可防止导电图案13的平面位置偏移导致的导电图案13相互之间的短路。
电路元件采用半导体元件16及片状元件17。这些电路元件被固定在由导电图案13构成的岛上。
密封树脂20使导电图案13的背面露出,覆盖电路元件、金属细线19及导电图案13。密封树脂20可全部采用热硬性树脂或热塑性树脂。另外,在分离各导电图案13的分离槽12内填充有密封树脂20。本实施例的电路装置10A整体被密封树脂20支承。
在本实施例中,可使导电图案的上面13A和导电图案的下面13B的平面形状不同。因此,可在一个导电图案13上形成多个导电图案的上面13A。由此,可将更复杂的电路装入电路装置9内。
第四实施例
本实施例中说明具有多层配线结构的电路装置的结构及制造方法。在本实施例中省去使用曝光掩膜的曝光工序,进行导电图案的露出。下面详细说明各工序。
本实施例的第一工序在于,如图9(A)所示,准备在绝缘树脂42上粘接第一导电膜40和第二导电膜41的绝缘树脂片。
绝缘树脂片的表面实质上在整个区域形成第一导电膜40,背面也实质上在整个区域形成第二导电膜41。绝缘树脂42的材料是由聚酰亚胺树脂或环氧树脂等高分子构成的绝缘材料。另外,第一导电膜40及第二导电膜41最好是以Cu为主材料的材料或公知的引线架的材料,可利用镀敷法、蒸镀法或喷溅法覆盖在绝缘树脂42上,也可以粘贴利用辊轧法或镀敷法形成的金属箔。
绝缘树脂片可以通过模铸法形成。下面简单说明其制造方法。首先,在平膜状的第一导电膜40上涂敷糊状的聚酰亚胺树脂,另外,在平膜状的第二导电膜41上也涂敷糊状的聚酰亚胺树脂。然后,在使两者的聚酰亚胺树脂半硬化后进行粘贴,即构成绝缘树脂片。
绝缘树脂42优选聚酰亚胺树脂或环氧树脂等。在涂敷膏状的物质构成片的铸造法的情况下,其膜厚为10μm~100μm程度。另外,在作为片形成时,市售的膜厚最小为25μm。另外,考虑到导热性,也可以向其中混入填充物。
本实施例的第二工序在于,如图9(B)及图9(C)所示,在绝缘树脂片的所希望的位置,在第一导电膜40及绝缘树脂42上形成通孔52,选择性地露出第二导电膜41。
首先,如图9(B)所示,在第一导电箔40的表面整面涂敷抗蚀剂50后,进行构图,部分地露出第一导电箔40。具体地说,进行抗蚀剂50的构图,使电连接两个导电箔的部分露出。
然后,如图9(C)所示,介由该抗蚀剂50蚀刻第一导电膜40。由于第一导电膜40是以Cu为主材料的膜,故蚀刻液使用氯化铁或氯化铜进行化学蚀刻。通孔52的开口直径根据光刻法的图像分辨率变化,但在此为50~100μm。
其次,参照图9(D),在清除抗蚀剂50后,以第一导电膜40为掩膜,利用激光清除通孔52正下方的绝缘树脂42,在通孔52的底部露出第二导电膜41的背面。激光优选使用二氧化碳激光。另外,在利用激光使绝缘树脂蒸发后,在开口部的底部具有残渣的情况下,利用过锰酸钠或过硫酸铵等进行湿式蚀刻,清除该残渣。
本实施例的第三工序在于,如图10(A)所示,在通孔52内形成连接装置46,将第一导电膜40和第二导电膜41电连接。
在包括通孔52的第一导电膜40的整个面上形成进行第二导电膜41和第一导电膜40的电连接的连接装置46即镀敷膜。该镀敷膜通过无电解镀敷和电镀两者形成,在此利用无电解镀敷至少在含有通孔52的第一导电膜40的整个面上形成约2μm的Cu。由此,为了使第一导电膜40和第二导电膜41电导通,再次将第一及第二导电膜40、41作为电极进行电镀,镀敷约20μm的Cu。由此,通孔52内埋入Cu,形成连接装置46。
本实施例的第四工序在于,如图10(B)~图10(D)所示,将第一导电膜40及第二导电膜41蚀刻成所希望的图案,形成第一导电图案43及第二导电图案44。
第一导电膜40上及第二导电膜41的表面利用所希望图案的光致抗蚀剂50覆盖,利用化学蚀刻进行构图。由于导电膜是以Cu为主材料的膜,故蚀刻液最好使用氯化铁或氯化铜。
本实施例的第五工序在于,参照图11,在由树脂膜48覆盖第一导电图案43后,使第一导电图案43的表面从树脂膜43露出。
首先,参照图11(A),形成树脂膜48,以覆盖第一导电图案43。该树脂膜48的形成可通过液化状态的树脂膜的涂敷或片状的树脂膜的层积进行。在通过层积进行树脂膜48的形成时,可使用与参照图2说明的方法相同的方法进行。在本实施例中,覆盖第一导电图案43上面的树脂膜48的厚度也比直接覆盖绝缘树脂42的树脂膜48的厚度薄。
其次,参照图11(B),通过将树脂膜48的表面整面地进行蚀刻,使第一导电图案43的上面露出。在本工序中,由于不使用曝光掩膜地进行树脂膜48的蚀刻,故可使用省去曝光的简化方法使图案的上面露出。另外,由于是省去了曝光掩膜的方法,故可无视该掩膜的对位精度而进行整体的设计。因此,可提高图案密度。另外,为使第一导电图案43的上面可靠地露出,也可以进行树脂膜48的蚀刻直至第一导电图案43的侧面部分地露出。
本发明的第六工序在于,如图12所示,进行电路元件45的固定,进一步进行其密封。
首先,参照图12(A),在第一导电图案43上固定电路元件45。在此,在第一图案43的表面固定电路元件,根据需要,利用金属细线19进行电连接。电路元件45可全部采用有源元件及无源元件。
其次,参照图12(B),利用密封树脂47进行密封,以覆盖电路元件45及金属细线19。另外,如图12(C)所示,进行从背面露出的第二导电图案44的背面处理。具体地说,利用被覆树脂22覆盖除形成外部电极53的位置之外的区域。然后,形成外部电极53,完成具有多层配线的电路装置。
Claims (12)
1、一种电路装置,其特征在于,包括:导电图案;电路元件,其与所述导电图案电连接;树脂膜,其形成于所述导电图案相互之间,覆盖所述导电图案的侧面;粘接剂,其具有导电性,并且与所述导电图案的上面及侧面接触,将所述电路元件和所述导电图案固定;密封树脂,其密封所述电路元件。
2、如权利要求1所述的电路装置,其特征在于,所述粘接剂的侧面描绘成圆滑的曲面。
3、如权利要求1所述的电路装置,其特征在于,所述导电图案具有多层的配线结构。
4、如权利要求1所述的电路装置,其特征在于,所述电路元件是利用倒装法安装的半导体元件。
5、一种电路装置的制造方法,其特征在于,包括:构成导电图案的工序;覆盖所述导电图案形成树脂膜的工序;从所述树脂膜露出所述导电图案的上面及自所述上面连续的侧面的一部分的工序;通过与所述导电图案的上面及自所述上面连续的侧面的一部分接触的粘接剂将电路元件电连接到所述导电图案上的工序;通过密封树脂覆盖所述电路元件的工序。
6、一种电路装置的制造方法,其特征在于,包括:准备导电箔的工序;通过在所述导电箔的表面形成分离槽,将导电图案形成凸状的工序;利用树脂膜覆盖所述导电箔的表面,使覆盖所述分离槽的所述树脂膜的厚度形成得比覆盖所述导电图案的上面的所述树脂膜厚的工序;通过除去所述树脂膜,使所述导电图案的上面及自所述上面连续的侧面的一部分从所述树脂膜露出的工序;通过与从所述树脂膜露出的导电图案的上面及自所述上面连续的侧面的一部分接触的粘接剂将电路元件电连接到所述导电图案上的工序;密封所述电路元件形成密封树脂的工序;除去所述导电箔的背面直至使所述导电图案相互之间分离的工序。
7、如权利要求5或权利要求6所述的电路装置的制造方法,其特征在于,通过均匀地蚀刻所述树脂膜,使所述导电图案的上面及侧面的一部分从所述树脂膜露出。
8、如权利要求5或权利要求6所述的电路装置的制造方法,其特征在于,所述电路元件包括利用倒装法安装的半导体元件。
9、如权利要求6所述的电路装置的制造方法,其特征在于,所述导电图案的背面构成外部电极。
10、如权利要求5或权利要求6所述的电路装置的制造方法,其特征在于,进行所述树脂膜的曝光后,除去所述树脂膜。
11、如权利要求5或权利要求6所述的电路装置的制造方法,其特征在于,所述树脂膜的形成通过将薄膜状的所述树脂膜利用真空加压层积在所述导电箔上来进行。
12、如权利要求5或权利要求6所述的电路装置的制造方法,其特征在于,所述树脂膜的形成通过在所述导电箔的表面涂敷液状或半固体状的树脂来进行。
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- 2005-03-16 CN CNB2005100558019A patent/CN100356822C/zh not_active Expired - Fee Related
- 2005-03-17 KR KR1020050022175A patent/KR100613791B1/ko not_active IP Right Cessation
- 2005-03-21 US US11/085,287 patent/US7329957B2/en not_active Expired - Fee Related
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CN1325136A (zh) * | 2000-05-24 | 2001-12-05 | 三洋电机株式会社 | 板状体和半导体器件的制造方法 |
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CN106469687A (zh) * | 2015-08-20 | 2017-03-01 | 爱思开海力士有限公司 | 具有嵌入式电路图案的封装基板其制造方法及半导体封装 |
Also Published As
Publication number | Publication date |
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KR100613791B1 (ko) | 2006-08-22 |
CN1674758A (zh) | 2005-09-28 |
KR20060043743A (ko) | 2006-05-15 |
US7329957B2 (en) | 2008-02-12 |
JP4446772B2 (ja) | 2010-04-07 |
TW200536441A (en) | 2005-11-01 |
JP2005277001A (ja) | 2005-10-06 |
US20050214981A1 (en) | 2005-09-29 |
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