CN1341963A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1341963A
CN1341963A CN01104552A CN01104552A CN1341963A CN 1341963 A CN1341963 A CN 1341963A CN 01104552 A CN01104552 A CN 01104552A CN 01104552 A CN01104552 A CN 01104552A CN 1341963 A CN1341963 A CN 1341963A
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mentioned
semiconductor element
welding zone
electrode
semiconductor device
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CN1266765C (zh
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坂本则明
小林义幸
阪本纯次
冈田幸夫
五十岚优助
前原荣寿
高桥幸嗣
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

以印刷电路板、陶瓷板、软性板等作为支持基板装配半导体元件的BGA型的半导体装置。但这些支持基板是多余的,支持基板的厚度使半导体装置大型化,并使组装到其中的半导体元件难于放热。本发明通过将导电图形11A~11D埋入到绝缘性树脂10中而且导电箔20进行半蚀刻后而形成,使其厚度充分薄。由于设置了放热用的电极11D,可提供放热性能优异的半导体装置。

Description

半导体装置及其制造方法
本发明涉及半导体装置及其制造方法,特别是可以很好地使半导体元件散热的半导体装置及其制造方法。
近年来,随着IC组件在便携式设备及小型而高密度装配设备中的应用,现有的IC组件及其装配概念发生了很大的变化。详细情况,在例如电子材料(1998年9月号22页~)的特集“CSP技术及支持它的安装材料和装置”中进行了介绍。
图10是采用软性板50作为插入板的图,在该软性板50上,通过粘接剂粘贴铜箔图形51,并进而固定IC芯片52。并且,作为该导电图形51,有在该IC芯片52的周围形成的焊接用的焊区53。另外,通过与该焊接用的焊区53一体地形成的配线51B形成焊锡球连接用的焊区54。
并且,在焊锡球连接用的焊区54的背面设置软性板开口的开口部56,通过该开口部56形成焊锡球55。并且,以软性板50作为基板,全部用绝缘性树脂58进行密封。
但是,设置在IC芯片52的背面的软性板50的价格非常昂贵,存在成本高、组件的厚度大、重量增加的问题。
另外,支持基板由金属以外的材料构成,所以,存在从IC芯片背面向组件的背面传热的热阻大的问题。作为上述支持基板,是软性板、陶瓷板或印刷电路板。另外,由热传导良好的材料构成的热传导通路是金属细线57、铜箔图形51和焊锡球55,是在驱动时不能充分放热的结构。因此,在驱动时,IC芯片的温度将上升,从而不能充分流过驱动电流。
本发明就是鉴于上述问题而提出的,第1,本发明是通过具有与半导体元件的焊接电极对应地设置的焊区、设置在上述半导体元件的配置区域中的放热用的电极、通过倒装与上述焊区电气连接的上述半导体元件、至少设置在上述半导体元件的下面的底层填料和露出上述焊区的背面和上述底层填料的背面而一体化地封装上述半导体元件的绝缘性树脂来解决上述问题的。
第2,本发明是通过具有与半导体元件的焊接电极对应地设置的焊区、设置在半导体元件的配置区域中的放热用的电极、通过倒装与上述焊区电气连接的上述半导体元件和至少设置在上述半导体元件的下面并露出上述焊区的背面而一体化地进行封装的底层填料来解决上述问题的。
第3,上述底层填料上溢到半导体元件的侧面,填充到相邻的上述焊区之间的分离沟和上述焊区与上述放热用的电极之间的分离沟中。
第4,本发明是通过具有与半导体元件的焊接电极对应地设置的焊区、设置在与上述焊区一体的配线上的外部连接电极、由上述外部连接电极包围而设置的放热用的电极、通过倒装与上述焊区电气连接的上述半导体元件、至少设置在上述半导体元件的下面的底层填料和露出上述外部连接电极的背面和上述底层填料的背面而一体化地封装上述半导体元件的绝缘性树脂来解决上述问题的。
第5,本发明是通过具有与半导体元件的焊接电极对应地设置的焊区、设置在与上述焊区一体的配线上的外部连接电极、由上述外部连接电极包围而设置的放热用的电极、通过倒装与上述焊区电气连接的上述半导体元件和至少设置在上述半导体元件的下面并露出上述外部连接电极的背面而一体化地封装的底层填料来解决上述问题的。
第6,上述底层填料上溢到半导体元件的侧面,填充到相邻的上述焊区之间的分离沟、相邻的上述配线之间的分离沟、上述外部连接电极与上述放热用的电极之间的分离沟中。
第7,连接上述半导体元件和上述焊区的连接手段,是焊料、导电胶或各向异性导电性树脂。
第8,上述焊区的侧面是弯曲结构。
第9,上述焊区、与上述焊区一体的配线、与上述配线一体的外部连接电极的侧面是弯曲结构。
第10,准备导电箔,半蚀刻为导电图形形成凸起状,通过倒装将上述导电图形与半导体元件连接,至少将底层填料浸入到上述半导体元件和上述导电箔之间,在上述导电箔上设置绝缘性树脂用以封装上述半导体元件和上述导电图形,露出上述底层填料的背面,并除去上述导电箔的背面,用以分离出导电图形。
第11,准备导电箔,半蚀刻为导电图形形成凸起状,通过倒装将上述导电图形与半导体元件连接,至少将底层填料浸入到上述半导体元件和上述导电箔之间,露出上述底层填料的背面,并除去上述导电箔的背面,用以分离出导电图形。
第12,在将上述导电图形分离后,进行切割分离。
第13,在上述导电箔上,作为1个单元的导电图形形成为矩阵状,而上述半导体元件设置到各个单元上。
第14,在将上述导电图形分离后,通过切割将上述单元与上述单元之间分离。
通过提供本半导体装置,可以将半导体元件的热向一个放热用的电极传导。另外,包含该放热用的电极的导电图形,不采用支持基板就可以形成,所以,可以降低成本,使半导体装置的厚度变薄。
图1是说明本发明的半导体装置的图。
图2是说明本发明的半导体装置的制造方法的图。
图3是说明本发明的半导体装置的制造方法的图。
图4是说明本发明的半导体装置的制造方法的图。
图5是说明本发明的半导体装置的制造方法的图。
图6是说明本发明的半导体装置的制造方法的图。
图7是说明本发明的半导体装置的图。
图8是说明本发明的半导体装置中采用的导电图形的图。
图9是说明本发明的半导体装置的图。
图10是说明现有的半导体装置的图。
实施例1.
下面,先参照图1说明本发明的半导体装置。图1A是半导体装置的平面图,图1B是沿A-A线的剖面图。
在图1中,绝缘性树脂10中埋入了以下的结构要素。即,埋入了焊区11A…、与该焊区11A…一体的配线11B、与配线11B一体地形成的设置在该配线11B的另一端的外部连接电极11C。此外,还埋入了设置在由该导电图形11A~11C包围的一个区域中的放热用的电极11D和设置在该放热用的电极11D之上的半导体元件12。半导体元件12通过底层填料AF与上述放热用的电极11D固定,在图1A中,用虚线表示。
另外,半导体元件12的焊接电极13和焊区11A通过倒装来装配半导体元件12,所以,通过焊锡等焊料SD、Ag胶等导电胶、各向异性导电性树脂进行电气连接。
另外,上述导电图形11A~11D的侧面,以非各向异性进行蚀刻,这里,是通过湿腐蚀形成的,所以,具有弯曲结构,利用该弯曲结构,产生制动效果。
本结构由半导体元件12、多个导电图形11A~11C、放热用的电极11D、底层填料AF、将它们埋入的绝缘性树脂10等4种材料构成。特别是在半导体元件12的配置区域中,在导电图形11A~11D上和它们之间的分离沟14中,形成上述底层填料AF,特别是在露出填充到分离沟14中的底层填料AF的背面的状态用绝缘性树脂10进行封装,形成组件。并且,利用绝缘性树脂10或底层填料AF支持上述焊区11A…、半导体元件12。
作为底层填料AF,由可以浸透到窄的间隙中的绝缘材料构成,最好是如图4所示所示的那样能够上溢到半导体元件12的侧面上的材料。另外,也可以在半导体元件12的背面薄薄地形成底层填料AF,而用绝缘性树脂10将其封装。
另一方面,根据后面所述的制造方法(图7)可知,作为半导体装置,也可以在半导体元件12的背面形成底层填料AF,而省略绝缘性树脂10。
另外,作为绝缘性树脂,可以使用环氧树脂等热硬化树脂、聚酰亚铵树脂、硫化聚苯等热可塑性树脂。另外,如果绝缘性树脂是使用模具固化的树脂、浸渍成形树脂、可以进行涂布而被覆的树脂,就可以采用所有的树脂。
另外,作为导电图形11A~11D,可以使用以Cu为主材料的导电箔、以Al为主材料的导电箔、或Fe-Ni合金、Al-Cu的集层体、Al-Cu-Al的集层体等。当然,也可以使用其他导电材料,特别是可以进行蚀刻的导电材料、通过激光而蒸发的导电料则更好。另外,若考虑半蚀刻性、电镀的形成性和热应力时,则最好是以通过轧制而形成的Cu为主材料的导电材料。
在本发明中,在图1B中绝缘性树脂10和底层填料AF填充在上述分离沟15中,而在图7中是底层填料AF填充到上述分离沟15中,所以,具有可以防止导电图形脱落的特征。另外,作为蚀刻,通过采用干腐蚀或湿腐蚀进行非各向异性的蚀刻,使焊区11A…的侧面、配线11B…的侧面、外部连接电极11C…的侧面、放热用的电极11D的侧面成为弯曲结构,从而也可以产生制动效果。结果,便可实现导电图形11A~11D不会从绝缘性树脂10中脱落的结构。
而且,导电图形11A~11D的背面从绝缘性树脂10的背面露出。在图1B中,虽然形成了绝缘被覆膜16,但是,也可以省略该绝缘被覆膜16,而直接将放热用的电极11D的背面和装配基板上的电极固定。利用该结构,从半导体元件12产生的热可以向装配基板上的电极放热,可以防止半导体元件12的温度上升,从而可以增大半导体元件12的驱动电流。另外,放热用的电极11C和半导体元件12也可以进行电气连接。
本半导体装置由作为封装树脂的绝缘性树脂10支持导电图形11A~11D,所以,不需要支持基板。该结构是本发明的特征。如在先有技术部分说明的那样,现有的半导体装置的导电路由支持基板(软性板、印刷电路板或陶瓷板)支持,或者由引线框支持,所以,附加了本来并不需要的结构。但是,本电路装置由所需最小限度的结构要素构成,不需要支持基板,所以,具有薄型、轻量而且不需要材料费的廉价的特征。
另外,组件的背面露出导电图形11A~11D。若在该区域被覆例如焊锡等焊料,由于放热用的电极11D的面积大,所以,焊料将增厚。于是,固定到装配基板上时,外部连接电极11C背面的焊料将涂不到装配基板上的电极上,从而将会发生焊接不良的情况。
为了解决这个问题,在半导体装置15的背面形成绝缘被覆膜16。在图1A中所示的虚线O,就表示从绝缘被覆膜16露出的外部连接电极11C…、放热用的电极11D。即,在该O以外,由绝缘被覆膜16所覆盖,O的部分的尺寸实际上是同一尺寸,所以,在该处形成的焊料的厚度实际上是相同的。这在焊锡印刷后和反流焊接后也是一样的。另外,使用Ag、Ag-Pd等导电胶也可以说是一样的。利用该结构,可以抑制电气的连接不良现象。另外,放热用的电极11D的露出部17,考虑到半导体元件的放热性,也可以形成为比外部连接电极11C的露出尺寸大。另外,外部连接电极11C…实际上全部是相同的尺寸,所以,外部连接电极11C…可以在整个区域露出,而放热用的电极11D的背面的一部分以实际上相同的尺寸从绝缘被覆膜16露出。
另外,通过设置绝缘被覆膜16,设置在装配基板上的配线可以延伸到本半导体装置的背面。通常,设置在装配基板侧的配线在上述半导体装置的固定区域迂回配置,但是,利用上述绝缘被覆膜16的形成,就可以不迂回进行配置。而且,绝缘性树脂10和底层填料AF比导电图形突出,所以,可以在装配基板侧的配线与导电图形之间形成间隙,从而可以防止发生短路。
实施例2.
本制造方法是表示图1的半导体装置15的制造方法,图2~图6是与图1A的A-A线对应的剖面图。
首先,如图2那样,准备导电箔20。厚度最好为10μm~300μm,这里,采用70μm的轧制铜箔。然后,在该导电箔20的表面,作为耐腐蚀掩膜,形成导电被覆膜21或感光性树脂。该图形是和图1A的焊区11A…、配线11B…、外部连接电极11C…、放热用的电极11D…相同的图形。另外,采用感光性树脂取代导电被覆膜21时,在感光性树脂的下层,在至少与焊区对应的部分形成Au、Ag、Pd或Ni等的导电被覆膜。这样,就可以防止Cu氧化和进行焊料的焊接(以上,参见图2)。
然后,通过上述导电被覆膜21或感光性树脂,对导电箔20进行半蚀刻。蚀刻的深度只要比导电箔20的厚度浅就行。蚀刻的深度越浅,越可以形成微细的图形。
并且,通过进行半蚀刻,导电图形11A~11D在导电箔20的表面将以凸起状出现。如前所述,导电箔20采用以轧制形成的Cu为主材料的Cu箔。但是,也可以是由Al构成的导电箔、由Fe-Ni合金构成的导电箔、Cu-Al的集层体、Al-Cu-Al的集层体。特别是Al-Cu-Al的集层体可以防止由于热膨胀系数的差别而发生的翘起。另外,可以使用轧制的铜箔。轧制的铜箔在X轴、Y轴方向的结晶的成长比Z轴方向大,耐弯曲性强。特别是配线11B形成得很长时,施加到该配线上的应力就增大,但是,通过采用该轧制的铜箔,便可提高对上述应力的耐性。(以上,参见图3)。
并且,焊接电极13和焊区11A配置为面对面,通过例如焊料SD进行固定。
例如,准备设置了焊锡球的半导体元件12,在焊区11A上涂布由焊料构成的导电胶。该导电胶在烧结前的粘性可以临时粘接半导体元件12。并且,以该临时粘接的状态投入到炉内,焊料熔融后将半导体元件12和焊区电气连接。
另一方面,在由焊料材料构成一定的间隙的部分,形成底层填料AF。该底层填料AF是容易浸入到半导体元件12与导电图形之间的间隙中的材料,另外,通过控制它的量,形成到半导体元件12的侧面或半导体元件的背面。该底层填料AF,考虑与绝缘性树脂10的粘接性和与导电图形的粘接性来进行选择。
因此,底层填料AF设置到放热用的电极11D与外部连接电极11C的分离沟14、由焊区11A~外部连接电极11C构成的导电图形之间的分离沟14中和这些分离沟之上。不使用以上支持基板就可以装配半导体元件,半导体元件12的高度通过倒装,配置得比较低。因此,可以使后面所述的组件外形的厚度变薄。(以上,参见图4)
并且,形成绝缘性树脂10,用以覆盖通过半蚀刻而形成的导电图形11A~11D…、半导体元件12和金属细线14。作为绝缘性树脂,可以是热可塑性和热硬化性树脂中的任何一种。
另外,可以通过转移模塑、注入模塑、浸渍法或涂布法而实现。作为树脂材料,环氧树脂等热硬化性树脂可以通过转移模塑而实现,液晶聚合物、硫化聚苯等热可塑性树脂可以通过注入模塑而实现。
在本实施例中,绝缘性树脂的厚度调整为从金属细线14的顶部开始在其上被覆约100μm。考虑半导体装置的强度,该厚度可厚可薄。
在树脂注入中,导电图形11A~11D与薄片状的导电箔20成为一体,所以,只要导电箔20没有偏离,导电图形11A~11D的位置就完全不会发生错位。
形成为凸起状的导电图形11A~11D和半导体元件12埋入到绝缘性树脂10和底层填料AF中,在凸起部下方的导电箔20从背面露出(以上,参见图5)。
然后,去除在上述绝缘性树脂10的背面露出的导电箔20,将导电图形11A~11D一个一个地分离。
这里的分离工序,可以考虑各种各样的方法,可以通过蚀刻去除背面而进行分离,或通过研磨、切削等进行分离。另外,也可以两种方法都采用。例如,利用切削使绝缘性树脂10露出时,导电箔20的切削渣或薄薄地延伸到外侧的金属毛刺将可能侵入到绝缘性树脂10或底层填料AF中。因此,如果利用蚀刻将焊区11…分离,在位于导电图形11A~11D之间的绝缘性树脂10或底层填料AF的表面就可以形成不会嵌入金属的导电箔20。这样,便可防止微细间隔的导电图形11A~11D之间发生短路。
另外,在形成多个成为半导体装置15的1个单元时,在该分离工序之后,增加切割工序。
这里,是采用切割装置将它们一个一个地分离的,但是,也可以利用分割、冲压或剪切进行分离。
这里,在分离表面露出的导电图形11A~11D上形成绝缘被覆膜16,在绝缘被覆膜16上刻制图形,用以露出由图1A的虚线的圆圈所示的部分。并且,在此之后,在由箭头所示的部分进行切割,形成半导体装置。
焊锡21可以在切割之前形成,也可以在切割之后形成。
利用以上的制造方法,可以实现导电图形和半导体元件埋入到绝缘性树脂中的轻、薄而短小的组件。
图7是图1的改良后的半导体装置,省略了绝缘性树脂10。在图4的工序中,为了形成底层填料AF,涂布到半导体元件12的背面,在固化之后,省略绝缘性树脂10的形成,而进行切割。在图7中,可以使半导体元件12的背面露出。另外,平面图和图1A相同,所以省略了。
本发明在所有的实施例中,都形成了防止流动膜,以使焊料SD不会流动。例如,以焊锡为例,如图1B所示,在导电图形11A~11C的至少一部分形成防止流动膜DM,用以阻止焊锡的流动。作为防止流动膜,是与焊锡的侵润性差的膜,例如高分子膜或在Ni膜之上形成的氧化膜等。
另外,防止流动膜的平面形状示于图8。由于图面的关系,省略了放热用的电极。
在图8中,形成了A~E的5个图形,但是,可以选择其中的一种。A所示的图形,防止流动膜DM设置在焊区11A与配线11B的分界处,实际上在焊区11A的整个区域中形成电气连接的手段。另外,也可以在配线11B的整个区域或包含外部连接电极11C形成防止流动膜DM。B是在焊区形成防止流动膜DM后除去了设置电气连接手段的部分的类型。C是除了类型B的形成区域外,在配线11B和外部连接电极11C也形成防止流动膜DM的类型。D是类型C的开口部从矩形变为圆形的类型。此外,E是在焊区上形成环状的防止流动膜DM的类型。焊区11A这里表示为矩形,但是,也可以是圆形。该防止流动膜DM用于防止焊锡等焊料、Ag胶等导电胶以及导电性树脂的流动,是对这些电气连接手段侵润性差的材料。例如,焊锡设为类型D时,在焊锡熔化时由防止流动膜DM进行阻止,从而由于表面张力而形成漂亮的半球。另外,附上该焊锡的半导体元件的焊接电极13的周围形成钝化膜,所以,只侵润焊接电极。因此,通过焊锡将半导体元件与焊区连接时,可以以圆柱状维持一定的高度进行固定。另外,该高度可以用焊锡的量来调整,所以,可以在半导体元件与导电图形之间设置一定的间隙,从而可以使清洗液浸入到其间。另外,也可以使底层填料AF这样的粘性低的粘接剂浸入。此外,通过在连接区域以外的全部区域用防止流动膜DM被覆,可以提高与绝缘性树脂10的粘接性。
下面,说明利用以上的制造方法而发生的效果。
首先,第1,导电图形进行半蚀刻,与导电箔成为一体而进行支持,所以,可以去掉以往支持用的基板。
第2,在导电箔上进行半蚀刻,形成凸起状的焊区,所以,可以实现焊区的微细化。因此,可以减小宽度和间隔,从而可以形成平面尺寸更小的组件。
第3,由于由导电图形、半导体元件、连接手段和封装材料构成,所以,可以用所需最小限度的要素构成,可以尽可能去掉不必要的材料,从而可以实现大幅度地抑制成本的薄型的半导体装置。
第4,焊区进行半蚀刻,形成凸起状,在封装后进行一个一个的分离,所以,不需要系杆和悬吊引线。因此,在本发明中,完全不需要形成系杆(悬吊引线)和切割系杆(悬吊引线)。
第5,成为凸起状的导电图形埋入到绝缘性树脂中后,从绝缘性树脂的背面除去导电箔,将导电图形分离,所以,可以去掉像现有的引线框那样在引线与引线之间发生的树脂缝脊。
第6,半导体元件通过底层填料与放热用的电极固定,该放热用的电极从背面露出,所以,可以从本半导体装置的背面有效地放出本半导体装置发生的热。此外,通过将Si氧化膜或氧化铝等填充物混入到绝缘性粘接物质中,可以进一步提高其放热性。另外,如果将填充物尺寸统一,可以使半导体元件12与导电图形的间隙保持一定。
实施例3.
图9表示本半导体装置40。图9 A是其平面图,图9B是沿A-A线的剖面图。
在图1中,在焊区11A上,配线11B和外部连接电极11C一体地形成,但是,这里,焊区11A的背面就成为外部连接电极。
另外,由于焊区11A的背面成为矩形,所以,从绝缘被覆膜16露出的图形也以和上述矩形相同的图形形成。另外,考虑底层填料AF的固定性,形成分离沟43,用以将放热用的电极11D分割为多个。
根据上述说明可知,在本发明中,即使不采用支持基板,形成岛状的导电图形通过具有厚度的导电箔(或导电箔)埋入到绝缘性粘接物质和绝缘性树脂中而构成。另外,位于半导体元件的背面的放热用的电极露出,所以,可以改善半导体元件的放热性。而且,由于不采用支持基板,所以,可以实现薄型而轻量的组件。
另外,由导电图形、半导体元件、底层填料和绝缘性树脂等所需最小限度的要素构成,成为没有资源浪费的电路装置。因此,直至完成半导体装置,没有多余的结构要素,从而可以实现能够大幅度地降低成本的半导体装置。

Claims (14)

1.一种半导体装置,其特征在于:具有与半导体元件的焊接电极对应地设置的焊区、设置在上述半导体元件的配置区域中的放热用的电极、通过倒装与上述焊区电气连接的上述半导体元件、至少设置在上述半导体元件的下面的底层填料和露出上述焊区的背面和上述底层填料的背面而一体化地封装上述半导体元件的绝缘性树脂。
2.一种半导体装置,其特征在于:具有与半导体元件的焊接电极对应地设置的焊区、设置在半导体元件的配置区域中的放热用的电极、通过倒装与上述焊区电气连接的上述半导体元件和至少设置在上述半导体元件的下面并露出上述焊区的背面而一体化地进行封装的底层填料。
3.按权利要求1或权利要求2所述的半导体装置,其特征在于:上述底层填料上溢到半导体元件的侧面,填充到相邻的上述焊区之间的分离沟和上述焊区与上述放热用的电极之间的分离沟中。
4.一种半导体装置,其特征在于:具有与半导体元件的焊接电极对应地设置的焊区、设置在与上述焊区一体的配线上的外部连接电极、由上述外部连接电极包围而设置的放热用的电极、通过倒装与上述焊区电气连接的上述半导体元件、至少设置在上述半导体元件的下面的底层填料和露出上述外部连接电极的背面和上述底层填料的背面而一体化地封装上述半导体元件的绝缘性树脂。
5.一种半导体装置,其特征在于:具有与半导体元件的焊接电极对应地设置的焊区、设置在与上述焊区一体的配线上的外部连接电极、由上述外部连接电极包围而设置的放热用的电极、通过倒装与上述焊区电气连接的上述半导体元件和至少设置在上述半导体元件的下面并露出上述外部连接电极的背面而一体化地封装的底层填料。
6.按权利要求5所述的半导体装置,其特征在于:上述底层填料上溢到半导体元件的侧面,填充到相邻的上述焊区之间的分离沟、相邻的上述配线之间的分离沟、上述外部连接电极与上述放热用的电极之间的分离沟中。
7.按权利要求1~权利要求6的任一权项所述的半导体装置,其特征在于:连接上述半导体元件和上述焊区的连接材料,是焊料、导电胶或各向异性导电性树脂。
8.按权利要求1~权利要求3的任一权项所述的半导体装置,其特征在于:上述焊区的侧面是弯曲结构。
9.按权利要求4~权利要求6的任一权项所述的半导体装置,其特征在于:上述焊区、与上述焊区一体的配线、与上述配线一体的外部连接电极的侧面是弯曲结构。
10.一种半导体装置的制造方法,其特征在于:准备导电箔,半蚀刻为导电图形形成凸起状,通过倒装将上述导电图形与半导体元件连接,至少将底层填料浸入到上述半导体元件和上述导电箔之间,在上述导电箔上设置绝缘性树脂用以封装上述半导体元件和上述导电图形,露出上述底层填料的背面,并除去上述导电箔的背面,用以分离出导电图形。
11.一种半导体装置的制造方法,其特征在于:准备导电箔,半蚀刻为导电图形形成凸起状,通过倒装将上述导电图形与半导体元件连接,至少将底层填料浸入到上述半导体元件和上述导电箔之间,露出上述底层填料的背面,并除去上述导电箔的背面,用以分离为导电图形。
12.按权利要求10或权利要求11所述的半导体装置的制造方法,其特征在于:在将上述导电图形分离后,进行切割分离。
13.按权利要求10或权利要求11所述的半导体装置的制造方法,其特征在于:在上述导电箔上,作为1个单元的导电图形形成为矩阵状,而上述半导体元件设置到各个单元上。
14.按权利要求13所述的半导体装置的制造方法,其特征在于:在将上述导电图形分离后,通过切割将上述单元与上述单元之间分离。
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1301044C (zh) * 2003-09-30 2007-02-14 三洋电机株式会社 电路装置
CN1331220C (zh) * 2002-04-11 2007-08-08 皇家飞利浦电子股份有限公司 制造电子器件的方法和电子器件
CN100338749C (zh) * 2002-04-11 2007-09-19 皇家飞利浦电子股份有限公司 电子器件的制造方法以及电子器件
CN100356822C (zh) * 2004-03-24 2007-12-19 三洋电机株式会社 电路装置及其制造方法
CN100378980C (zh) * 2003-09-11 2008-04-02 罗姆股份有限公司 半导体装置
CN101911271B (zh) * 2008-01-17 2012-05-30 株式会社村田制作所 电子部件
CN103682043A (zh) * 2013-11-28 2014-03-26 天津金玛光电有限公司 一种水平式led芯片的固晶方法及采用该方法制备的led光源
CN105161425A (zh) * 2015-07-30 2015-12-16 南通富士通微电子股份有限公司 半导体叠层封装方法
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6562671B2 (en) * 2000-09-22 2003-05-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device and manufacturing method thereof
JP2005522863A (ja) 2002-04-11 2005-07-28 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体デバイス及びその製造方法
CN1675967A (zh) * 2002-08-05 2005-09-28 皇家飞利浦电子股份有限公司 电子产品、主体及其制造方法
DE10240461A1 (de) * 2002-08-29 2004-03-11 Infineon Technologies Ag Universelles Gehäuse für ein elektronisches Bauteil mit Halbleiterchip und Verfahren zu seiner Herstellung
JP2004186362A (ja) * 2002-12-03 2004-07-02 Sanyo Electric Co Ltd 回路装置
JP4479209B2 (ja) * 2003-10-10 2010-06-09 パナソニック株式会社 電子回路装置およびその製造方法並びに電子回路装置の製造装置
DE102005007643A1 (de) * 2005-02-19 2006-08-31 Assa Abloy Identification Technology Group Ab Verfahren und Anordnung zum Kontaktieren von Halbleiterchips auf einem metallischen Substrat
DE102017106055B4 (de) * 2017-03-21 2021-04-08 Tdk Corporation Trägersubstrat für stressempflindliches Bauelement und Verfahren zur Herstellung

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5350947A (en) * 1991-11-12 1994-09-27 Nec Corporation Film carrier semiconductor device
US5677246A (en) * 1994-11-29 1997-10-14 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
JPH08335653A (ja) 1995-04-07 1996-12-17 Nitto Denko Corp 半導体装置およびその製法並びに上記半導体装置の製造に用いる半導体装置用テープキャリア
DE19532755C1 (de) 1995-09-05 1997-02-20 Siemens Ag Chipmodul, insbesondere für den Einbau in Chipkarten, und Verfahren zur Herstellung eines derartigen Chipmoduls
US5744383A (en) * 1995-11-17 1998-04-28 Altera Corporation Integrated circuit package fabrication method
JPH09260552A (ja) * 1996-03-22 1997-10-03 Nec Corp 半導体チップの実装構造
JPH09312355A (ja) * 1996-05-21 1997-12-02 Shinko Electric Ind Co Ltd 半導体装置とその製造方法
JPH10256417A (ja) 1997-03-07 1998-09-25 Citizen Watch Co Ltd 半導体パッケージの製造方法
JPH10335566A (ja) 1997-04-02 1998-12-18 Dainippon Printing Co Ltd 樹脂封止型半導体装置とそれに用いられる回路部材、および樹脂封止型半導体装置の製造方法
JPH10303336A (ja) 1997-04-30 1998-11-13 Nec Corp フリップチップ型半導体素子の樹脂封止構造
JPH11163024A (ja) 1997-11-28 1999-06-18 Sumitomo Metal Mining Co Ltd 半導体装置とこれを組み立てるためのリードフレーム、及び半導体装置の製造方法
JPH11186326A (ja) * 1997-12-24 1999-07-09 Shinko Electric Ind Co Ltd 半導体装置
JP3219043B2 (ja) * 1998-01-07 2001-10-15 日本電気株式会社 半導体装置のパッケージ方法および半導体装置
CN1134833C (zh) * 1998-09-30 2004-01-14 精工爱普生株式会社 半导体装置及其制造方法、电路基板和电子装置
JP3395164B2 (ja) * 1998-11-05 2003-04-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体装置
JP3436159B2 (ja) 1998-11-11 2003-08-11 松下電器産業株式会社 樹脂封止型半導体装置の製造方法
US6383846B1 (en) * 2000-03-20 2002-05-07 Chi-Chih Shen Method and apparatus for molding a flip chip semiconductor device

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CN1331220C (zh) * 2002-04-11 2007-08-08 皇家飞利浦电子股份有限公司 制造电子器件的方法和电子器件
CN100338749C (zh) * 2002-04-11 2007-09-19 皇家飞利浦电子股份有限公司 电子器件的制造方法以及电子器件
CN100378980C (zh) * 2003-09-11 2008-04-02 罗姆股份有限公司 半导体装置
CN1301044C (zh) * 2003-09-30 2007-02-14 三洋电机株式会社 电路装置
CN100356822C (zh) * 2004-03-24 2007-12-19 三洋电机株式会社 电路装置及其制造方法
CN101911271B (zh) * 2008-01-17 2012-05-30 株式会社村田制作所 电子部件
CN103682043A (zh) * 2013-11-28 2014-03-26 天津金玛光电有限公司 一种水平式led芯片的固晶方法及采用该方法制备的led光源
CN105161425A (zh) * 2015-07-30 2015-12-16 南通富士通微电子股份有限公司 半导体叠层封装方法
CN105161424A (zh) * 2015-07-30 2015-12-16 南通富士通微电子股份有限公司 半导体叠层封装方法

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US20020048828A1 (en) 2002-04-25
EP1187205A3 (en) 2004-06-23
TW511399B (en) 2002-11-21
CN1266765C (zh) 2006-07-26
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US6963126B2 (en) 2005-11-08

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