CN1489202A - 电子器件模块 - Google Patents

电子器件模块 Download PDF

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Publication number
CN1489202A
CN1489202A CNA031563430A CN03156343A CN1489202A CN 1489202 A CN1489202 A CN 1489202A CN A031563430 A CNA031563430 A CN A031563430A CN 03156343 A CN03156343 A CN 03156343A CN 1489202 A CN1489202 A CN 1489202A
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China
Prior art keywords
mentioned
conductor portion
semiconductor chip
circuit board
wiring
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CNA031563430A
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English (en)
Inventor
Զ�ٹⷼ
远藤光芳
平冈俊郎
֮
堀田康之
青木秀夫
向田秀子
山口直子
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Toshiba Corp
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Toshiba Corp
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Publication of CN1489202A publication Critical patent/CN1489202A/zh
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    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/185—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method by making a catalytic pattern by photo-imaging
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Abstract

本发明提供一种实现了电子器件的小型安装结构的电子器件模块。在具有布线基板和与该布线基板一体化的电子器件的模块中，布线基板具有多孔质绝缘性基板，以及由选择性地导入该绝缘性基板的多孔质组织内的导电材料所形成的导体布线。

Description

电子器件模块
技术领域
本发明涉及一种使半导体芯片等电子器件与布线基板一体化的电子器件模块。
背景技术
为了便携式信息仪器等的高性能化，需要用于将电子器件高密度集成的小型轻量、薄型的封装或模块。例如在半导体封装中，作为半导体芯片端子为窄间距情况下的理想的连接法，TAB连接或倒装连接等正在被实用。
图8示出按照以往的倒装芯片连接的封装结构。在半导体芯片1、布线基板2的任意一方或两方的端子电极上预先形成Au或者焊锡构成的凸点4。配置半导体芯片1，使其端子焊盘向下并与布线基板2上面位置对合，一旦通过加热、压接而使端子间连接，则形成芯片固定。在芯片1和布线基板2之间，根据需要借助树脂3进行密封。
在多孔质薄板中按照通路孔或布线图形的样子填充导电性物质从而形成多层布线基板的方法已经由本发明人等提出(参照专利文件1)。
平纹编织纤维的多孔质薄板的方案也已经形成(例如参照专利文件2)。
[专利文件1]
特开2001-83347号公报
[专利文件2]
特开平10-321989号公报
发明内容
由于半导体芯片和布线基板的热膨胀系数有很大不同，在以往的倒装芯片法中，半导体芯片和布线基板之间加有很大的应力，存在所谓半导体芯片的连接用凸点和布线基板的布线容易剥离、断裂的问题。
此外，在以往的倒装芯片法中，由于需要连接用凸点，不能使半导体芯片与布线基板贴紧，在薄型化方面存在限制。此外也需要在半导体芯片和布线基板之间形成防止剥离用的应力缓和层，使封装的薄型化困难。
简言之，用以往的倒装芯片法制作的封装存在薄型化困难，半导体芯片和布线基板的连接容易断裂的问题。
此外以往的倒装芯片法，与半导体芯片或布线基板连接用凸点的形成、加热压接工艺是不可缺少的，工艺的成本也高。而且，当半导体芯片的端子间距变得细微，例如成为50μm或以下的间距时，半导体芯片与封装的位置对合变得困难，由于各种部件的制造限制、装置的位置对合精度限制等，倒装芯片的工艺本身也正在变得困难。
本发明目的在于提供一种电子器件模块，该模块具有半导体芯片和布线基板的连接难以断裂，而且还可能薄型化的封装结构，实现了电子器件的小型安装结构。
本发明是一种具有布线基板和与该布线基板一体化的电子器件的模块，其特征在于，上述布线基板具有多孔质的绝缘性基板，以及由选择性地导入该绝缘性基板的多孔质组织内的导电材料所形成的导体布线。
根据本发明的模块结构这样获得：优选多孔质绝缘性基板与电子器件的端子电极露出的面触接配置，进行图形曝光和无电解电镀，在绝缘性基板内形成导体布线，上述多孔质绝缘性基板含有通过能量线照射离子交换性基生成或消失的感光性层。由此，布线基板和电子器件以导体布线的与电子器件端子电极相接的部分作为粘结层而直接连接。从而，使得不需要以往的倒装芯片方式中那样的连接用凸点，可获得薄型、小型的模块。
布线基板的导体布线最好形成为具有：第1导体部，作为与电子器件的装载面平行的布线部；第2导体部，贯通绝缘性基板。由此，电子器件的端子通过布线基板而在其底面导出，而且容易完成印制布线板等的连接。
在布线基板的导体布线中，构成贯通布线的第2导体部的宽度被形成为，在第1和第2导体部的连接部中，在平行于布线基板的上述电子器件的装载面的平面内，第1导体部的长度方向的第2导体部的宽度比上述第1导体部的宽度方向的第2导体部的宽度长。更优选，使第1导体部宽度方向的宽度和相同方向的第2导体部的宽度相同。即由于不形成以往那样的焊接区而连接水平布线和贯通布线，所以即使在电子器件具有微小间距的端子电极排列的情况下，也可形成与该端子间距对应的微小间距的布线，实现模块小型化。此外贯通布线具有与水平布线足够的连接面积而被连接，所以可以形成可靠性高，电气特性优异的电子模块。
绝缘性基板优选具有与电子器件大致相等的热膨胀系数。由此，防止由热应力产生的电子器件和布线基板之间的剥离或破裂。此外，由于导体布线形成在绝缘性基板的多孔质组织内部，所以也没有所谓的布线从基板的剥离，可获得高的可靠性。此外同样由于导体部在多孔质组织内部一体地形成，也不容易产生例如通路孔和布线的接合部的剥离等的导体部的断裂。
按照如上上述的本发明，具有在薄型化、小型化方面理想的安装构造，可获得电气特性及可靠性优异的电子器件模块。
附图说明
图1是展示本发明实施方式的半导体芯片封装结构的剖面图。
图2是展示同一实施方式的制造工艺的剖面图。
图3是同一实施方式的布线基板的平面图及其I-I’剖面图。
图4是展示同一实施方式的半导体芯片装载状态的平面图。
图5是展示其他实施方式的半导体芯片封装结构的剖面图。
图6是展示其他实施方式的半导体芯片封装结构的剖面图。
图7是展示其他实施方式的半导体芯片封装结构的剖面图。
图8是展示以往的倒装芯片安装结构的剖面图。
图9是展示其他实施方式的半导体芯片封装结构的剖面图。
图10是展示其他实施方式的半导体芯片封装结构的剖面图。
图11是展示半导体芯片封装的制造工艺的1个例子的剖面图。
图12是展示其他实施方式的封装结构的剖面图。
图13是展示其他实施方式的封装结构的剖面图。
图14是展示其他实施方式的封装结构的剖面图。
图15是展示其他实施方式的封装结构的剖面图。
符号说明
11…半导体芯片、12…端子电极、20…布线基板、21…多孔质绝缘性基板、22a，22b…布线导体、30…光掩模、31…玻璃基板、32a…完全遮蔽掩模部、32b…部分遮蔽掩模部、40…模制树脂、51…封装基座
具体实施方式
以下参照附图说明本发明的实施方式。在以下的实施方式中举出半导体封装作为电子器件模块。
图1展示了根据一种实施方式的半导体封装的剖面结构。半导体芯片11的端子电极12不通过凸点，而直接连接在布线基板20的导体布线22上。
布线基板20在多孔质绝缘性基板21的多孔质组织内形成有导体布线22。导体布线22由平行于基本面的构成布线的导体部22a和贯通上下面间的导体部22b构成。这些导体部22a、22b详细情况在后面叙述，可以通过在使半导体芯片11与绝缘性基板21触接的状态下进行图形曝光和无电解电镀来形成。此时导体部22b含有从半导体芯片11的端子电极12的面成长的电镀层，因此导体部22b与端子电极12相接的部分成为半导体芯片11与布线基板20之间的粘结层，形成半导体芯片11与布线基板20之间的电性及机械性连接。在多孔质绝缘性基板21中，优选将热固性树脂等的浸渍树脂浸渍在多孔质组织内，进行固化，使得布线基板20的机械性强度和可靠性提高，同时将布线基板20与半导体芯片11粘结，使之一体化。
图2(a)到(c)是展示根据本实施方式的半导体封装的制造工艺的剖面图。如图2(a)所示，在形成有半导体芯片11的端子电极12的面上配置后来成为布线基板20的多孔质绝缘性基板21。令绝缘性基板21含有可通过能量线照射使得离子交换性基生成或消失的感光性层。为使芯片11和绝缘性基板21之间暂时粘结固定，在绝缘性基板21上形成预粘着层，或使用有粘着性的基板材料。
之后，在绝缘性基板21与半导体芯片11相反的一侧上，配置光掩模30，并对布线导体图形进行曝光。如果使含于绝缘性基板21中的感光性层通过光照射生成离子交换性基，则光掩模30使用在玻璃基板31中，形成有对作为要形成的布线部进行光照射的两重掩模材料32a、32b的掩模。一方面掩模材料32a为完全遮蔽不形成布线导体的部分的掩模。另一方面掩模材料32b为部分遮蔽掩模，与图1所示的布线导体中的平行于基板21的导体部22a对应地形成。透过部对应于同样在图1所示出的布线导体中的贯通基板21的导体部22b。
使用这样的光掩模30进行曝光时，曝光量和曝光深度随掩模图形位置而不同，离子交换性基的生成深度受到控制。具体地说，在部分遮蔽的掩模材料32b的部分中，仅在基板21的表面部形成离子交换性基，在透过部，通过充分的曝光量，在贯通基板21的深度的范围内形成离子交换性基。该离子交换性基的分布成为导体布线的潜像。
此后，当对绝缘性基板21进行无电解电镀时，在多孔质组织内的离子交换性基中吸附金属离子或金属胶体。由此，如图2(b)所示，形成根据曝光图形及其各部分的曝光量而深度不同的布线导体22。即，布线导体22由在曝光侧表面部中平行于基板21而形成的导体部22a，和贯通基板21、到达基板21的背面而导引该导体部22a的导体部(贯通导体)22b构成。
此外，在电镀工艺中，优选用适当的保护层覆盖半导体芯片11的表面，使之不形成电镀。
在电镀工艺中形成的导体部22b，如上述那样也成为相对于与半导体芯片11的端子电极12的粘结层，与端子电极12直接、机械地且电性地连接。此后，根据需要，如图2(c)所示，使树脂浸渍在绝缘性基板21中。
更具体地来说明。多孔质的绝缘性基板21可使用有机材料、无机材料，只要是内部有空孔的就可以。例如作为有机绝缘性基板，可使用作为印制布线基板以往所使用的材料的环氧树脂、双马来酰亚胺-三嗪树脂、PEEK树脂、丁二烯树脂等。使用这些印制材料，可通过延伸法、相转移法等作成多孔质基板(薄板)。
作为无机绝缘性基板，可使用陶瓷材料。例如，二氧化硅、氧化铝、二氧化钛、钛酸钾等的金属氧化物，或碳化硅、氮化硅、氮化铝等。通过溶胶-凝胶法、乳液模板法等，可由这些陶瓷材料形成多孔质基板。
作为绝缘性基板21，也可使用无机材料和有机材料的复合材料。例如，可举出使二氧化硅、氧化铝等陶瓷填充物分散在聚酰亚胺或聚酰胺等聚合物中的材料。
绝缘性基板的多孔质结构优选三维网目状多孔质结构，该结构在基板内部均匀地形成了在基板外部具有开口端的分支的连续空孔。在具有三维网目状的多孔质结构的绝缘性基板中，由于在其内部浸渍、填充的导电性物质也在基板内三维地连续，因而被良好地保持、固定。此外，由于填充了导电性物质的空孔不仅在基板的膜厚方向而且在水平方向也连续，所以除了可形成贯通或非贯通的导体部以外，也可获得良好的导电率。
此外，在不具有三维连续空孔的蜂窝状多孔质薄板或平纹编织纤维等网格状薄板等的情况下，不能期待这样的效果。例如，在专利文件2(特开平10-321989号公报)中所揭示的那样的平纹编织的网格状薄板中，虽然可向若干水平方向导通，但必须在薄板的上下确保大部分的水平方向的导电性。因此，在导电性图形部分和非导电部分形成了凹凸。因此，由于难以层叠等，层间的绝缘层厚度不定，使得高频特性差。此外，在通路孔或布线微细化的情况下，由于导电图形尺寸和纤维粗度成为同一水平，难以形成小直径的通路孔。而且，由于布线宽度不一定，高频特性显著恶化。此外，在无纺织布的情况下，由于一般的无纺织布由10μm左右或以上的纤维形成，存在与蜂窝状多孔质薄板或网格状薄板同样的问题。特别是形成由通路孔和布线形成的立体化微细布线结构非常困难。
通过使用具有与导体部的图形尺寸相比足够小的、最好10分之一或以下的空孔直径的三维连续空孔的多孔质绝缘性基板，可消除这样的问题。
绝缘性基板的多孔质组织的空孔率优选为45-95％，更优选为50-85％。在空孔率过大的情况下，绝缘性基板的机械性强度和尺寸稳定性不够。另一方面，如果过小则难以填充导电性物质，确保充分的导电率变得困难。空孔率可借助电子显微镜观察等来测定。此外也可以通过求出绝缘性基板的比重算出来。
另外，绝缘性基板的多孔质组织的空孔的平均空孔径优选是0.05-5μm，更优选是0.1-0.5μm。在空孔径过大时，形成细微的导体部变得困难。特别是在通过上述那样的曝光形成导体部的情况下，由于引起大的散射而不能对细微的图形进行曝光。另一方面，如果空孔径过小则难以填充导电性物质。此外与空孔径同时，空孔的间距大小也是重要的。如果存在间距大的部分即无孔部分，则在这里引起大的光散射，难以一边控制达到绝缘性基板内部的形状一边进行曝光。无孔部分的旋转半径优选在10μm或以下，更优选在5μm或以下。此外，优选无孔部分不局部性地存在，而是均匀地分散。平均空孔径和无孔部分的旋转半径等可通过光散射法和X射线散射法等进行测定。
绝缘性基板的薄板厚度采用平均空孔径的10倍或以上，优选50倍或以上。如果相对于空孔径，余下的薄板厚度过薄，则所形成的导体部在厚度方向上的形状容易乱，使导体部的电气特性劣化。导体部由在空孔中填充的导电物质累积而形成。如果相对于薄板厚度空孔径太大，则难以析像清晰度良好地形成导体部厚度方向的形状。特别是在贯通薄板的导体部和非贯通的导体部形成在一片薄板中的情况下，空孔径相对于薄板的厚度需要足够小。
此外，如果空孔径相对于薄板的厚度过大，则缺乏厚度方向的伸缩性，对于电子器件表面凹凸的随动性不足。
多孔质绝缘性基板的优选薄板厚度根据与上述空孔径的关系，以及在一片薄板中形成的布线层数来适当地确定。在一片薄板中形成沿厚度方向贯通的导体部的情况下，薄板厚度优选为5-30μm。在薄板过薄时操作困难，并且不能充分确保布线层间的绝缘性。另一方面，如果太厚则贯通薄板厚度方向形成导体部变得困难。在将布线层以及用于将该布线层连接到电极的通路孔制作到一片薄板上的情况下，绝缘性基板的厚度优选为10-200μm，更优选为40-100μm。
此外，作为绝缘性基板21，优选使用热膨胀系数与半导体芯片11大致相等的，低热膨胀系数的材料。由此，可防止因热应力造成的半导体芯片11与布线基板20之间的剥离，或布线基板和芯片中发生破裂的情况。导体布线22由于形成在绝缘性基板21的多孔质组织内部，所以没有所谓的从基板剥离。
形成在绝缘性基板21的内部的感光性层，只要是具有借助能量性照射而使离子交换性基生成或消失的感光性基就可以。作为由能量线照射而生成离子交换性基的分子，可列举例如，羧酸、磺酸或硅烷醇的邻-硝基苄基酯衍生物、对-硝基苄基酯衍生物等。由能量线照射而使离子交换性基消失的感光性基，在照射前具有离子交换性基，由于能量线照射而使离子交换性基脱离，或变化成疏水性基，可列举例如，通过脱碳酸反应而分解的羧基衍生物基。
形成在绝缘性基板21的内部的感光性层，优选使用预先具有感光性基的聚合物材料形成，也可通过使感光材料溶液浸渍之后进行干燥的方法来形成。
在形成与在绝缘性基板21内通过曝光而形成的离子交换性基的潜像对应的导体布线时，在离子交换性基的图形中吸附金属离子，根据需要将该金属离子还原成金属粒子，并进行无电解电镀。此时如果电镀液通过绝缘性基板21处于与半导体芯片11的端子电极12的面接触的状态，则在端子电极12为铜、金、银、钯、镍等的情况下，从端子电极面也析出电镀。这与在绝缘性基板21内部析出的电镀成一体化，使成为贯通布线的导体部22b与端子电极12电气地以及机械性良好地连接。特别是通过使布线导体22与半导体芯片11的端子电极12为相同的金属例如铜，在连接界面中不插入异种金属，使强固的连接成为可能。
按照该实施方式，与倒装芯片方式不同，可以不使用凸点而在布线基板上搭载半导体芯片。因此，封装薄型化成为可能。此外，在半导体芯片和布线基板之间不需要倒装芯片方式那样意义上的位置对合，而通过使它们重合的状态下的曝光工艺，决定在布线基板中形成的布线导体与半导体芯片的端子电极的连接状态。因此，即使在半导体芯片的端子电极按微小的间距排列的情况下也不需要以往那样的困难的位置对合。
此外在该实施方式的情况下，如上上述，与布线导体22的布线基板20平行地形成的导体部22a，和引导该导体部22a贯通基板20到达基板20的背面的导体部(贯通导体)22b可以一起形成。因此从原理上来说22a和22b位置不会偏移。因此在导体部22a和22b的连接部，不需要设置比通常层间连接所需要的布线宽度更宽面积的焊接区，作为相对于位置偏移的余量。
具体地说，图3(a)(b)展示了按照该实施方式形成的布线基板20的布线导体22部的平面图及其I-I’剖面图。构成横方向布线的导体部22a的布线宽度(宽度方向的宽度)一直到构成贯通布线的导体部22b都保持一定，在导体部22b不需要制作焊接区。此外，由于在光掩模30的透过部和部分遮光部的交界部，曝光量在基板内部连续地变化，因此在电镀工艺中实际形成的导体部22b，如图3(b)所示，在基板厚度内的宽度变为仅在布线的长度方向变化的状态。
即，在导体部22a和22b的接合部中，导体部22a的长度方向的导体部22b的宽度比导体部22a的宽度方向的导体部22b的宽度形成得长。这是因为，如图3(c)所示，对导体部22a进行曝光的泄漏光以及对导体部22b进行曝光的泄漏光协同作用，使得导体部22b只沿导体部22a的长度方向引出末端形成。泄漏光在图3(C)中用箭头表示。因此可以不形成对布线宽度进行阔宽那样的无用的焊接区，获得导体部22a和22b足够的接合面积，并且可以平滑的曲面进行连接。因此，在导体部22a和22b的接合部中不断裂的可靠性高，并且电气特性方面也优异。
这样的导体部22b与22a的接合部的形状最好形成为导体部22a的长度方向的导体部22b的宽度L1，比导体部22a的宽度方向的导体部22b的宽度L2长。L1与L2的比率L1/L2的值优选是1.2或以上，进一步优选1.5或以上。L1/L2的值如果太小，则上述那样的可靠性或电气特性不充分。至于L1/L2的值的上限则没有特别的限制，但最好L1/L2的值在3.5或以下，进一步优选在2.5或以下。L1/L2的值如果过大，则阻抗匹配变得困难。
图4是展示按照该实施方式在布线基板20上装载具有微细间距的多个端子电极的半导体芯片11的情况的平面图。由于上述那样的布线导体22不设置焊接区而是按照一定的宽度形成，因此容易按照与半导体芯片的端子间距对合的微细间距来形成，因而可获得小型的封装。
而且，作为布线基板20，通过使用与半导体芯片11相同程度的低热膨胀系数材料，可获得不发生因热应力造成的芯片剥离的可靠性高的封装。由于布线导体形成在绝缘性基板内部，因此不仅布线导体与基板的贴紧性良好，而且也不发生布线的剥离。
图5与图1对应地展示根据本发明另外的实施方式的封装结构。与图1的实施方式的不同点是：在布线基板20的导体布线22中，作为平行于基板表面的布线部的导体部22a被埋入到基板21的厚度的中程处。除曝光工艺外与前面的实施方式同样地进行来获得该结构。
在曝光工艺中，例如与前面实施方式中的部分遮光掩模32b相当的部分的曝光，使用透镜进行使得聚光在绝缘性基板21的厚度方向中程处的扫描曝光。由此，可以形成在绝缘性基板21的内部埋设状态的导体部22a。
图6是又一个另外的实施方式，以图1的封装结构为基础，用模制树脂40覆盖半导体芯片11。
到此为止的实施方式是以布线基板20作为封装基座的。因此，在实际的用途中，例如在布线基板20的与半导体芯片11相反侧的表面中露出的贯通导体部22b的端面再设置凸点，变成通过该凸点与印制基板等的布线相连接。
与此相对照，图7是按照另一个实施方式的模块结构。半导体芯片11在图示的情况下为2个，但布线基板20被预先装载在另外准备的封装基座50上。具体地说，封装基座50形成有用于装载半导体芯片11的凹部51，以在该凹部51中埋入的形式装载半导体芯片11。
这样在将半导体芯片11以端子电极12向上埋入封装基座50中的状态下，配置多孔质绝缘性基板21，以便与前面的实施方式同样地与半导体芯片11的端子电极12触接，进行图形曝光和无电解电镀。由此，可以形成作为横方向布线的导体部22a，和将其与半导体芯片11的端子电极12以及封装基座50的端子电极52连接的贯通导体部22b。
至此，作为电子器件，仅说明了半导体芯片的情况，但本发明不限于此，例如在含有片状电容器或电阻、线圈等其他芯片状器件，将各种电子器件进行封装或模块化的情况下也是有效的。
以下详述上述那样的电子模块的具体结构例子。图9是展示根据本发明的半导体封装的一个例子的构成的剖面图。多孔质绝缘性基板21贴紧在半导体芯片11上，在绝缘性基板上形成有与半导体芯片11的端子电极12连接的导体部22b(通路孔)和导体部22a(布线)。导体部22a在绝缘性基板21外也一部分涨起22c，降低布线电阻。通过浸渍在绝缘性基板21中的固化性树脂等将半导体芯片11和绝缘性基板21粘结。
此外，浸渍树脂的一部分在绝缘性基板21上形成焊料抗蚀剂层52。而且，导体部22a和22c连接到设置在焊料抗蚀剂层52上的凸点53上。
在这样构成的半导体封装中，由于导体部22b(通路孔)和导体部22a及22c(布线)与绝缘性基板21一体化，难以引起由于起因于半导体芯片11和绝缘性基板21的热膨胀率不同的应力带来的破损。特别是，不仅导体部22b(通路孔)和端子电极12的界面，而且导体部22b(通路孔)和导体部22a及22c(布线)的界面都可以良好地连接。而且由于焊料抗蚀剂层52与浸渍在绝缘性基板21中的树脂一体化，因此焊料抗蚀剂层52与绝缘性基板21的界面难以剥离，可靠性高。在图9中虽然绝缘性基板21比半导体芯片11大，但如图10所示的半导体芯片11与绝缘性基板21同样大小的芯片尺寸封装也可以。
图11中示出了图9或图10所示的半导体封装的制造工艺。首先，使用记述过的方法，准备贴紧在半导体芯片11上，并且形成了与电极12接合的导体部22b(通路孔)和导体部22a及22c(布线)的多孔质绝缘性基板21(参照图11(a))。
其次，使固化性树脂等浸渍在绝缘生基板21中。使树脂固化，将半导体芯11与绝缘性基板21粘结。在浸渍时，树脂堆积到绝缘性基板21上面，形成焊料抗蚀剂层52(参照图11(b))。用激光等除去焊料抗蚀剂层52的规定区域，形成形成有焊锡凸点的开口部54(参照图11(c))。在开口部54中进行Ni-Au电镀等后，形成凸点53，作为半导体封装(参照图11(d))。
在使用半导体芯片时，既可以在单片化的半导体芯片上进行上述工艺，也可以在晶片水平上进行上述工艺。即，在形成了电路的晶片上贴附绝缘性基板，进行上述工艺。然后，也可以进行切分，成为芯片尺寸的封装。
接着在图12中示出连接了多个电子器件的模块，及其制造工艺。
首先，在图12(a)中所示的绝缘性基板21上载置多个电子器件55后(参照图12(b))，通过在绝缘性基板上形成将这些电子器件55的电极56相互连接的布线57，可获得模块57(参照图12(c))。
图13(a)、(b)、(C)示出了半导体封装的结构的例子。在图13中，例示了水平方向的布线层为1层的，但布线层是2层或2层以上也可以。此外例示了凸点是形成了焊锡凸点的凸点，但不用说即使是焊锡以外的凸点也可以。
图14中展示了层叠用封装58(图14(a))，和层叠了该封装的层叠封装59(图14(b))的一个例子。封装58在下表面具有焊锡凸点53，在上表面形成了用于接合焊锡凸点的上部焊盘60。通过将该封装58的焊锡凸点与下一个封装的上部焊盘60接合，形成层叠封装59。
此外，作为其他层叠封装的例子，图15那样的也可以。首先，如图15(a)所示，在半导体芯片11上贴附多孔质绝缘性基板21。然后，如图15(b)所示，在形成与半导体芯片的端子电极(图中未示出)连接的导体部61后，如图15(c)所示，弯折绝缘性基板21，到达半导体芯片的上表面，形成层叠用封装62。在将浸渍树脂浸渍在绝缘性基板21上后，对层叠用封装62进行多层层叠，如图15(d)所示，形成层叠封装63。由于绝缘性基板为多孔质，将层叠用封装彼此粘结的浸渍树脂由于是成一体地固化，因此不容易发生封装间的剥离等，可靠性非常优异。
也可以在将预先形成了导体部潜像的绝缘性基板21弯折后进行电镀，形成从最初就是弯折状态的导体部64。弯折之后进行电镀的方法可以防止因弯折而造成的导体部61的损伤等。
(实施例)
以下具体说明本发明的实施例，但本发明不仅限于这些实施例。
作为电子器件，使用厚50μm，焊盘直径100μm，焊盘间距200μm的半导体芯片。焊盘表面为铜，使用通过钯置换电镀进行了活性化的焊盘。此外半导体芯片的背面和侧面利用硅烷偶合剂进行了疏水化处理。
作为用于形成封装布线的多孔质薄板，准备亲水化处理过的PTFE多孔质薄板(平均空孔径0.1μm，膜厚60μm)，从其单面涂敷丙烯酸系粘合剂溶液，进行干燥。作为丙烯酸系粘合剂溶液，使用在由2-乙基己基丙烯酸酯、甲基丙烯酸甲酯以及丙烯酸构成的共聚物中添加了异氰酸酯系交联剂和萜烯系赋予粘着性的树脂的混合溶液。涂敷干燥后，利用异氰酸酯系交联剂将共聚物进行交联，给PTFE多孔质薄板提供粘着性。此外，在丙酮中溶解作为有机感光性组合物的含有萘醌二叠氮基的酚醛树脂(萘醌二叠氮基含有率为33当量mo1％)，调制1wt％的丙酮溶液。用浸渍法将所获得的溶液涂敷到上述的多孔质薄板的全表面上。在室温下干燥30分钟，用含有萘醌二叠氮基的酚醛树脂涂敷空孔内表面，获得感光性以及粘着性的多孔质薄板。
在该多孔质薄板上载置半导体芯片，使其与形成了焊盘的面相接，以10g/cm2的压力加压，通过粘合进行贴附。贴附后，借助CANON PLA501，通过线宽20μm、间隔30μm的布线图形掩模，在曝光量200mJ/cm2(波长436nm)的条件下进行曝光，在感光性层中形成由茚羧酸构成的布线图形的潜像。进一步，通过50μm通路孔径的通路孔图形的掩模，在曝光量2000mJ/cm2(波长436nm)的条件下进行曝光，形成通路孔图形的潜像。
布线图形和通路孔图形的潜像形成后，在贴附半导体芯片的状态下，在硼氢化钠为5mM的水溶液中浸渍10分钟后，重复3次利用蒸馏水进行的清洗。接着在调整为50mM的醋酸铜水溶液中浸渍30分钟后，用蒸馏水洗净。接着，在硼氢化钠为30mM的水溶液中浸渍1小时后，用蒸馏水清洗。进一步，通过在无电解电镀液PS-503(荏原ユ-ジライト社制)中浸渍3小时，实施铜电解，形成布线及通路孔构成的封装布线。
结果在PTFE多孔质薄板的表面上形成线宽25μm、间隔25μm，深度20μm的表面布线。此外，沿薄板厚度方向贯通该PTFE多孔质薄板，形成55μm直径的无焊接区的通路孔。此外表面布线和通路孔的接合部分用顺滑的曲面连接。此外，接合部分中通路孔的长度方向与宽度方向的比(L1/L2)为1.5。
另一方面，调制在氰酸酯树脂(旭チバ株式会社制)100重量份中添加了2重量份的铝螯合物催化剂的树脂液作为浸渍在多孔质薄板中的浸渍树脂。将该树脂液浸渍在形成了上述的导电部的多孔质薄板后，在150℃下加热5小时，使之固化。使浸渍树脂不仅浸渍在多孔质薄板中，而且涨到多孔质薄板上面，形成厚度10μm的焊料抗蚀剂层。
固化后，借助激光钻孔除去覆盖封装布线的焊盘部分的树脂，进行开口。对露出的焊盘表面进行无电解镍电镀后，进行置换金电镀。接着加载焊锡球形成焊锡凸点，做成半导体封装。作为浸渍树脂，即使替代氰酸酯树脂，使用环氧树脂或苯并环丁烯树脂，也同样可以制作半导体封装。
此外，代替对布线和通路孔分两次进行曝光，除了使用半色调(ハ-フト-ン)掩模，使对布线进行曝光的部分的透过量为对通路孔进行曝光的部分的透过量的10％，在曝光量2000mJ/cm2(波长436nm)的条件下进行曝光以外，利用同样的工艺也可以制作半导体封装。
而且，除了在多孔质薄板上贴附2个半导体芯片以外，用同样的工艺，可以制作由2个半导体芯片和与之相互连接的封装布线构成的半导体模块。
此外，作为比较例，调整通路孔和布线连接部分的曝光量，将接合部分的通路孔的长度方向与宽度方向的比(L1/L2)调整到1及1.2，制作半导体封装。对于这些半导体封装进行布线电阻和热循环试验，L1/L2＝1时布线电阻最高，可靠性差，L1/L2＝1.5时最好。
此外，作为其他的制作方法，在形成通路孔和布线之后制作贴附在半导体芯片上的半导体封装。首先，不与半导体芯片贴附，制作形成有同样的通路孔和表面布线的PTFE多孔质薄板，使同样的氰酸酯树脂液浸渍之后，将该薄板压接在半导体芯片上，进行粘结。将该半导体封装与前面在半导体芯片上贴附多孔质薄板后进行电镀而制作的半导体封装进行比较，则在半导体芯片上贴附多孔质薄板后进行电镀的半导体封装，半导体芯片端子电极与通路孔之间的电阻低，而且进行热循环试验时，电极和通路孔之间的界面不容易剥离，可靠性优异。

Claims (7)

1.一种电子器件模块，具有布线基板和与该布线基板一体化的电子器件，其特征在于，上述布线基板具备：
多孔质绝缘性基板，以及
由选择性地导入该绝缘性基板的多孔质组织内的导电材料所形成的导体布线。
2.根据权利要求1所述的电子器件模块，其特征在于，
布线基板的导体布线具有：作为与上述电子器件的装载面平行的布线部的第1导体部；和贯通上述多孔质绝缘性基板的第2导体部。
3.根据权利要求2所述的电子器件模块，其特征在于，
上述第2导体部的宽度，在第1和第2导体部的连接部中，在平行于上述布线基板的上述电子器件的装载面的面内，上述第1导体部的长度方向的上述第2导体部的宽度比上述第1导体部的宽度方向的上述第2导体部的宽度长。
4.根据权利要求1所述的电子器件模块，其特征在于，
上述布线基板和电子器件以上述导体布线的与上述电子器件端子电极相接的部分作为粘结层而直接连接。
5.根据权利要求1至4任意一项所述的电子器件模块，其特征在于，
上述绝缘性基板具有与上述电子器件大致相等的热膨胀系数。
6.根据权利要求1至4任意一项所述的电子器件模块，其特征在于，
上述电子器件是半导体芯片，上述布线基板是装载上述半导体芯片的封装基座。
7.根据权利要求1至4任意一项的电子器件模块，其特征在于，
上述电子器件是端子电极向上地装载在封装基座上的半导体芯片，上述布线基板在直接连接上述半导体芯片的端子电极的状态下载置在上述半导体芯片上面。
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