CN1301044C - 电路装置 - Google Patents

电路装置 Download PDF

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Publication number
CN1301044C
CN1301044C CNB2004100120160A CN200410012016A CN1301044C CN 1301044 C CN1301044 C CN 1301044C CN B2004100120160 A CNB2004100120160 A CN B2004100120160A CN 200410012016 A CN200410012016 A CN 200410012016A CN 1301044 C CN1301044 C CN 1301044C
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China
Prior art keywords
semiconductor element
conductive pattern
peristome
circuit arrangement
conductive
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Expired - Fee Related
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CNB2004100120160A
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CN1604719A (zh
Inventor
中野敦史
加藤敦史
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication of CN1604719A publication Critical patent/CN1604719A/zh
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Abstract

一种电路装置,可使电路元件和其它构成要素的粘附性提高。本实施例的电路装置(10A)包括:导电图案(12);覆盖树脂(14),除去第一开口部(11A),覆盖导电图案(12);半导体元件(13A),其介由导电膏(9)电连接在自第一开口部(11A)露出的导电图案(12)上,其中,第一开口部(11A)的大小比半导体元件(13A)更小地形成,导电膏(9)接触自第一开口部(11A)露出的导电图案(12)及覆盖树脂(14)两者。

Description

电路装置
技术领域
本发明涉及电路装置,特别是涉及使电路元件和其它构成要素的密封性提高的电路装置。
背景技术
参照图9说明现有型半导体装置100的结构。图9(A)是半导体装置100的平面图,图9(B)是其剖面图(参照专利文献1)。
参照图9(A),在半导体装置100的中央部形成由导电材料构成的接合区102,并在接合区102的周围近接多个引线101的一端。引线101的一端介由金属细线105和半导体元件104电连接,另一端自密封树脂103露出。密封树脂103具有密封半导体元件104、接合区102及引线101,并将其一体地支承的作用。
专利文献1特开平11-340257号公报
但是,在所述的装置中,在其表面形成有镀膜的接合区102的表面安装半导体元件104。由此,在介由银膏等低粘附性的粘接剂将半导体元件104安装在接合区102上时,由于半导体元件104和接合区102的粘附性不足,容易引起接触不良。另外,粘接半导体元件104和接合区102的粘接剂还具有自接合区102流出的问题。
发明内容
本发明是着眼于所述的问题而开发的,本发明的主要目的在于,提供使电路元件和其它构成要素的粘附性提高的电路装置。
本发明的特征在于,包括:导电图案;覆盖树脂,其除开口部外,覆盖所述导电图案;半导体元件,其介由导电膏电连接在自所述开口部露出的所述导电图案上,其中,所述开口部比所述半导体元件更小地形成,所述导电膏接触自所述开口部露出的所述导电图案及所述覆盖树脂两者。
另外,本发明的特征在于,所述导电膏是银膏。
另外,本发明的特征在于,在自所述开口部露出的所述导电图案的表面形成有镀膜。
此外,本发明的特征在于,沿所述半导体元件各边的中间部设置所述开口部,所述半导体元件的角部介由所述导电膏粘接在所述覆盖树脂上。
本发明的特征在于,形成有密封所述半导体元件的密封树脂。
另外,本发明的特征在于,所述导电图案具有多层配线结构。
根据本发明的电路装置,通过在导电图案和将其覆盖的覆盖树脂两者上接触进行半导体元件粘接的导电膏,可介由覆盖树脂提高半导体元件和导电图案的粘附性。另外,通过沿半导体元件各边的中间部设置自覆盖树脂露出导电图案的开口部,抑制了导电膏的过度扩散。
附图说明
图1是显示本发明电路装置的平面图(A)、剖面图(B);
图2是显示本发明电路装置的平面图(A)、剖面图(B);
图3是显示本发明电路装置的剖面图;
图4是显示本发明电路装置的剖面图;
图5是显示本发明电路装置制造方法的剖面图(A)~(D);
图6是显示本发明电路装置制造方法的剖面图(A)~(D);
图7是显示本发明电路装置制造方法的剖面图(A)、平面图(B);
图8是显示本发明电路装置制造方法的剖面图(A)、平面图(B);
图9是显示现有的电路装置的平面图(A)、剖面图(B)。
具体实施方式
参照图1,说明本实施例的电路装置10A的结构。图1(A)是电路装置10A的平面图,图1(B)是其剖面图。
参照图1(A),本实施例的电路装置10A是利用密封树脂18密封半导体元件13A的封装体。另外,还形成有由第一配线层20及第二配线层21构成的多层配线。在此,第一配线层20含有第一导电图案12A及第二导电图案12B。以下,详细说明各要素及相关结构。
参照图1(B),形成由第一配线层20及第二配线层21构成的多层配线结构。另外,也可以构成三层以上的多层配线结构。所述第一导电图案12A及第二导电图案12B形成在第一配线层20上。另外,也可以形成使这些导电图案12相互之间连接的配线部。第二配线层21形成用于粘接外部电极的焊盘部。另外,也可以在第二配线层21上形成用于使电路交叉的配线部。第一配线层20和第二配线层21介由由树脂构成的绝缘层32层积,并通过连接部23在所希望的位置进行电连接。
如上所述,第一导电图案12A被设于半导体元件的下方。并且,第一导电图案12A也可以形成为平面尺寸比半导体元件13A更大的接合区状。第一导电图案12A的表面由覆盖树脂14覆盖,且该表面自第一开口部11A部分地露出。露出部分的第一导电图案12A介由导电图案9与半导体元件的背面电连接。第一导电图案12A也可以介由连接部23和下层的第二配线层21连接。另外,还可以介由外部电极17电连接在安装侧的安装衬底等上。
第二导电图案12B包围所述接合区状的第一导电图案而配置。第二导电图案12B的表面自设于覆盖树脂14的第二开口部11B露出。第二导电图案12B介由金属细线15和半导体元件13A电连接。
在此,电路元件13采用半导体元件13A。另外,可采用LSI芯片、裸晶体管芯片、二极管等有源元件作为电路元件13。另外,还可以采用片状电阻、片状电容或电感等无源元件作为电路元件13。也可以内装这些多个电路元件13,并在内部将其电连接。半导体元件13A的背面介由导电膏9固定在导电图案12上。介由金属细线15将半导体元件13A的表面电极和第二导电图案12B电连接。另外,半导体元件13A也可以通过倒装法连接。当使用片状元件时,介由焊锡等焊料其两端电极固定在导电图案12上。
密封树脂18由利用注入膜形成的热塑性树脂或利用传递膜形成的热硬性树脂构成。密封树脂18具有密封装置整体的作用,同时,还具有机械地支承装置整体的功能。
第二配线层21利用由树脂构成的抗蚀剂16覆盖。在自设于抗蚀剂16上的开口部露出的第二配线层21的表面形成由焊锡等焊料构成的外部电极17。
第一开口部11A是部分地除去覆盖第一导电图案12的覆盖树脂14的区域,自该区域部分地露出第一导电图案12。第二开口部11B是部分地除去覆盖第二导电图案13的覆盖树脂14的区域。这样,和电路元件13电连接的位置的导电图案12自开口部露出。参照图2详细说明这些开口部的具体结构。另外,在自开口部露出的位置的导电图案12的表面形成镀膜。在此,镀膜可采用由银或金构成的镀膜。
说明半导体元件13A和第一导电图案12A的相关结构。使用银膏等导电膏9将半导体元件13A固定在覆盖树脂14的表面。在此,在半导体元件13的载置区域形成第一开口部11A,该第一开口部11A的平面大小比半导体元件13A小。导电膏9粘附于半导体元件13A的背面整个区域上。因此,导电膏9接触自第一开口部11A露出的第一导电图案11A的表面和覆盖树脂14两者。
通过使导电膏9接触第一导电图案11A的表面,可将半导体元件13A的背面和第一导电图案12A电连接,因此,当半导体元件13A为IC时,可将半导体元件13A的背面和接地电位连接,或,也可以将通过接地电位以外的电信号的半导体元件13A的背面和第一导电图案12A电连接。
另外,通过使导电膏9接触覆盖树脂14,可提高半导体元件13A的固定强度。如上所述,在自第一开口部11A露出的第一导电图案12A的表面形成镀膜。由此,该镀膜和导电膏9的附着强度非常弱。因此,在本发明中,通过使导电膏9也与覆盖树脂14接触来确保半导体元件13A的连接强度。由于含有树脂成分的导电膏9和覆盖树脂14的附着强度大,故可提高半导体元件13A的固定强度。
参照图2,以第一开口部11A的具体结构为中心进行说明。图2(A)的平面图及图2(B)的剖面图是省略金属细线等的图示。
参照图2(A),第一开口部11A具有矩形的平面形状。沿同图中以虚线所示的半导体元件13A的周边部设置四个第一开口部11A。另外,沿半导体元件13A的边的中间部设置各个第一开口部11A。另外,第一开口部11A的长度方向沿半导体元件13A的边的方向延伸。第一开口部11A的宽度方向自半导体元件13A的下方向半导体元件13A的外部延伸。
在半导体元件13A角部的下方未设置第一开口部11A。其原因是,在半导体元件12A的角部和导电膏9之间作用有大的应力,该位置的连接在进行半导体元件13A的固定时是重要的。因此,通过在该位置将导电膏9和覆盖树脂14粘接,可使半导体元件13A的固定结构更牢固。
即,在半导体元件13A的下方,未设置第一导电图案12A的区域,导电膏9和覆盖树脂14牢固地附着。参照图2(A),固定区域A1表示导电膏9和覆盖树脂14附着的区域。即,该固定区域A1在半导体元件13A的中央部及角部延伸。换句话说,固定区域A1在半导体元件13A周边部的除各边中间部外的区域延伸。
参照图2(B),说明第一开口部11A另外的效果。第一开口部11A具有抑制导电膏9的扩散的作用。具体地说,通过设置第一开口部11A,可形成对应于覆盖树脂14厚度的台阶。可利用该台阶抑制导电膏9的扩散,可防止导电膏9和其它导电图案12形成短路。另外,导电膏9的扩散在半导体元件13A的边的中间部附近比半导体元件13的角部更大。因此,通过在对应于半导体元件13A的边的中间部的位置设置第一开口部11A,可抑制在该中间部的导电膏9的过度的扩散。另外,通过抑制导电膏9的扩散,也可以使介由导电膏9连接的导电图案12和其它的导电图案的间隔接近。
参照图3,说明另一实施例的电路装置10的结构。电路装置10B的基本结构和图1所示的半导体装置10A相同,不同点在于,具有单层的配线结构。在此,导电图案12相互之间通过填充于分离槽19内的覆盖树脂24分离。然后,将导电图案12的背面自覆盖树脂24露出于下方。另外,其它结构和电路装置10A相同。另外,导电图案12的背面和外部电极17电连接。
参照图4,说明另一实施例的电路装置10C的结构。同图中显示剖面的电路装置10C的基本结构和图1所示的电路装置10A相同,不同点在于,具有支承衬底31。该支承衬底31可使用玻璃环氧衬底等树脂性衬底、陶瓷衬底、金属衬底等众所周知的衬底。
以下,参照图5~图8,说明图1所示的电路装置10A的制造方法。首先,参照图5(A),准备介由绝缘层32层积第一导电箔33及第二导电箔34的层积片。
其次,参照图5(B)在第一导电箔33的表面层积抗蚀剂PR,进行图案形成。具体地说,使对应形成规定连接部的位置的抗蚀剂PR开口。
参照图5(C),介由图案形成的抗蚀剂PR进行第一导电箔33的蚀刻。通过该蚀刻,可部分地除去预定形成连接部的区域的第一导电箔33,形成通孔35。
参照图5(D),在形成通孔35后,除去抗蚀剂PR。然后,通过除去位于通孔35下方的绝缘层32,使通孔35到达第二导电箔34的表面。该绝缘层32的除去可使用碳酸气激光进行。
然后,参照图6(A),通过形成由铜等金属构成的镀膜,在通孔35内形成连接部23,并将第一导电箔33和第二导电箔34电连接。然后,参照图6(B),由抗蚀剂PR覆盖第一导电箔33的上面及第二导电箔34的下面。然后,进行该两抗蚀剂PR的图案形成。另外,使用抗蚀剂PR蚀刻两导电箔。
参照图6(C),以抗蚀剂PR为蚀刻掩膜,蚀刻第一导电箔33及第二导电箔34。其结果形成第一配线层20及第二配线层21。在该蚀刻完成后,如图6(D)所示,剥离抗蚀剂PR。然后,由覆盖树脂14覆盖第一配线层20,使所希望位置的导电图案露出,形成开口部11。
参照图7(A)的剖面图及图7(B)的平面图,在载置预定的半导体元件13A的周边部形成第一开口部11A。然后,构成金属细线连接的焊盘的区域形成第二开口部11B。通过部分地除去覆盖树脂14,形成开口部11。覆盖树脂14的部分的除去可使用激光等进行。另外,覆盖树脂14的部分的除去还可以通过平板印刷工序进行。
其次,参照图8(A)的剖面图及图8(B)的平面图,介由导电膏9将半导体元件13A和第一导电图案12A电连接。在该工序中,通过在自第一开口部11A露出的第一导电图案12A上接触导电膏9,将半导体元件13A的背面和第一导电图案12A导通。然后,通过在覆盖树脂14上附着导电膏9,使半导体元件13A的固定强度提高。具体地说,首先,在覆盖树脂14的上部涂敷导电膏9,在导电膏9上载置半导体元件13A。在本工序中,第一开口部11A具有作为阻止导电膏9过度扩散的阻止区域的功能。因此,在图8(B)中,可防止导电膏9自虚线所示的半导体元件13A的载置区域过度地逸出。由此,可防止由流出的导电膏9引起的导电图案12相互之间的短路。在所述工序后,形成连接半导体元件13A和第二导电图案12B的金属细线15,形成覆盖半导体元件13A的密封树脂18,从而制造图1所示的电路装置10A。
另外,也可使用绝缘性粘接剂代替所述导电膏。此时,也可以利用第一开口部的作用抑制绝缘性粘接剂的过度扩散。

Claims (6)

1、一种电路装置,其特征在于,包括:导电图案;覆盖树脂,其除开口部外,覆盖所述导电图案;半导体元件,其介由导电膏电连接在自所述开口部露出的所述导电图案上,其中,所述开口部比所述半导体元件更小地形成,所述导电膏接触自所述开口部露出的所述导电图案及所述覆盖树脂两者。
2、如权利要求1所述的电路装置,其特征在于,所述导电膏是银膏。
3、如权利要求1所述的电路装置,其特征在于,在自所述开口部露出的所述导电图案的表面形成有镀膜。
4、如权利要求1所述的电路装置,其特征在于,沿所述半导体元件的各边中间部设置所述开口部,并介由所述导电膏将所述半导体元件的角部粘接在所述覆盖树脂上。
5、如权利要求1所述的电路装置,其特征在于,形成有密封所述半导体元件的密封树脂。
6、如权利要求1所述的电路装置,其特征在于,所述导电图案具有多层配线结构。
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JPH04254396A (ja) * 1991-01-30 1992-09-09 Matsushita Electric Ind Co Ltd 高密度実装基板の製造方法
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