CN1341962A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN1341962A
CN1341962A CN01104553A CN01104553A CN1341962A CN 1341962 A CN1341962 A CN 1341962A CN 01104553 A CN01104553 A CN 01104553A CN 01104553 A CN01104553 A CN 01104553A CN 1341962 A CN1341962 A CN 1341962A
Authority
CN
China
Prior art keywords
mentioned
electrode
semiconductor element
insulating properties
adhesive substance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN01104553A
Other languages
English (en)
Other versions
CN1265451C (zh
Inventor
坂本则明
小林义幸
阪本纯次
冈田幸夫
五十岚优助
前原荣寿
高桥幸嗣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN1341962A publication Critical patent/CN1341962A/zh
Application granted granted Critical
Publication of CN1265451C publication Critical patent/CN1265451C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Measurement Of Radiation (AREA)

Abstract

以印刷电路板、陶瓷板、软性板等作为支持基板来装配半导体元件的BGA型的半导体装置。但这些支持基板是多余的材料,支持基板的厚度将使半导体装置大型化,从而成为组装到其中的半导体元件的热难于放热的结构。本发明是将导电图形11A～11D埋入到绝缘性树脂10中而且导电箔20通过半蚀刻而形成,可以充分地减小其厚度。由于设置了放热用的电极11D,可以提供散热性能优异的半导体装置。

Description

半导体装置及其制造方法
本发明涉及半导体装置及其制造方法，特别是可以良好地散出半导体元件的热的半导体装置及其制造方法。
近年来，随着IC芯片在便携式设备及小型、高密度装配设备中的应用，先有的IC组件及其装配概念发生了很大的变化。详细情况，在例如电子材料(1998年9月号22页～)的特集CSP技术及支持它的装配材料和装置中作了介绍。
图9是采用软性板50作为插入板的图，在该软性板50上，通过粘接剂粘贴了铜箔图形51，进而固定了IC芯片52。并且，作为该导电图形51，有在该IC芯片52的周围形成的焊接用的焊区53。另外，通过与该焊接用的焊区53一体形成的配线51B形成焊锡球连接用的焊区54。
并且，在焊锡球连接用的焊区54的背面侧设置了软性板开口的开口56，通过该开口部56形成焊锡球55。并且，以该软性板50为基板全部用绝缘性树脂58进行密封。
但是，设在IC芯片52的背面的软性板50的价格非常昂贵，存在成本高、组件的厚度大、重量增加的问题。
另外，由于支持基板由金属以外的材料构成，所以，存在从IC芯片背面向组件的背面传导的热阻增大的问题。作为上述支持基板，是软性板、陶瓷板或印刷电路板。另外，由热传导良好的材料构成的热传导通路是金属细线57、铜箔图形51和焊锡球55，是在驱动时不能充分放热的结构。因此，在驱动时，IC芯片的温度将上升，从而不能流过充分的驱动电流。
本发明就是鉴于上述问题而提出的，第1，本发明是通过具有与半导体元件的焊接电极对应设置的焊区、设置在上述半导体元件的配置区域中的放热用的电极、设置在上述放热用的电极上的绝缘性粘接物质、固定在上述绝缘性粘接物质上的与上述焊区电气连接的上述半导体元件和露出上述焊区的背面和上述绝缘性粘接物质而一体化地封装上述半导体元件的绝缘性树脂来解决上述问题的。
第2，上述绝缘性粘接物质是粘接薄片或粘接剂。
第3，上述半导体元件以倒装的方式进行装配，上述焊区和上述焊接电极用金属细线连接。
第4，本发明是通过具有包围一个区域而设置的多个焊区、与上述焊区一体地延伸的外部连接电极、设置在上述一个区域中的放热用的电极、设置在上述放热用的电极上的绝缘性粘接物质、通过上述绝缘性粘接物质而固定的半导体元件、将上述半导体元件上的焊接电极与上述焊区连接的金属细线、被覆到上述半导体元件、上述焊区、上述放热用的电极、上述外部连接电极和上述金属细线上并露出上述外部连接电极的背面、上述放热用的电极的背面和上述绝缘性粘接物质的背面的绝缘性树脂来解决上述问题的。
第5，本发明是通过具有包围一个区域而设置的多个焊区、设置在上述一个区域中的放热用的电极、设置在上述放热用的电极上的绝缘性粘接物质、通过上述绝缘性粘接物质而固定的半导体元件、将上述半导体元件上的焊接电极与上述焊区连接的连接部件、被覆到上述半导体元件、上述焊区和上述连接部件上并且露出上述焊区的背面和上述绝缘性粘接物质的背面的绝缘性树脂并将上述焊区的背面作为外部连接电极来解决上述问题的。
第6，上述连接部件是金属细线或焊料。
第7，上述焊区、焊区或外部连接电极的侧面是弯曲结构。
第8，准备导电箔，将导电图形半蚀刻为凸起状，设置绝缘性粘接物质用以填充通过上述半蚀刻而形成的分离沟，与上述导电图形电气连接并且通过上述绝缘性粘接物质固定半导体元件，在上述导电箔上设置绝缘性树脂用以密封上述半导体元件和上述导电图形，露出上述绝缘性粘接物质的背面，除去上述导电箔的背面而分离出导电图形。
第9，准备导电箔，将至少由焊区和放热用的电极构成的导电图形半蚀刻为凸起状，设置被覆到上述放热用的电极上用以填充到与该电极相邻的分离沟中的绝缘性粘接物质，与上述焊区电气连接并且通过上述绝缘性粘接物质将半导体元件固定到上述放热用的电极上，在上述导电箔上设置绝缘性树脂用以密封上述半导体元件和上述焊区，露出上述绝缘性粘接物质的背面，除去上述导电箔的背面而分离出上述导电图形。
通过提供本半导体装置，可以将半导体元件的热向一个放热用的电极传导。另外，包含该放热用的电极的导电图形不采用支持基板就可以形成，所以，可以降低成本，使半导体装置的厚度变薄。
图1是说明本发明的半导体装置的图。
图2是说明本发明的半导体装置的制造方法的图。
图3是说明本发明的半导体装置的制造方法的图。
图4是说明本发明的半导体装置的制造方法的图。
图5是说明本发明的半导体装置的制造方法的图。
图6是说明本发明的半导体装置的制造方法的图。
图7是说明本发明的半导体装置中采用的导电图形的图。
图8是说明本发明的半导体装置的图。
图9是说明现有的半导体装置的图。
实施例1。首先，参照图1说明本发明的半导体装置。图1A是半导体装置的平面图，图1B是沿A-A线的剖面图。
在图1中，将以下的结构要素埋入到了绝缘性树脂10中。即，埋入了焊区11A…、与该焊区11A…一体的配线11B、与配线11B一体形成的设置在该配线11B的另一端的外部连接电极11C。此外，还埋入了设置在由该导电图形11A～11C所包围的一个区域中的放热用的电极11D和设置在该放热用的电极11D上的半导体元件12。半导体元件12通过绝缘性粘接物质AD与上述放热用的电极11D固定，在图1A中，用虚线表示。
另外，半导体元件12的焊接电极13和焊区11A通过金属细线14电气连接。
另外，上述焊区11A…的侧面以非各向异性进行蚀刻，这里，是通过湿腐蚀而形成的，所以，具有弯曲结构，由该弯曲结构发生制动效果。
本结构由半导体元件12、多个导电图形11A～11C、放热用的电极11D、绝缘性粘接物质AD和将它们埋入其中的绝缘性树脂10等4种材料构成。另外，在半导体元件12的配置区域中，在导电图形11B～11D上和它们之间形成上述绝缘性粘接物质AD，特别是在通过蚀刻而形成的分离沟15中设置上述绝缘性粘接物质AD，并露出其背面。另外，包含上述这些材料全部用绝缘性树脂10进行密封。并且，由绝缘性树脂10支持上述焊区11A…和半导体元件12。
作为绝缘性粘接物质，最好是由绝缘材料形成的粘接剂、粘接性的绝缘片。另外，由后面所述的制造方法可知，最好是可以粘贴到整个晶片上并且可以利用光刻法刻制图形的材料。另外，作为绝缘性树脂，可以使用环氧树脂等热硬化树脂、聚酰亚铵树脂、硫化聚苯等热可塑性树脂。另外，只要绝缘性树脂是使用模具固化的树脂、浸渍成形、可以进行涂布而被覆的树脂，则所有的树脂就全部可以采用。另外，作为导电图形11A～11D，可以使用以Cu为主材料的导电箔、以Al为主材料的导电箔、或Fe-Ni合金、Al-Cu的集层体和Al-Cu-Al的集层体等。当然，也可以是其他的导电材料，特别是最好是可以进行蚀刻的导电材料和通过激光照射而蒸发的导电材料。另外，若考虑半蚀刻性、电镀的形成性和热应力时，最好是以通过轧制而形成的Cu为主材料的导电材料。
在本发明中，由于绝缘性树脂10和绝缘性粘接物质AD也填充到上述分离沟15中，所以，具有可以防止导电图形脱落的特征。另外，作为蚀刻，通过采用干腐蚀或湿腐蚀进行非各向异性的蚀刻，使焊区11A…的侧面成为弯曲结构，也可以产生制动效果。结果，可以实现导电图形11A～11D不会从绝缘性树脂10脱出的结构。
而且，导电图形11A～11D的背面从组件的背面露出。因此，放热用的电极11D的背面与装配基板上的电极固定，利用该结构，从半导体元件12发生的热可以向装配基板上的电极放热，从而可以防止半导体元件12的温度上升，增大半导体元件12的驱动电流。另外，放热用的电极11C与半导体元件12也可以电气连接。
本半导体装置由作为封装树脂的绝缘性树脂10支持导电图形11A～11D，所以，不需要支持基板。该结构是本发明的特征。如在先有技术部分说明的那样，先有的半导体装置的导电路由支持基板(软性板、印刷电路板或陶瓷板)支持，或由引线框支持，所以，附加了本来并不需要的结构。但是，本电路装置由所需最小限度的结构要素构成，不需要支持基板，成为薄型、轻量的装置而且不需要材料费，所以，具有廉价的特征。
另外，在组件的背面露出导电图形11A～11D。若将例如焊锡等焊料被覆到该区域时，由于放热用的电极11D的面积大，所以，焊料将浸润上厚厚的一层。因此，固定到装配基板上时，外部连接电极11C背面的焊料浸润不到装配基板上的电极上，从而将发生接触不良的现象。
为了解决这一问题，在半导体装置15的背面形成绝缘被覆膜16。在图1A中所示的虚线的O表示从绝缘被覆膜16露出的外部连接电极11C…、放热用的电极11D。即，在该O以外由绝缘被覆膜16所覆盖，O部分的尺寸实际上是相同的尺寸，所以，在该处形成的焊料的厚度实际上是相同的。这在焊锡印刷后和反流焊接后也是一样的。另外，对于Ag、Au、Ag-Pd等导电胶可以说也是一样的。利用该结构，还可以抑制电气的接触不良。另外，考虑到半导体元件的放热性，放热用的电极11D的露出部17可以形成为比外部连接电极11C的露出尺寸大的尺寸。另外，由于外部连接电极11C…实际上全部是相同的尺寸，所以，外部连接电极11C…在全部区域露出，而放热用的电极11D的背面的一部分也可以从绝缘被覆膜16以实际上相同的尺寸露出。
另外，通过设置绝缘被覆膜16，可以使设置在装配基板上的配线延伸到本半导体装置的背面。通常，设置在装配基板上的配线在上述半导体装置的固定区域中迂回地配置，但是，通过形成上述绝缘被覆膜16，就可以不迂回地进行配置。而且，由于绝缘性树脂10和绝缘性粘接物质AD比导电图形突出，所以，可以在装配基板侧的配线与导电图形之间形成间隙，从而可以防止发生短路现象。
实施例2。本制造方法是表示图1的半导体装置15的制造方法，图2～图6是与图1A的A-A线对应的剖面图。
首先，如图2那样准备导电箔20。厚度最好约为10μm～300μm，这里，采用70μm的轧制铜箔。然后，在该导电箔20的表面，作为耐蚀刻掩膜，形成导电被覆膜21或感光性树脂。该图形是和图1A的焊区11A…、配线11B…、外部连接电极11C…、放热用的电极11D…相同的图形。另外，采用感光性树脂取代导电被覆膜21时，在感光性树脂的下层，在至少与焊区对应的部分形成Au、Ag、Pd或Ni等导电被覆膜。这是为了可以进行焊接而设置的。(以上，参见图2)
然后，通过上述导电被覆膜21或感光性树脂对导电箔20进行半蚀刻。蚀刻的深度只要比导电箔20的厚度浅就可以了。蚀刻的深度越浅，越可以形成微细图形。
并且，通过进行半蚀刻，导电图形11A～11D在导电箔20的表面呈现为凸起状。如前所述，这里采用以通过轧制而形成的Cu为主材料的Cu箔作为导电箔20。但是，也可以是由Al构成的导电箔、由Fe-Ni合金构成的导电箔、Cu-Al的集层体和Al-Cu-Al的集层体。特别是Al-Cu-Al的集层体可以防止由于热膨胀系数的差别而发生的翘起。
并且，在图1的虚线对应的部分形成绝缘性粘接物质AD。该绝缘性粘接物质AD设置在放热用的电极11D与外部连接电极11C的分离沟14、放热用的电极11D与配线11B之间的分离沟14以及它们之上。(以上，参见图3)
然后，将半导体元件12固定到设置了绝缘性粘接物质AD的一个区域中，将半导体元件12的焊接电极13与焊区11A电气连接。图中，半导体元件12是面朝上装配的，所以，作为连接部件，采用金属细线14。
在焊接中，由于焊区11A…与导电箔20是一体的，而且导电箔20的背面是平面，所以，与焊接机器的台面是面接触。因此，如果导电箔20完全固定到焊接台上，就不会发生焊区11A…的位置偏离，从而可以使焊接能量有效地向金属细线14和焊区11A…传导。因此，连接时可以提高金属细线14的固定强度。焊接台的固定，可以通过例如在整个台面上设置多个真空吸引孔而实现。另外，也可以从上面挤压导电箔20。
另外，不采用支持基板就可以装配半导体元件，从而可以将半导体元件12的高度配置得很低。因此，可以使后面所述的组件的外形的厚度变薄。(以上，参见图4)
并且，形成绝缘性树脂10，用以覆盖通过半蚀刻而形成的导电图形11A～11D…、半导体元件12和金属细线14。作为绝缘性树脂，可以是热可塑性树脂和热硬化性树脂中的任何一种。
另外，可以通过转移模塑、注入模塑、浸渍法或涂布法而实现。作为树脂材料，可以利用转移模塑实现环氧树脂等热硬化性树脂，利用注入模塑可以实现液晶聚合物、硫化聚苯等热可塑性树脂。
在本实施例中，绝缘性树脂的厚度调整为从金属细线14的顶部开始在其上被覆约100μm。考虑半导体装置的强度，该厚度可厚可薄。
在树脂注入中，导电图形11A～11D与薄片状的导电薄20成为一体，所以，只要导电薄20没有错位，就完全不会发生导电图形11A～11D的位置偏离。
以上，是作为凸起部而形成的导电图形11A～11D和半导体元件12埋入到绝缘性树脂10中，比凸起部低的导电箔20在背面露出。(以上，参见图5)
然后，去除在上述绝缘性树脂10的背面露出的导电箔20，从而将导电图形11A～11D一个一个地分离。
该分离工序可以考虑各种各样的方法，可以通过蚀刻去除背面而进行分离，也可以通过研磨或切削方法进行分离。另外，也可以两种方法都采用。例如，通过切削而露出绝缘性树脂10时，导电箔20的切削渣和薄薄地延伸到外侧的金属毛刺将侵入到绝缘性树脂10或绝缘性粘接物质AD中。因此，如果通过蚀刻而将焊区11A…分离，导电箔20的金属就不会侵入到位于导电图形11A～11D之间的绝缘性树脂10或绝缘性粘接物质AD的表面。这样，便可防止微细间隔的导电图形11A～11D之间的短路。(以上，参见图5)。
另外，在成为半导体装置15的1个单元形成多个时，在该分离工序之后，应增加切割工序。
这里，采用切割装置进行一个一个地分离，但是，也可以利用分割、冲压或剪切方法。
这里，分离后在背面露出的导电图形11A～11D上形成绝缘被覆膜16，在绝缘被覆膜16上刻制图形，用以露出由图1A的虚线圆圈表示的部分。并且，在此之后，在由箭头所示的部分进行切割而获得半导体装置。
焊锡21可以在切割之前或切割之后形成。
利用上述制造方法，可以实现导电图形和半导体元件埋入到绝缘性树脂中的轻、薄而短小的组件。
图3～图4所示的绝缘性粘接物质AD，也可以在半导体元件12分离为一个一个之前的晶片的阶段进行相互粘贴。即，在晶片的阶段，在晶片背面形成薄片状的粘接剂，在进行切割时，如果与薄片一起将晶片切断，就不需要图3的工序所示的在导电箔20上形成绝缘性粘接物质AD的工序。
图7是表示在导电箔20上形成的导电图形的图。这里，在纵向形成4个单元，在横向形成8个单元，成为引线框的形状。
30A、30B是表示切割线的位置的标志，切割刀片配置在这两条线之间，从而分离为一个一个的半导体装置。另外，31、32是定位标志。由33A、33B所示的L型的线表示芯片的角部。芯片的角部配置并固定到该角部。
下面，说明利用上述制造方法所发生的效果。
首先，第1，导电图形被进行半蚀刻，与导电箔成为一体而被支持，所以，可以去掉以往作为支持用所使用的基板。
第2，在导电箔上，形成通过半蚀刻而成为凸起部的焊区，所以，可以实现焊区的微细化。因此，可以缩小宽度和间隔，从而可以形成平面尺寸更小的组件。
第3，由于由导电图形、半导体元件、连接材料和封装材料构成，所以，可以由所需最小限度的要素构成，可以尽可能去掉不必要的材料，从而可以实现大幅度地降低成本的薄型的半导体装置。
第4，焊区通过半蚀刻形成为凸起部，在封装之后进行一个一个地分离，所以，不需要系杆和悬吊引线。因此，在本发明中完全不需要形成系杆(悬吊引线)和剪切系杆(悬吊引线)。
第5，成为凸起部的导电图形埋入到绝缘性树脂中后，从绝缘性树脂的背面除去导电箔，分离出导电图形，所以，可以消除以往引线框那样在引线与引线之间发生的树脂缝脊。
第6，半导体元件通过绝缘性粘接物质与放热用的电极固定，该放热用的电极从背面露出，所以，可以有效地从本半导体装置的背面将本半导体装置发生的热放出。此外，通过将Si氧化膜或氧化铝等填充物混入绝缘性粘接物质中，可以进一步提高其放热性。另外，如果将填充物的尺寸统一，便可使半导体元件12与导电图形的间隙保持一定。
实施例3.
图8表示本半导体装置42。图8A是其平面图，图8B是沿A-A线的剖面图。
在图1中，配线11B、外部连接电极11C与焊区11A一体地形成，但是，这里，焊区11A的背面成为外部连接电极。
另外，由于焊区11A的背面为矩形，所以，从绝缘被覆膜16露出的图形也形成为与上述矩形相同的图形。另外，考虑绝缘性粘接物质AD的粘接性，形成分离沟43，用以将放热用的电极11D分割为多个。
根据上述说明可知，在本发明中，不采用支持基板，形成为岛状的导电图形也可以将由具有一定厚度的导电箔埋入到绝缘性粘接物质和绝缘性树脂中而构成。另外，由于位于半导体元件的背面的放热用的电极露出，所以，可以改善半导体元件的放热性。而且，由于不采用支持基板，所以，可以实现薄型而轻量的组件。
另外，由导电图形、半导体元件和绝缘性树脂等所需最小限度的结构要素构成，从而成为没有资源浪费的电路装置。因此，直至完成组件为止没有多余的构成要素，从而可以实现能够大幅度地降低成本的半导体装置。

Claims (9)

1.一种半导体装置，其特征在于：具有与半导体元件的焊接电极对应地设置的焊区、设置在上述半导体元件的配置区域中的放热用的电极、设置在上述放热用的电极上的绝缘性粘接物质、固定在上述绝缘性粘接物质上的与上述焊区电气连接的上述半导体元件和露出上述焊区的背面和上述绝缘性粘接物质而一体化地封装上述半导体元件的绝缘性树脂。
2.按权利要求1所述的半导体装置，其特征在于：上述绝缘性粘接物质是粘接薄片或粘接剂。
3.按权利要求1或权利要求2所述的半导体装置，其特征在于：上述半导体元件以面朝上的方式进行装配，上述焊区和上述焊接电极用金属细线连接。
4.一种半导体装置，其特征在于：具有包围一个区域而设置的多个焊区、与上述焊区一体地延伸的外部连接电极、设置在上述一个区域中的放热用的电极、设置在上述放热用的电极上的绝缘性粘接物质、通过上述绝缘性粘接物质而固定的半导体元件、将上述半导体元件上的焊接电极与上述焊区连接的金属细线、被覆到上述半导体元件、上述焊区、上述放热用的电极、上述外部连接电极和上述金属细线上并露出上述外部连接电极的背面、上述放热用的电极的背面和上述绝缘性粘接物质的背面的绝缘性树脂。
5.一种半导体装置，其特征在于：具有包围一个区域而设置的多个焊区、设置在上述一个区域中的放热用的电极、设置在上述放热用的电极上的绝缘性粘接物质、通过上述绝缘性粘接物质而固定的半导体元件、将上述半导体元件上的焊接电极与上述焊区连接的连接部件、被覆到上述半导体元件、上述焊区和上述连接部件上并且露出上述焊区的背面和上述绝缘性粘接物质的背面的绝缘性树脂，将上述焊区的背面作为外部连接电极。
6.按权利要求5所述的半导体装置，其特征在于：上述连接部件是金属细线或焊料。
7.按权利要求1～权利要求6的任一权项所述的半导体装置，其特征在于：上述焊区、焊区或外部连接电极的侧面是弯曲结构。
8.一种半导体装置的制造方法，其特征在于：准备导电箔，将导电图形半蚀刻为凸起状，设置绝缘性粘接物质用以填充通过上述半蚀刻而形成的分离沟，与上述导电图形电气连接并且通过上述绝缘性粘接物质固定半导体元件，在上述导电箔上设置绝缘性树脂用以封装上述半导体元件和上述导电图形，露出上述绝缘性粘接物质的背面，去除上述导电箔的背面而分离出导电图形。
9.一种半导体装置的制造方法，其特征在于：准备导电箔，将至少由焊区和放热用的电极构成的导电图形半蚀刻为凸起状，设置被覆到上述放热用的电极上用以填充到与该电极相邻的分离沟中的绝缘性粘接物质，与上述焊区电气连接并且通过上述绝缘性粘接物质将半导体元件固定到上述放热用的电极上，在上述导电箔上设置绝缘性树脂用以封装上述半导体元件和上述焊区，露出上述绝缘性粘接物质的背面，除去上述导电箔的背面而分离出上述导电图形。
CNB011045531A 2000-09-06 2001-02-15 半导体装置及其制造方法 Expired - Fee Related CN1265451C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP269467/00 2000-09-06
JP2000269467 2000-09-06

Publications (2)

Publication Number Publication Date
CN1341962A true CN1341962A (zh) 2002-03-27
CN1265451C CN1265451C (zh) 2006-07-19

Family

ID=18756068

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB011045531A Expired - Fee Related CN1265451C (zh) 2000-09-06 2001-02-15 半导体装置及其制造方法

Country Status (5)

Country Link
US (2) US6462418B2 (zh)
EP (1) EP1187203A3 (zh)
KR (1) KR100407595B1 (zh)
CN (1) CN1265451C (zh)
TW (1) TW501382B (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1301044C (zh) * 2003-09-30 2007-02-14 三洋电机株式会社 电路装置
CN1303852C (zh) * 2002-06-12 2007-03-07 威盛电子股份有限公司 导线架封装体的散热结构及提高该封装体散热性的方法
CN1307714C (zh) * 2002-11-25 2007-03-28 恩益禧电子股份有限公司 树脂密封型半导体器件及用于生产这种半导体器件的生产工艺
CN110382224A (zh) * 2017-01-16 2019-10-25 日进材料股份有限公司 附有载体箔的超薄铜箔

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3420153B2 (ja) * 2000-01-24 2003-06-23 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP3883784B2 (ja) * 2000-05-24 2007-02-21 三洋電機株式会社 板状体および半導体装置の製造方法
JP3609737B2 (ja) * 2001-03-22 2005-01-12 三洋電機株式会社 回路装置の製造方法
TW538658B (en) * 2001-08-27 2003-06-21 Sanyo Electric Co Manufacturing method for circuit device
DE10148120B4 (de) * 2001-09-28 2007-02-01 Infineon Technologies Ag Elektronische Bauteile mit Halbleiterchips und ein Systemträger mit Bauteilpositionen sowie Verfahren zur Herstellung eines Systemträgers
JP2004186362A (ja) * 2002-12-03 2004-07-02 Sanyo Electric Co Ltd 回路装置
SG119185A1 (en) 2003-05-06 2006-02-28 Micron Technology Inc Method for packaging circuits and packaged circuits
US7488565B2 (en) * 2003-10-01 2009-02-10 Chevron U.S.A. Inc. Photoresist compositions comprising diamondoid derivatives
JP4446772B2 (ja) * 2004-03-24 2010-04-07 三洋電機株式会社 回路装置およびその製造方法
JP4489485B2 (ja) 2004-03-31 2010-06-23 株式会社ルネサステクノロジ 半導体装置
US8022532B2 (en) * 2005-06-06 2011-09-20 Rohm Co., Ltd. Interposer and semiconductor device
JP5081578B2 (ja) 2007-10-25 2012-11-28 ローム株式会社 樹脂封止型半導体装置
US7727813B2 (en) * 2007-11-26 2010-06-01 Infineon Technologies Ag Method for making a device including placing a semiconductor chip on a substrate
US9276336B2 (en) 2009-05-28 2016-03-01 Hsio Technologies, Llc Metalized pad to electrical contact interface
WO2014011232A1 (en) 2012-07-12 2014-01-16 Hsio Technologies, Llc Semiconductor socket with direct selective metalization
WO2011153298A1 (en) 2010-06-03 2011-12-08 Hsio Technologies, Llc Electrical connector insulator housing
US8955215B2 (en) 2009-05-28 2015-02-17 Hsio Technologies, Llc High performance surface mount electrical interconnect
US8525346B2 (en) 2009-06-02 2013-09-03 Hsio Technologies, Llc Compliant conductive nano-particle electrical interconnect
WO2010141295A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed flexible circuit
US9930775B2 (en) 2009-06-02 2018-03-27 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
WO2010141313A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit socket diagnostic tool
US9196980B2 (en) 2009-06-02 2015-11-24 Hsio Technologies, Llc High performance surface mount electrical interconnect with external biased normal force loading
US9277654B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Composite polymer-metal electrical contacts
US8789272B2 (en) 2009-06-02 2014-07-29 Hsio Technologies, Llc Method of making a compliant printed circuit peripheral lead semiconductor test socket
US9613841B2 (en) 2009-06-02 2017-04-04 Hsio Technologies, Llc Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection
US9136196B2 (en) 2009-06-02 2015-09-15 Hsio Technologies, Llc Compliant printed circuit wafer level semiconductor package
US9184145B2 (en) 2009-06-02 2015-11-10 Hsio Technologies, Llc Semiconductor device package adapter
US9699906B2 (en) 2009-06-02 2017-07-04 Hsio Technologies, Llc Hybrid printed circuit assembly with low density main core and embedded high density circuit regions
US8610265B2 (en) 2009-06-02 2013-12-17 Hsio Technologies, Llc Compliant core peripheral lead semiconductor test socket
WO2010141316A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit wafer probe diagnostic tool
US9603249B2 (en) 2009-06-02 2017-03-21 Hsio Technologies, Llc Direct metalization of electrical circuit structures
US9318862B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Method of making an electronic interconnect
US8618649B2 (en) 2009-06-02 2013-12-31 Hsio Technologies, Llc Compliant printed circuit semiconductor package
US9276339B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Electrical interconnect IC device socket
WO2010147934A1 (en) * 2009-06-16 2010-12-23 Hsio Technologies, Llc Semiconductor die terminal
US9054097B2 (en) 2009-06-02 2015-06-09 Hsio Technologies, Llc Compliant printed circuit area array semiconductor device package
US8988093B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Bumped semiconductor wafer or die level electrical interconnect
US8955216B2 (en) 2009-06-02 2015-02-17 Hsio Technologies, Llc Method of making a compliant printed circuit peripheral lead semiconductor package
WO2012074963A1 (en) 2010-12-01 2012-06-07 Hsio Technologies, Llc High performance surface mount electrical interconnect
WO2012061008A1 (en) 2010-10-25 2012-05-10 Hsio Technologies, Llc High performance electrical circuit structure
US9320133B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Electrical interconnect IC device socket
WO2010141264A1 (en) 2009-06-03 2010-12-09 Hsio Technologies, Llc Compliant wafer level probe assembly
US9231328B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc Resilient conductive electrical interconnect
US8987886B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
US8981568B2 (en) 2009-06-16 2015-03-17 Hsio Technologies, Llc Simulated wirebond semiconductor package
US9320144B2 (en) 2009-06-17 2016-04-19 Hsio Technologies, Llc Method of forming a semiconductor socket
US8984748B2 (en) 2009-06-29 2015-03-24 Hsio Technologies, Llc Singulated semiconductor device separable electrical interconnect
US8981809B2 (en) 2009-06-29 2015-03-17 Hsio Technologies, Llc Compliant printed circuit semiconductor tester interface
US8758067B2 (en) 2010-06-03 2014-06-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US9350093B2 (en) 2010-06-03 2016-05-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US10159154B2 (en) 2010-06-03 2018-12-18 Hsio Technologies, Llc Fusion bonded liquid crystal polymer circuit structure
US9689897B2 (en) 2010-06-03 2017-06-27 Hsio Technologies, Llc Performance enhanced semiconductor socket
US9761520B2 (en) 2012-07-10 2017-09-12 Hsio Technologies, Llc Method of making an electrical connector having electrodeposited terminals
US10667410B2 (en) 2013-07-11 2020-05-26 Hsio Technologies, Llc Method of making a fusion bonded circuit structure
US10506722B2 (en) 2013-07-11 2019-12-10 Hsio Technologies, Llc Fusion bonded liquid crystal polymer electrical circuit structure
US9559447B2 (en) 2015-03-18 2017-01-31 Hsio Technologies, Llc Mechanical contact retention within an electrical connector

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437436B1 (ko) 1994-03-18 2004-07-16 히다치 가세고교 가부시끼가이샤 반도체패키지의제조법및반도체패키지
JP3509274B2 (ja) * 1994-07-13 2004-03-22 セイコーエプソン株式会社 樹脂封止型半導体装置およびその製造方法
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
JPH09312355A (ja) * 1996-05-21 1997-12-02 Shinko Electric Ind Co Ltd 半導体装置とその製造方法
JPH10335566A (ja) * 1997-04-02 1998-12-18 Dainippon Printing Co Ltd 樹脂封止型半導体装置とそれに用いられる回路部材、および樹脂封止型半導体装置の製造方法
US6201292B1 (en) * 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
JP3521758B2 (ja) * 1997-10-28 2004-04-19 セイコーエプソン株式会社 半導体装置の製造方法
JPH11195742A (ja) * 1998-01-05 1999-07-21 Matsushita Electron Corp 半導体装置及びその製造方法とそれに用いるリードフレーム

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1303852C (zh) * 2002-06-12 2007-03-07 威盛电子股份有限公司 导线架封装体的散热结构及提高该封装体散热性的方法
CN1307714C (zh) * 2002-11-25 2007-03-28 恩益禧电子股份有限公司 树脂密封型半导体器件及用于生产这种半导体器件的生产工艺
CN1301044C (zh) * 2003-09-30 2007-02-14 三洋电机株式会社 电路装置
CN110382224A (zh) * 2017-01-16 2019-10-25 日进材料股份有限公司 附有载体箔的超薄铜箔
US11166378B2 (en) 2017-01-16 2021-11-02 Iljin Materials Co., Ltd. Carrier-foil-attached ultra-thin copper foil

Also Published As

Publication number Publication date
US6596564B2 (en) 2003-07-22
KR20020020169A (ko) 2002-03-14
US20030011065A1 (en) 2003-01-16
US6462418B2 (en) 2002-10-08
US20020027290A1 (en) 2002-03-07
CN1265451C (zh) 2006-07-19
EP1187203A2 (en) 2002-03-13
KR100407595B1 (ko) 2003-12-01
TW501382B (en) 2002-09-01
EP1187203A3 (en) 2004-04-14

Similar Documents

Publication Publication Date Title
CN1265451C (zh) 半导体装置及其制造方法
JP5442368B2 (ja) 直付リード線を備えるｉｃチップパッケージ
KR960003766B1 (ko) 플래스틱 핀 그리드 어레이 패키지 제조 방법
JP4850184B2 (ja) 標準占有面積を含む半導体ダイパッケージ及びその製造方法
US7812442B2 (en) High-power ball grid array package, heat spreader used in the BGA package and method for manufacturing the same
US9130064B2 (en) Method for fabricating leadframe-based semiconductor package with connecting pads top and bottom surfaces of carrier
CN1104741C (zh) 半导体封装及其制造方法
CN1309283C (zh) 电路装置的制造方法
CN1571151A (zh) 双规引线框
US6696310B2 (en) Manufacturing method of lighting device
CN1266765C (zh) 半导体装置及其制造方法
CN103367300A (zh) 引线框、半导体装置以及引线框的制造方法
KR100606295B1 (ko) 회로 모듈
US7867908B2 (en) Method of fabricating substrate
JP2001085603A (ja) 半導体装置
JPH09326450A (ja) 半導体装置およびその製造方法
JPH06132441A (ja) 樹脂封止型半導体装置及びその製造方法
KR101008534B1 (ko) 전력용 반도체모듈패키지 및 그 제조방법
JP2002270711A (ja) 半導体装置用配線基板およびその製造方法
JP4994883B2 (ja) 樹脂封止型半導体装置
JP2504262Y2 (ja) 半導体モジュ―ル
JP2002026180A (ja) 回路装置の製造方法
KR19980015389A (ko) 서포트 링을 이용한 tab(tape automated bonding) lga(land grid array) 패키지
JPH09213841A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20060719

Termination date: 20140215