TW501382B - Semiconductor device and process therefor - Google Patents
Semiconductor device and process therefor Download PDFInfo
- Publication number
- TW501382B TW501382B TW90103573A TW90103573A TW501382B TW 501382 B TW501382 B TW 501382B TW 90103573 A TW90103573 A TW 90103573A TW 90103573 A TW90103573 A TW 90103573A TW 501382 B TW501382 B TW 501382B
- Authority
- TW
- Taiwan
- Prior art keywords
- electrode
- aforementioned
- conductive
- pad
- semiconductor element
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Measurement Of Radiation (AREA)
Description
A7 A7 經濟部智慧財產局員工消費合作社印製 1 五、發明說明(1 [發明所屬技術領域] 、♦本發明係有關-種半導體裝置及其製造方法,尤指能 將半導體7G件所產生之熱量有效地散放出去之半導體裝置 及其製造方法。 [習知之技術] 近年1C封裝體逐漸被攜帶機器、小型•高密度安裝 機器所採用,以往之10:封裝及其安裝概念也產生巨大變 化。詳細内容刊登於諸如電子材料(1998年9月號22頁〜) 「CSP技術及支援該技術之安裝材料·裝置」特集。 第9圖係採用撓性片5G為中介基板之例子,透過黏著 劑將銅箔圖案51黏貼固定於此撓性片5〇上,並將IC晶片 52固定。另外,此導電圖案51具有搭接用焊墊^形成於 此1C晶片52周圍。又,透過與此搭接用焊墊53形成一體 之配線51B構成焊球連接墊54。 此外,於焊球連接墊54背面設置有開口於撓性片之開 口部56,透過此開口部56形成焊球55。且,以撓性片5〇 為基板,用絕緣性樹脂58將全體密封住。 I發明欲解決之問題] 然而,設置於1C晶片52背面之撓性片5〇,價格非常 昂貴,導致成本上升,且有增加封裝體厚度以及增加重量 之問題產生。 且,支持基板係由金屬以外的材料構成,導致熱能從 1C晶片背面傳達於封裝體背面之阻力增高之問題發生。前 述支持基板為撓性片、陶瓷基板或印刷基板。又,熱傳導 ^紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 312151 (請先閱讀背面之注意事項再填寫本頁)
2 A7 _B7 五、發明說明(2 良好材料製造之熱傳導路徑為金屬細線57、銅箔51及焊 球55,此構造於驅動時無法充分散熱,故導致驅動時,會 有1C晶片溫度上升,無法讓驅動電流順暢流動之問題產 生。 [解決問題之方案] 本發明係鑑於前述問題而開發者,第1解決方案具 有·對應半導體元件之搭接電極而設置之焊墊;設於前逑 半導體70件之配置領域之散熱用電極;設置於前述散熱用 電極上之絕緣性黏著機構;固定於前述絕緣性黏著機構, 且與則述焊墊電性連接之前述半導體元件;以及,密封前 述半導體元件使其一體化,且使前述焊墊背面與前述絕緣 性黏著機構露出之絕緣性樹脂。 第2解決方案中,前述絕緣性黏著機構可為黏著片或 黏著劑。 第3解決方案,其中,前述半導體元件係以面朝上方 弋女裝刚述知墊及刚述搭接電極係由金屬細線連接。 第4解決方案具備:設置包圍一領域之數個焊墊;盘 前述搭接塾一體化而延伸之外部連接電極;設置於前述 領域之散熱用電極;設置於前述散熱用電極之絕緣性黏著 機構,藉由剛述絕緣性黏著機構而固定之半導體元件;連 接續前述半導體元件上之搭接電極與前述搭接墊之金屬細 線’以及’覆盖前述半導體元件、前述搭接塾、前述散熱 用電極、前述外部連接電極與前述金屬細線,且讓前料 部連接電極背面、前述散熱用電極背面與前述絕緣性黏著 本雌尺度顧中關家· 312151 .——Μ.--------^---------線 (請先閱讀背面之注意事項再填寫本頁) B7 B7 消 五、發明說明(3 機構背面露出之絕緣性樹脂。 *第5解決方案之半導體裳置具備:包圍一領域之方式 ^Ϊ數個焊墊;於前述—領域所設置之散熱用電極;設 =述散熱用電m緣性㈣機構;藉 性黏著機構固定之半導體元件;連接前述半導體元件上邑= =電極與前述焊塾之連接手段;覆蓋前述半導體元件、 接墊及前料接手段,且使前述搭接墊背面及前述 絕緣性黏著機構露出之絕緣性樹脂, f將前述搭接墊背面做為外部連接電極。 =6解決方案中’前述連接機構為金屬細線或谭封 第7解決方案中,前述焊墊、 之側面係以f曲構造形成。 連接電! ^解決方案之半導體裝置製造方法係包 治,=行半钱刻,使導電圖案形成凸狀’· 設置絕緣性黏著機構,# 乂 之隔離溝; ㈣I之填充於刖述半钱刻所形居 與前述導電圖案電性連接,並藉由前 構固定半導體元件; 豕注黏者機 件!=導電落上設置絕緣性樹脂,係將前述半導體天 件、刚述導電圖案密封;以及, 使前述絕緣性黏著機構背面露出,將前述導 除去,分離成為導電圖案。 / 第9解決方案之半導體裝置之製造方法 塾跟散熱用電極形 本&尺度樹 312151 (請先閱讀背面之注音?事項再填寫本頁)
3 501382 A7 __B7 五、發明說明G 電圖案形成凸狀; 覆蓋前述散熱用電極,机罟 + & 置絕緣性黏著機構,傕之埴 充與此電極鄰接之隔離溝; 傅便之填 (請先閱讀背面之注音?事項再填寫本頁) 與前述焊墊做電性連接,並笋 構,將丰墓夢开杜门 藉由刚述絕緣性黏著機 冓將丰導體70件固定於前述散熱用電極上; 於刖述導電箱上設置絕緩姓格^ ►及前述焊塾密封4 料’將前述半導體元件 前述絕緣性黏著機構背面露出,且去除前述導電落背 面,使前述導電圖案分離。 藉由本半導體裝置,可以讓半導體元件的熱傳到散熱 用電m含於此散熱用電極之導電圖案之構造乃不 採用支持基板即可形成,故可降低成本,並減少半導體裝 置之厚度。 [發明之實施型態] > 兹說明半導體裝置之第i實施型態。 經濟部智慧財產局員工消費合作社印製 首先,本發明之半導體裝置之說明係參考第1圖。第 1圖A為半導體裝置之俯視圖,第1圖b為a—A線之剖 視圖。 第1圖係以下構成要件埋入於絕緣性樹脂1 〇之圖。亦 即,埋入有·搭接塾11···,與此搭接塾11A…/體之配衮 11B;設於此配線πβ之另端,且與配線11B形成一體之 外部連接電極11C。此外尚埋入有··設於此導電圖案11/ 至11C所包圍之一領域裡之散熱用電極no;及設於此黄 熱用電極11D上之半導體元件12。另外,半導體元件12 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐 31215] 501382 A7 五、發明說明(5 ) 透過絕緣性黏著機構AD而與前述散熱用電極11D固接, 其為第1圖A中用虛線表現之部分。 (請先閱讀背面之注意事項再填寫本頁) 此外’半導體元件12之搭接電極13與搭接墊11係透 過金屬細線14電性連接。 則述之搭接墊11A…的側面進行非各向異性餘刻,此 處乃採用濕式蝕刻法形成,故具有彎曲構造,藉此彎曲構 造會發生錨定效果。 本構造係由:半導體元件12;複數導電圖案11A至 11C與散熱用電極11D ;及絕緣性黏著機構ad,以及埋設 上述元件之絕緣性樹脂10等4種材料所構成。在半導體 12之配置領域中,於導電圖案11B至11D上及其間形成有 刖述絕緣性黏著機構AD,尤其在姓刻所形成之隔離溝^ 5 亦設有前述之絕緣性黏著機構AD,且露出背面。其次, 用絕緣性樹脂10將這些全都封裝,並藉此絕緣性樹脂ι〇 支持前述搭接墊11A…、半導體元件12。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 絕緣性黏著機構最好採用絕緣材料製造之黏著劑、黏 著性之絕緣片。再者,從後述的製造方法可以报明確地知 道,最好採用可黏貼於整體晶圓’且可用微影法形成圖案 之材料。絕緣性樹脂可為環氧樹脂等熱硬化性樹脂、聚醯 亞胺樹脂、聚硫苯等熱塑性樹月旨。又,絕緣性樹脂只要是 可用金屬模固定之樹脂,或可用浸潰或塗佈覆蓋之樹脂均 可。導電圖案11A至HD可用以Cu為主材料之導電猪、 以A1為主材料之導電镇、或Fe_犯 σ金、A1 — Cii之疊 層體、A1〜Cu_A12疊層體。當然, __ ,、他導電材料也可 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 x 297公釐) D 312151 經濟部智慧財產局員工消費合作社印製 501382 A7 '— ------丨丨 ---^ _____ 五、發明說明(6 ) 以,特別是可蝕刻之導電材料或可用雷射蒸發之導電材料 尤佳。另外,若考慮到半蝕刻性、電鍍之形成性及熱應力, 則最好採用壓延所形成之Cu為主材料之導電材料。 本發明中,前述隔離溝15亦填充前述絕緣性樹脂ι〇 及絕緣性黏著機構AD,故有可以防止導電圖案脫落之特 徵。此外’蝕刻法係採用乾式蝕刻法或濕式蝕刻法,進行 非各向異性之蝕刻,故搭接墊UA…的側面產生彎曲構 造,而發生錨定之效果。此項結果可提供導電圖案UA至 11D無法從絕緣性樹脂1 〇掉落的構造。 且,導電圖案11A至11D背面係露出於封裝體背面。 故,散熱用電極11D之背面可以固接在安裝基板上之電 極,藉此構造,將半導體元件12產生的熱即可放熱到安裝 基板上的電極,防止半導體元件12的溫度上升,並可增強 半導體元件12的驅動電流。且,散熱用電極uc跟半導 丨體元件12亦可以電性連接。 本半導體裝置係由密封導電圖案11A至UD之絕緣性 樹脂10支持,故不需支持基板。此構造為本發明之特徵。 如在習知技術部分所說明者,習知之半導體裝置的導電路 係以支持基板(撓性片、印刷基板或陶瓷基板)或引線架支 撐,故增加了本來不需要之構造。然而,本電路裝置由於 用最小必要限度之構成元件所構成,不用支持基板,故有 可達到型薄、量輕之效果,且因材料費少,價格亦可壓低 之特點。 之外,導電圖案11 A至11D露出於封裝體背面。若以 ^--------^---------^ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公餐) 6 312151 A7 五、發明說明(7 ) 例如焊錫等焊材覆蓋 後因散熱用電極1 ID之面籍 恨大,焊材要厚。故,固接 Μ ^ ^ ^ 接在女裝基板時,可預料到會右 ^ 之烊材無法延伸至安裝基板上之雷 極而發生連接不良之缺點。電 解決上述缺點之辦法,乃在 絕緣被覆膜16。g 1回 牛導體裝置15 ♦面形成 i 、 回A上之虛線〇即為從絕緣被覆膜 =出之外部連接電極11C···、散熱用電極UD。亦即、, 之外的部位都被絕緣被覆臈16覆蓋。〇部分的 質上為相同尺寸,故,於未 了故於此處形成之焊材厚度實質上一樣, p使焊料印刷後、迴焊後也—樣。此外,Ag、Au、八卜
Pd等之導電糊可說亦相同。此構造可以抑制不良之 接。散熱用電極UD之露出部17,因考慮到半導體元件之 )± %出。(5分尺寸可以比外部連接電極的露出部 還要大。此外,外部連接電極llc...的尺寸實質上全部一 樣,因而外部連接電極nc...可全部領域皆露出,散熱用 電極11D之部分背面實質上以相同尺寸露出於絕緣被 1 6亦可。 另外,因設置絕緣被覆膜16,故,安裝基板上所設置 之配線可延伸到本半導體裝置之背自。一般情況,設於安 裝基板側之配線之配置須迂迴到前述半導體裝置之固接領 域,但,因有前述絕緣被覆膜16之形成,就不用迂迴可直 接配置。且,絕緣性樹脂1 〇、絕緣性黏著機構AD比導電 圖案還要突出’安裝基板側之配線跟導電圖案之間會形成 間隙,可防止短路情況發生。 & 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 7 312151 f靖先閱讀背面之注音?事項再填寫本頁} I-裝--------訂: 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 1· n n · A7 五、發明說明(8 ) 其次說明本丰邕骑姑 _裝置之製造方法之第 本製造方法係為κ筮 — 實悲。 方法,繁?国丨、、 圖所不之半導體裴置15之製、i 到第6圖為對應第1圖A_ A绫 ^ 首先,章锯‘钕 A線之剖面圖。 至鳥m程度,此處^之導電错2〇,其厚度最好是〜 處係採用7〇um的壓延鋼蠕。姑 此導電自20的表面上形成導電被覆膜2朵。 '’於 蝕刻遮罩。且,此$ 3、阻劑作為耐 皁且此圖案與第i圖A之搭接塾UA...、 、外部連接電極11C.·.散熱用電極1 ID...等為相: :。另:,採用光阻劑代替導電被覆…,: '至(在與搭接墊對應之部分’須形成Μ、岣、
Nl等之導電被覆膜’此這是為了能夠搭接 I 請參考第2圖)。 τ u乂上 其次,介著前述導電被覆膜21或光阻劑對導電落2〇 進行半#刻mi度,只要比導電2Q之厚度㈣可。 餘刻深度越淺,越能形成微細圖案。 接著,藉由半蝕刻讓導電圖案11A至11D在導電落2Q 表面呈現凸出狀。且如前述,導電箔20係採用以由壓延形 成之Cu為主材料之Cu箔,但亦可採用A1形成之導電箔、 Fe-Ni合金製造之導電箔、Cu-Al之疊層體、A1 — Cu_ 八1之疊層體。尤其是A1 — Cu —A1之疊層體可以防止因熱 膨脹係數差異所導致之翹曲。
接著,於第1圖虛線對應部分形成絕緣性黏著機構 AD。此絕緣性黏著機構AD係設置在散熱用電極11D與外 部連接電極11C之隔離溝14、散熱用電極hd與配線11B 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐产、〜- -- 8 312151 面 之 項 再 % 寫 頁 裴 i I I 訂 線 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 A7 五、發明說明(9 間的隔離溝14及其上方。(以上請參考第3圖) 然後,將半導體元件12 鏠 AD的領域上,使半導體…广於叹有絕緣性黏著機構 使丰導體凡件12之搭接電極13與搭接墊 電性連接。时,半導體元件12係為面朝上安裝故 連接機構為採用金屬細線14。 此搭接過程,使搭接墊11Α.·.係與導電落2〇形成一 體,且導電落20背面為平坦狀,故可 接機的台面。故,只要導電…完全固定於;=搭 搭接塾ΠΑ..·的位置即不會偏移,搭接能量可以 傳達給金屬細線14與搭接塾 > 細線之固定強度,提高連接效果 、屬 tl 4沖为 怜接σ之固定,可例如 訂 置夕個真空抽吸孔’或亦可從上屢導電箱21。 使丰==可不需使用支持基板就安裝半導體元件,且 使+導體1件12的配置高度相對應地降低 述之封裝體外型之厚度。(以上請參考第4圖)此了心後 接著,形成絕緣性㈣1G,使之覆蓋由半 之導電圖案11A至UD…、半導體 所/成 絕緣性樹脂可為熱塑性或熱硬導::件12及金屬細線“。 又,絕緣性樹脂之形成可使用轉移模塑法、注入模塑 法、浸潰模塑法或塗佈法達成。樹脂材料可為環氧樹脂等 …硬化性樹脂以轉移模塑法達成,液晶聚合物、聚硫 熱可塑性樹脂則用模塑法達成。 ; 本實施型態中,絕緣性樹脂之厚度,須 蓋住金屬細線頂部以上約1〇um 二整^夠覆 I_____ 此厚度可因考慮半導 本紙張尺度適时關家辟(cns)a4祕(2m97公餐 312151 501382 A7 _B7 五、發明說明(1〇 體裝置之強度而增減。 於樹脂注入時,因導電圖案
沒偏移,導電圖案1J A 箱20成為一體,故只要導電箱20至仙與片狀之導電 至11D就不會移動其位置。 前述絕緣性樹脂〗〇埋嗖 Μ至,半導體元件12:凸部 =凸:'導電圖案 出其背面。(以上請參考第5圖)之電治20則露 接著’將露出前述絕緣性樹脂 去,使導電圖案以至仙―個—個/離面除I寫 此分離工程,有卵夕士、+ 離 、夕法。可用蝕刻除掉背面後分離, 亦可用研磨、研削方法 ^ 訂 切削呈絕緣性樹脂10露 仁 削薄之毛邊野導電泊20的削屑及外側被 又入絕緣性樹腊1〇、絕緣性黏著機構 裡^問題。因此,用㈣分離搭接塾H...時,導 線 電& 20之金屬就不會沒入於導電圖案11A至11D間之絕 緣性樹脂10、絕緣性黏著機構AD的表面上。故,可藉此 防止細小間隔之導電11AS 11D彼此間之短路。(以上9來 經濟部智慧財產局員工消費合作社印製 考第5圖)。 〃 又’半導體裝置15之單元具有複數個時,在此分離步 驟後尚須追加切割步驟。 此處係採用切割裝置使之一個一個分離,但也可以採 用刀塊剝離(Chocolatebreak)、壓斷或剪斷。 然後’於分離後露出背面之導電圖案U A至11D上形 成絕緣被覆膜1 6。使絕緣被覆膜1 6形成圖案,俾使第 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 x 297公釐) A7 五、發明說明(u !二上用虛線圓圈表示的部分露出。接著,於箭頭表示之 邛刀進行切割,完成半導體裝置。 2球21可在切割前或切割後形成。 稭由以上製造方法,可將導電圖案、半導體元件全埋 在、、邑緣性樹脂裡,而完成輕薄短小之封裝體。 另外第3圖至第4圖所表示之絕緣性黏著機構—,
亦可在半導體元件12被一個伽八銳1 R 反個一個分離前之晶圓階段黏 “亦即’在晶圓階段時,於晶圓背面形成片狀黏著劑。 刀口】時晶圓與黏著片一起切斷 刀斷如第3圖工程所示之於導 泊20上形成絕緣性黏著機構AD之工程即可省略。 第7圖係表示於導電簿20上形成之導電圖案。此處係 縱向4個單元’橫向8個單元,形狀如同引線架。 3〇A、30B為切判位署沾诚― ^ 置的輮記,將切割刀置於這二條 分離成-個-個半導體裝置。另外,31、32為對準 曰“己&33Α、33Β所指之L形線為晶片之角部。此角部為 曰日片角部配置固定之處。 以下說明上述製造方法所發生之效果。 第1’導電圖案經由半蝕刻而與導電箔成為一體予以 支持,不須跟以往一樣使用支持基板。 第2’導電箔上藉由半蝕刻而形成突起狀搭接墊,可 將搭接塾微細化。故可縮小寬产 s τ 』見度間隔,而形成平面尺寸 更小之封裝體。 丁 第3,因係由導電圖案、半導 ^ ^ 干等骽70件、連接機構及密 、于材所構成,故可構成為最小 _____ 晋限度儘量減少浪費多 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公g )----------- 11 31215: (請先閱讀背面之注意事項再填寫本頁) FI 1 裝 經濟部智慧財產局員工消費合作社印製
第8圖B為A-A線之剖視圖。 經濟部智慧財產局員工消費合作社印製 第1圖中,配線11B、外部連接電極Uc於搭接墊UA 上形成一體。此處,搭接墊11A之背面為外部連接電極。 且’搭接墊11A背面為形成矩形狀,露出絕緣被覆 膜16之圖案跟前述矩形同一圖案所形成。此外,因考慮到 絕緣性黏著機構AD之固定性而形成溝43,使散熱用電極 UD分割成複數個。 [發明之功效] 從上述說明可以很清楚地知道,本發明即使不採用支 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 12 312151 501382 A7 ___B7 五、發明說明(13 持基板’亦可用有一定厚度之導電落(或導電罐形成於 晶島部上之導電圖案埋入於絕緣性黏著機構及絕緣性樹脂 中。又因,位於半導體元件背面之散熱用電極露出,故可 改善半導體元件之散熱。且因不採用支持基板,故可完成 薄型又輕量之封裝體。 此外,本半導體裝置係由導電圖案、半導體元件及絕 緣樹:之最小必要限度所構成,可成為省資源之線路裝 置,完成前沒有多餘的構成要件,故可大幅降低本。 :[圖面之簡單說明] 第1圖(A)、(B)為本發明之半導體裝置說明圖。 第2圖為本發明半導體裝置之製造方法說明圖。 第3圖為本發明半導體裝置之製造方法說明圖。 第4圖為本發明半導體裝置之製造方法說明圖。 第5圖為本發明半導體裝置之製造方法說明圖。 第6圖為本發明半導體裝置之製造方法說明圖。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 第7圖為本發明半導體裝置所採用之導電圖案說明 圖。 ,、
本Λ張尺度適用中國國家標準(CNs)A4規格⑵“挪公髮 312151 501382 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(Η ) 11Β 、51B 配線 11C 外部連接電極 11D 散熱用電極 12 半導體元件 13 搭接電極 14、 15 隔離溝 > 14、 57 金屬細線 15 半導體裝置 16 > 21 絕緣被覆膜 17 露出部 20 導電箔 21、 55 焊球 30A 、30B 切割位置 3卜 32 對準標記 >43 溝 50 撓性片 51 銅箔圖案 51 導電圖案 52 1C晶片 53 焊墊 54 焊球連接墊 56 開口部 AD 絕緣性黏著機構 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 14 312151
Claims (1)
- 第90103573號專利申請案 申清專利乾圍修正本 j _ (91年5月23曰: ·、種半導體裝置,其特徵在具有:與半導體元件的搭接 電極對應之焊墊;設置於前述半導體元件之配置領域之 散熱用f極,·設置於前述冑熱用電極上之絕緣性黏著機 構L固定於前述絕緣性黏著機構且與前述·燁墊電性連接 之前述半導體元件;以將前述半導體元件密封使其一體 化之方式將前述焊墊與前述絕緣性黏著機構露出之絕 緣性樹脂。 …如申:專利範圍第}項之半導體裝置,其中,前述絕緣 性黏著機構為黏著片或黏著劑。 '· 2申請專利範圍第1項或第2項之半導體裝置,其中, 刖述半導體元件係以面朝上安裝,且前述焊墊與前述搭 接電極係以金屬細線連接。 經濟部中央標準局員工福利委員會印製 4· 一種半導體裝置,其特徵在具備··以包圍一領域之方式 設置之複數個搭接墊;跟前述搭接墊形成一體而延伸之 外部連接電極;設置於前述一領域之散熱用電極;設置 於前述散熱用電極之絕緣性黏著機構;藉由前述絕=性 黏著機構固定之半導體元件;連接前述半導體元件上之 搭接電極與前述搭接墊之金屬細線;以及,覆蓋前述半 導體元件、前述搭接墊、前述散熱用電極、前述外部連 接電極與前述金屬細線,且使前述外部連接電極背面 前述散熱用電極之背面與前述絕緣性黏著機構之背面 本紙張尺度適财國A4規格⑽χ 297^)露出之絕緣性樹脂。 5. -種半導體裝置,其特徵在具借:以㈣—領域之方式 設置之複數料墊;設置於前述—領域之散熱用電極; 設置於前述散熱用電極之絕緣性黏著機構;透過前述絕 緣性黏著機構*固定之半導體元件;連接前述半導體元 件上之搭接電極與前述焊塾之連接機構,n,覆蓋前 述半導體元件、前述搭㈣與前料接手段,且,使前 述搭接墊之背面跟前述絕緣性黏著機構露出之絕緣性 樹脂; 亚以别述搭接墊之背面做為外部連接電極。 6. 如申請專利範圍第5項之半導體裝置,其中,前述連接 機構為金屬細線或焊材。 7. 如申請專利範圍第5項之半導體裝置,其中,前述谭塾、 搭接墊或外部連接電極之側面為彎曲構造所成。 !•一種半導體製造方法,其步驟為:準備導電落,並進行 半钱刻使導電墊成為凸起狀, 在前述半蝕刻所形成之隔離溝中,填充絕緣性黏著 機構; 1 與别述導電圖案電性連接,並透過前述絕緣性 機構使半導體元件固定; 於別述導電Vg上设置絕緣性樹脂,將前述半導體元 件' 前述導電圖案密封; 刖述絕緣性黏著機構背面露出,將前述導電箔之背 面去除,使其當作導電圖案予以分離。 9 H3 一種半導體裝置之絮i止方、土 ^ ^ ^ 裏方法,其步驟為:準備導電箔, 進行半蝕刻,使至少焊墊盥崙敍 /、散",、用電極所形成之導電圖 案形成凸狀; 覆蓋前述散熱用電極,且設置絕緣性黏著機構,填 充與此電極鄰接之隔離溝; 與前述焊墊電性連接,並藉由前述絕緣性黏著機構 將半導體元件固定於前述散熱用電極上; 於前述導電箔上設置絕緣性樹脂,將前述半導體元 件與前述焊墊密封;以及, 月ίι述絕緣性黏著機構背面露出,將前述導電箔背面 去除,使導電圖案分離。經濟部中央標準局員工福利委員會印製 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 3 312151
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000269467 | 2000-09-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW501382B true TW501382B (en) | 2002-09-01 |
Family
ID=18756068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW90103573A TW501382B (en) | 2000-09-06 | 2001-02-16 | Semiconductor device and process therefor |
Country Status (5)
Country | Link |
---|---|
US (2) | US6462418B2 (zh) |
EP (1) | EP1187203A3 (zh) |
KR (1) | KR100407595B1 (zh) |
CN (1) | CN1265451C (zh) |
TW (1) | TW501382B (zh) |
Families Citing this family (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3420153B2 (ja) * | 2000-01-24 | 2003-06-23 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP3883784B2 (ja) * | 2000-05-24 | 2007-02-21 | 三洋電機株式会社 | 板状体および半導体装置の製造方法 |
JP3609737B2 (ja) * | 2001-03-22 | 2005-01-12 | 三洋電機株式会社 | 回路装置の製造方法 |
TW538658B (en) * | 2001-08-27 | 2003-06-21 | Sanyo Electric Co | Manufacturing method for circuit device |
DE10148120B4 (de) * | 2001-09-28 | 2007-02-01 | Infineon Technologies Ag | Elektronische Bauteile mit Halbleiterchips und ein Systemträger mit Bauteilpositionen sowie Verfahren zur Herstellung eines Systemträgers |
CN1303852C (zh) * | 2002-06-12 | 2007-03-07 | 威盛电子股份有限公司 | 导线架封装体的散热结构及提高该封装体散热性的方法 |
JP2004179253A (ja) * | 2002-11-25 | 2004-06-24 | Nec Semiconductors Kyushu Ltd | 半導体装置およびその製造方法 |
JP2004186362A (ja) * | 2002-12-03 | 2004-07-02 | Sanyo Electric Co Ltd | 回路装置 |
SG119185A1 (en) | 2003-05-06 | 2006-02-28 | Micron Technology Inc | Method for packaging circuits and packaged circuits |
JP2005109225A (ja) * | 2003-09-30 | 2005-04-21 | Sanyo Electric Co Ltd | 回路装置 |
US7488565B2 (en) * | 2003-10-01 | 2009-02-10 | Chevron U.S.A. Inc. | Photoresist compositions comprising diamondoid derivatives |
JP4446772B2 (ja) * | 2004-03-24 | 2010-04-07 | 三洋電機株式会社 | 回路装置およびその製造方法 |
JP4489485B2 (ja) | 2004-03-31 | 2010-06-23 | 株式会社ルネサステクノロジ | 半導体装置 |
US8022532B2 (en) * | 2005-06-06 | 2011-09-20 | Rohm Co., Ltd. | Interposer and semiconductor device |
JP5081578B2 (ja) | 2007-10-25 | 2012-11-28 | ローム株式会社 | 樹脂封止型半導体装置 |
US7727813B2 (en) * | 2007-11-26 | 2010-06-01 | Infineon Technologies Ag | Method for making a device including placing a semiconductor chip on a substrate |
WO2010138493A1 (en) | 2009-05-28 | 2010-12-02 | Hsio Technologies, Llc | High performance surface mount electrical interconnect |
US9536815B2 (en) | 2009-05-28 | 2017-01-03 | Hsio Technologies, Llc | Semiconductor socket with direct selective metalization |
US9276336B2 (en) | 2009-05-28 | 2016-03-01 | Hsio Technologies, Llc | Metalized pad to electrical contact interface |
WO2010147934A1 (en) * | 2009-06-16 | 2010-12-23 | Hsio Technologies, Llc | Semiconductor die terminal |
US9930775B2 (en) | 2009-06-02 | 2018-03-27 | Hsio Technologies, Llc | Copper pillar full metal via electrical circuit structure |
US9184527B2 (en) | 2009-06-02 | 2015-11-10 | Hsio Technologies, Llc | Electrical connector insulator housing |
US9603249B2 (en) | 2009-06-02 | 2017-03-21 | Hsio Technologies, Llc | Direct metalization of electrical circuit structures |
US9231328B2 (en) | 2009-06-02 | 2016-01-05 | Hsio Technologies, Llc | Resilient conductive electrical interconnect |
US9699906B2 (en) | 2009-06-02 | 2017-07-04 | Hsio Technologies, Llc | Hybrid printed circuit assembly with low density main core and embedded high density circuit regions |
US9613841B2 (en) | 2009-06-02 | 2017-04-04 | Hsio Technologies, Llc | Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection |
US8928344B2 (en) | 2009-06-02 | 2015-01-06 | Hsio Technologies, Llc | Compliant printed circuit socket diagnostic tool |
WO2010141266A1 (en) | 2009-06-02 | 2010-12-09 | Hsio Technologies, Llc | Compliant printed circuit peripheral lead semiconductor package |
US9136196B2 (en) | 2009-06-02 | 2015-09-15 | Hsio Technologies, Llc | Compliant printed circuit wafer level semiconductor package |
WO2010141318A1 (en) | 2009-06-02 | 2010-12-09 | Hsio Technologies, Llc | Compliant printed circuit peripheral lead semiconductor test socket |
US9232654B2 (en) | 2009-06-02 | 2016-01-05 | Hsio Technologies, Llc | High performance electrical circuit structure |
US8618649B2 (en) | 2009-06-02 | 2013-12-31 | Hsio Technologies, Llc | Compliant printed circuit semiconductor package |
US8525346B2 (en) | 2009-06-02 | 2013-09-03 | Hsio Technologies, Llc | Compliant conductive nano-particle electrical interconnect |
WO2010141298A1 (en) | 2009-06-02 | 2010-12-09 | Hsio Technologies, Llc | Composite polymer-metal electrical contacts |
US9276339B2 (en) | 2009-06-02 | 2016-03-01 | Hsio Technologies, Llc | Electrical interconnect IC device socket |
WO2010141295A1 (en) | 2009-06-02 | 2010-12-09 | Hsio Technologies, Llc | Compliant printed flexible circuit |
WO2010141316A1 (en) | 2009-06-02 | 2010-12-09 | Hsio Technologies, Llc | Compliant printed circuit wafer probe diagnostic tool |
WO2012074963A1 (en) | 2010-12-01 | 2012-06-07 | Hsio Technologies, Llc | High performance surface mount electrical interconnect |
WO2010141311A1 (en) | 2009-06-02 | 2010-12-09 | Hsio Technologies, Llc | Compliant printed circuit area array semiconductor device package |
WO2012078493A1 (en) | 2010-12-06 | 2012-06-14 | Hsio Technologies, Llc | Electrical interconnect ic device socket |
US8987886B2 (en) | 2009-06-02 | 2015-03-24 | Hsio Technologies, Llc | Copper pillar full metal via electrical circuit structure |
US9318862B2 (en) | 2009-06-02 | 2016-04-19 | Hsio Technologies, Llc | Method of making an electronic interconnect |
US9184145B2 (en) | 2009-06-02 | 2015-11-10 | Hsio Technologies, Llc | Semiconductor device package adapter |
US8610265B2 (en) | 2009-06-02 | 2013-12-17 | Hsio Technologies, Llc | Compliant core peripheral lead semiconductor test socket |
US9196980B2 (en) | 2009-06-02 | 2015-11-24 | Hsio Technologies, Llc | High performance surface mount electrical interconnect with external biased normal force loading |
US8988093B2 (en) | 2009-06-02 | 2015-03-24 | Hsio Technologies, Llc | Bumped semiconductor wafer or die level electrical interconnect |
US8803539B2 (en) | 2009-06-03 | 2014-08-12 | Hsio Technologies, Llc | Compliant wafer level probe assembly |
US8981568B2 (en) | 2009-06-16 | 2015-03-17 | Hsio Technologies, Llc | Simulated wirebond semiconductor package |
US9320144B2 (en) | 2009-06-17 | 2016-04-19 | Hsio Technologies, Llc | Method of forming a semiconductor socket |
US8984748B2 (en) | 2009-06-29 | 2015-03-24 | Hsio Technologies, Llc | Singulated semiconductor device separable electrical interconnect |
US8981809B2 (en) | 2009-06-29 | 2015-03-17 | Hsio Technologies, Llc | Compliant printed circuit semiconductor tester interface |
US10159154B2 (en) | 2010-06-03 | 2018-12-18 | Hsio Technologies, Llc | Fusion bonded liquid crystal polymer circuit structure |
US9689897B2 (en) | 2010-06-03 | 2017-06-27 | Hsio Technologies, Llc | Performance enhanced semiconductor socket |
US8758067B2 (en) | 2010-06-03 | 2014-06-24 | Hsio Technologies, Llc | Selective metalization of electrical connector or socket housing |
US9350093B2 (en) | 2010-06-03 | 2016-05-24 | Hsio Technologies, Llc | Selective metalization of electrical connector or socket housing |
US9761520B2 (en) | 2012-07-10 | 2017-09-12 | Hsio Technologies, Llc | Method of making an electrical connector having electrodeposited terminals |
US10506722B2 (en) | 2013-07-11 | 2019-12-10 | Hsio Technologies, Llc | Fusion bonded liquid crystal polymer electrical circuit structure |
US10667410B2 (en) | 2013-07-11 | 2020-05-26 | Hsio Technologies, Llc | Method of making a fusion bonded circuit structure |
US9559447B2 (en) | 2015-03-18 | 2017-01-31 | Hsio Technologies, Llc | Mechanical contact retention within an electrical connector |
KR101944783B1 (ko) | 2017-01-16 | 2019-04-18 | 일진머티리얼즈 주식회사 | 캐리어박 부착 극박동박 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1995026047A1 (en) | 1994-03-18 | 1995-09-28 | Hitachi Chemical Company, Ltd. | Semiconductor package manufacturing method and semiconductor package |
JP3509274B2 (ja) * | 1994-07-13 | 2004-03-22 | セイコーエプソン株式会社 | 樹脂封止型半導体装置およびその製造方法 |
US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
JPH09312355A (ja) * | 1996-05-21 | 1997-12-02 | Shinko Electric Ind Co Ltd | 半導体装置とその製造方法 |
US6201292B1 (en) * | 1997-04-02 | 2001-03-13 | Dai Nippon Insatsu Kabushiki Kaisha | Resin-sealed semiconductor device, circuit member used therefor |
JPH10335566A (ja) * | 1997-04-02 | 1998-12-18 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置とそれに用いられる回路部材、および樹脂封止型半導体装置の製造方法 |
JP3521758B2 (ja) * | 1997-10-28 | 2004-04-19 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JPH11195742A (ja) * | 1998-01-05 | 1999-07-21 | Matsushita Electron Corp | 半導体装置及びその製造方法とそれに用いるリードフレーム |
-
2001
- 2001-02-15 CN CNB011045531A patent/CN1265451C/zh not_active Expired - Fee Related
- 2001-02-16 TW TW90103573A patent/TW501382B/zh not_active IP Right Cessation
- 2001-02-24 KR KR10-2001-0009507A patent/KR100407595B1/ko not_active IP Right Cessation
- 2001-03-16 US US09/809,849 patent/US6462418B2/en not_active Expired - Lifetime
- 2001-03-20 EP EP20010302549 patent/EP1187203A3/en not_active Withdrawn
-
2002
- 2002-09-06 US US10/236,502 patent/US6596564B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR20020020169A (ko) | 2002-03-14 |
US6462418B2 (en) | 2002-10-08 |
CN1341962A (zh) | 2002-03-27 |
CN1265451C (zh) | 2006-07-19 |
US20020027290A1 (en) | 2002-03-07 |
US20030011065A1 (en) | 2003-01-16 |
EP1187203A3 (en) | 2004-04-14 |
EP1187203A2 (en) | 2002-03-13 |
US6596564B2 (en) | 2003-07-22 |
KR100407595B1 (ko) | 2003-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW501382B (en) | Semiconductor device and process therefor | |
TW535462B (en) | Electric circuit device and method for making the same | |
US6482674B1 (en) | Semiconductor package having metal foil die mounting plate | |
TW510034B (en) | Ball grid array semiconductor package | |
TW497371B (en) | Semiconductor device and semiconductor module | |
JPH08125094A (ja) | 電子パッケージおよびその製造方法 | |
TW200532823A (en) | Circuit device | |
TW511401B (en) | Method for manufacturing circuit device | |
TW417220B (en) | Packaging structure and method of semiconductor chip | |
JP2010263080A (ja) | 半導体装置 | |
TW571402B (en) | Leadframe semiconductor device and the manufacturing method thereof, circuit substrate and electronic machine | |
JPH03108744A (ja) | 樹脂封止型半導体装置 | |
JP2009010213A (ja) | 混成集積回路装置 | |
TW200534454A (en) | Exposed pad module integrated a passive device therein | |
TW200539408A (en) | Method of manufacturing circuit device | |
JP3759572B2 (ja) | 半導体装置 | |
JP2006286679A (ja) | 半導体装置およびその製造方法 | |
JPH10256473A (ja) | 半導体装置 | |
JPH06132441A (ja) | 樹脂封止型半導体装置及びその製造方法 | |
JP3337911B2 (ja) | 半導体装置及びその製造方法 | |
TW432643B (en) | Low pin-count chip package structure and its manufacturing method | |
JP3676197B2 (ja) | 半導体装置および混成集積回路装置 | |
TW445600B (en) | Low-pin-count chip package and its manufacturing method | |
JP2962575B2 (ja) | 半導体装置 | |
JP4166065B2 (ja) | 回路装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |