TW432643B - Low pin-count chip package structure and its manufacturing method - Google Patents

Abstract

A low pin-count chip package structure and its manufacturing method is provided. It comprises a chip stand that loads a semiconductor chip and plural connection pads connected the chip. An encapsulation body covers the chip, chip seat and plural connection pads with the bottom surface of chip seat and connection pads being exposed. The feature of this invention is that the chip seat and connection pads have concave cross-section toward interior. This structure can lengthen the time of moisture diffusing into the package and enhance the fixing of the chip seat and connection pads in the encapsulation body. The manufacturing of this low pin-count chip package is also described.

Description

"鼷 4326 4 3 V. Description of the Invention (l) Field of the Invention: The present invention relates to a semiconductor wafer package structure, and more particularly to a low-pin-count chip package structure (l0w-pin-count chip package) and its manufacturing. Method: The first technique is a low-pin-count semiconductor chip package structure 100 according to a preferred embodiment of the “Resin-Packaged Component and Manufacturing Method” according to the Republic of China Publication No. 34830 6. The wafer 110 is enclosed in a colloid 120. The front surface of the chip 110 has a plurality of wafer pads 110a electrically connected to the plurality of connection pads 130. The back surface of the chip 110 is exposed to the encapsulant 120 with a conductive adhesive layer 112. The plurality of connection pads 130 are arranged around the chip 110 and are exposed on the lower surface of the encapsulant 120 for electrical connection to the outside. Since the sealing compound 120 does not cover the exposed lower surfaces of the plurality of connection pads 130, it cannot securely fix the plurality of connection pads 130 ° the plurality of connection pads 1 3 0-generally made of a metal with good conductivity (Such as copper), but the encapsulant 1 2 0 is made of an insulating material (such as epoxy compound plastic). Therefore, the bonding force between the plurality of connection pads 130 and the sealant 120 is relatively weak, and the thermal expansion coefficients between them are greatly different. When the conventional package structure is subjected to temperature changes, the interface between the connection pad and the sealing compound will cause stress due to CTE mismatch, and the stress will cause delamination of the metal / plastic interface. Phenomenon. When the metal / plastic interface is spalled, the surrounding water will permeate and accumulate to the spalled area through the sealant.

Page 4 PM 326 4 3 V. Description of the invention (2) 蜮 > And -I finds and accumulates in the sealant, then when the temperature increases rapidly, the accumulated moisture will evaporate and expand instantly, so in this layer The cracked area generates a hygrothermal stress that causes the nearby sealing colloid to pop (the popcorn of the sealing colloid is common when the conventional device is soldered to the substrate by IR reflow) Time. In addition, since the sealing compound 120 seals only one side of the wafer 110, moisture and / or ionic contamination from the air can penetrate from the joint between the sealing compound and the wafer and affect the reliability of the wafer (in other words, reHabiHty), in other words , Greatly reducing the operating life of the chip. As the semiconductor industry tends to package electronic devices in smaller and smaller packaging structures, this phenomenon is becoming increasingly critical. SUMMARY OF THE INVENTION The present invention therefore provides a low-pin-count semiconductor chip package structure that overcomes or at least improves the aforementioned problems of the prior art. Therefore, the "first aspect" of the present invention provides a low-pin-count chip package structure, which includes a chip holder for carrying a semiconductor chip, and a plurality of connection pads electrically connected to the chip pad. The semiconductor crystal moon. A piece of colloid covers the semiconductor wafer, the wafer holder, and the plurality of connection pads so that the lower surfaces of the wafer holder and the connection pad are exposed to the sealing gel. The invention is characterized in that the wafer holder and the plurality of connection pads have inwardly recessed cross-sections, thereby prolonging the path and time for water vapor to penetrate into the packaging structure, and strengthening and fixing the wafer holder and the plurality of connection pads to the sealing body. Inside. According to a second aspect, the present invention further provides a method for manufacturing the low pin number half.

• 432643 V. Description of the invention (3) Guiding crystal); the method of packaging structure. The method includes the following steps: (a) providing a carrier sheet; (b) laminating a metal layer on the carrier sheet; (c) half-etching = (half-etching) the metal layer to form a plurality of predetermined positions Recesses; (d) forming a photoresist layer on the metal layer; (e) half-removing the photoresist layer leaving only the photoresist in the plurality of recesses; (f) forming a metal cover Layer on the surface covered by the metal layer that is not light I1; (g) removing the photoresist in the plurality of recesses; (h) etching the metal layer to form a wafer holder with an inwardly concave section and a plurality of recesses Connection pads; (i) fixing a semiconductor wafer on the carrier sheet; (j) electrically connecting the semiconductor wafer to the plurality of connection pads; (k) forming a gel covering the semiconductor wafer and the connection pads, wherein The inwardly recessed cross-section helps to secure the plurality of connection pads in the sealant; (1) remove the carrier sheet; and (m) form a thin metal plating layer under the wafer holder and the plurality of connection pads surface. Illustrative illustrations: In order to make the above and other objects, features, and advantages of the present invention more obvious, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1: A cross-sectional view of a low-pin-count semiconductor chip package structure according to a preferred embodiment of the “Resin-Packed Ship and Its Manufacturing Method” patent No. 34830 6; FIG. 2: According to the present invention Cross-section 低 of a low-pin-count semiconductor chip package structure according to one of the first preferred embodiments; FIGS. 3 to 10: FIG.

p f4 326 4 3

V. Description of the invention (4) A semiconductor chip package structure with a lower pin count than the poorer embodiment. Figure 11: A cross-sectional view of a semiconductor chip package structure according to a second preferred embodiment of the present invention; A method for manufacturing a semiconductor chip package structure according to the present invention a. Figure 12 to Figure 15. Figure 2 low pin number drawing preferred embodiment description: 100 low pin number semi-conductor wafer package structure 110 chip 110a Wafer pads 112 120 Sealant 130 Connection pad 200 Low pin number semiconductor wafer package structure 210 Wafer 210a Wafer wafer 212 220 Sealant 230 Connection pad 232 240 Nickel layer 250 Gold (or palladium) layer 252 Nickel layer 254 Gold (or Palladium) layer 260 carrier sheet 270 metal layer 272 280 photoresist layer conductive adhesive layer connecting wire wafer holder

3 0 0 Low pin count semiconductor chip package structure invention description: The second figure shows a semiconductor chip package structure 200 according to one of the first preferred embodiments of the present invention, which includes a chip 210 through a conductive adhesive layer or A non-conductive adhesive layer such as an epoxy adhesive (not shown in the figure) is fixed on a wafer holder 2 32. The front surface of the chip 210 has a plurality of wafer pads 2′10a, which are electrically connected to a plurality of connection pads 230 via a plurality of bonding wires 212. The plurality of connection pads 23 are provided on the wafer holder 232.

Page 7 "Xin 4 3 2 6 4 3 V. Description of the invention (5) Edge is encountered. The chip holder 232 and a plurality of connection pads 23 0 are exposed on the bottom of the sealing skull 220 and all have inward recesses. The cross section of the chip is used to extend the path and time for water and gas to penetrate the package structure 2000, and to strengthen and fix the chip holder 232 and the plurality of connection pads 230 in a predetermined position in the sealing compound 220. One gel covers The semiconductor wafer 210 and the plurality of connection pads 230 are disposed on the wafer holder 232 and the plurality of connection pads 230. A metal covering layer is preferably provided to form a good bond with the connection line 212. The metal covering layer Generally, it includes a layer of nickel 240 covering the wafer holder 232 and a plurality of connection pads 230 on the upper surface and a portion of the side close to the upper surface, and a layer of gold (or palladium) 250 covering the nickel layer 240. The wafer holder 232 And the lower surface of the plurality of connection pads 230 has a thin metal plate (flash) »The thin metal plated layer preferably includes a layer of nickel 252 covering the chip holder 232 and the lower surface of the plurality of connection pads 230 and a layer of gold (Or palladium) 254 covers the nickel layer. The thin metal plating layer can protect the wafer holder 232 and the plurality of connection 塾 230 from corrosion or pollution. The package structure 2 0 0 series can be similar to other non- The leadless device is mounted on a substrate, such as a printed circuit board. The printed circuit board can be screen printed with solder paste to correspond to the connection pad 230 at the bottom of the package structure 200. A pattern. Then the package structure 200 is placed on the printed circuit board and re-soldered using a conventional surface bonding technique. It can be understood that 'the connection pad 230 exposed at the bottom of the package structure 200 is also May be printed on tin

——F 4 32B ^ 3 __— 5. Description of the invention (6) f (solder paste), and then install it on the substrate. 3 to 10 illustrate a method for manufacturing the low-contact-count semiconductor chip package structure 200 according to the first preferred embodiment of the present invention. The third figure discloses a carrier sheet 260 and a metal layer 270 (e.g., a copper foil) laminated thereon. Specifically, the carrier sheet 260 is preferably a polyimide or polyester tape having a silicone resin layer. The metal layer 270 is laminated on the carrier sheet 260 by a conventional method (for example, a hot pressing method). The carrier wafer 260 is used to support the semiconductor wafer 210 during the entire manufacturing process to manufacture the low-pin-count semiconductor wafer package structure 200. Referring to the fourth figure, the metal layer 270 is formed by a plurality of recesses at a predetermined position in a half-etching manner. The plurality of protrusions 272 not eroded during the half-etching process will eventually form the wafer holder 232 and the plurality of connection pads 230. In this embodiment, the thickness of the metal layer 270 is about 5-20 mils, and the etching depth of each recess is about 2-8 mils—depending on the thickness of the metal layer 270, set. It is worth noting that the half-etching process referred to here does not only mean that half of the thickness of the metal layer 270 is accurately removed by etching, but also includes that a portion of the thickness of the metal layer 270 is removed by partial etching. Referring to the fifth figure, a photoresist layer 280 is formed on the metal layer 270 by a conventional technique (such as printing). The photoresist layer 280 is mainly composed of a resin mixture and a photoactive material. ), The photoactive material makes the photoresist layer 280 photodefinable (photode fi nab 1e).

Page 9 f K4326 4 ______ 5. Description of the invention (7) Please refer to the sixth figure, 'The photoresist layer 280 is "half-removing" in a conventional manner and is left only in the plurality of recesses. The first obstruction in. It is worth noting that the photoresist layer 280 is preferably "half-removed" so that the plurality of convex portions 272 slightly protrude from the remaining photoresist, whereby all the convex portions 272 are substantially exposed on The remaining photoresist, and the surface of each recess is almost completely covered by the remaining photoresist. It can be understood that 'the photoresist layer 280 can also be "half-removed" to make the complex number Each convex portion 272 is flush with the photoresist layer 280. Please refer to the seventh figure. The metal cover layer including a layer of nickel 240 and a layer of gold (or palladium) 250 is formed on the exposed convex portion 272 using a conventional plating technique. »The nickel layer 240 is first plated on the convex portion 272, and then the gold (or palladium) layer 250 is plated on the nickel layer 240. If the photoresist layer 280 of the sixth figure is "half-removed" and is flush with the plurality of convex portions 272 ', the metal cover layer is formed only on the upper surface of the plurality of convex portions 272. Preferably, the photoresist layer 280 is “half-removed” so that the plurality of convex portions 272 protrude from the photoresist layer 280 ′, so that the metal covering layer is not only formed on the plurality of convex portions. The 272 upper surface is preferably formed at the same time as the side surface close to the upper surface. Referring to FIG. 8, the photoresist layer 280 is removed by a conventional method. Please refer to the ninth figure, 'The chip holder 232 and the plurality of connection pads 230 are formed by indenting a plurality of recesses (refer to the eighth figure) on the metal layer 27, which are not protected by a metal cover layer. By appropriate control of the concentration of the etching solution and the buttoning time, the wafer holder 2 3 2 and a plurality of

Page 10 Γ · 4 326 4 3 V. Description of the invention (8) All joints 230 can be obtained-a concave section inward. In addition, a metal cover layer formed on a part of the side surface of the wafer holder 232 and the plurality of connection pads 230 helps to improve the undercut that often occurs in isotropic etching. Since the metal cover layer is also coated on the plurality of connection pads 230 for electrically connecting to the semiconductor chip 210, it must be selected with a good bonding force with a conventional bonding wire. Referring to the tenth figure, the back surface of the semiconductor wafer 210 is fixed to the wafer holder 232 with an adhesive layer such as a conductive or non-conductive epoxy adhesive (not shown). The plurality of bonding wires 212 are connected to the plurality of wafer pads 210a on the chip 210 and the plurality of connection pads 230 using a conventional bonding technique. Then, the sealing compound 22 is formed on the carrier sheet 260, the semiconductor wafer 21, and the plurality of connection pads 230 by a conventional plastic molding method (for example, transfer molding). During the curing process, the plastic (B) olding compoimd will shrink and apply mechanical stress to the wafer holder 2 3 2 and the connection pad 23. Therefore, the hardened plastic of the wafer holder 232 and the connection pad 23 is fixed in position. Finally, a separation step is performed to remove the carrier sheet 26 (), and a thin metal plating layer is plated on the lower surface of the wafer holder 232 and the plurality of connection pads 23 (), so as to make the second circle Low pin count makes 200. The specific m-separated step cost refers to direct support ^^ 26 = division. And after peeling off, the wafer holder 232 and still be embedded in the sealing compound 22 as expected. W reverse connection. Preferably, the metal thin film I_ 0n _ _ contains a layer of nickel 2 5 2 to cover the wafer.

% Article 11 14326 4 3 V. Description of the invention (9) The lower surface of the socket 232 and the plurality of connection pads 23, and a layer of gold (or period) 254 covers the recording layer 252. The thin metal recording layer can protect the exposed portions of the wafer socket 232 and the plurality of connection pads 23 from corrosion. This ensures heat dissipation efficiency and solder ball connection of the wafer socket 232 and the plurality of connection pads 230. Reliability (solder_jint reliability). FIG. 11 illustrates a low-pin-count semiconductor chip package structure 300 according to a second preferred embodiment of the present invention, which includes a chip 21 sealed in a gel body 220. Except that the wafer holder 232 is omitted and the adhesive layer (not shown in the figure) is directly exposed on the sealing compound 220, the package structure 300 is substantially the same as the package structure 2000 of the second figure. The twelfth to fifteenth circles disclose a method of manufacturing a low-pin-count semiconductor chip package structure 300 according to the second preferred embodiment of the present invention. Please refer to the twelfth figure 'a metal layer 270 (such as a copper foil) is laminated on a carrier sheet 260' by a conventional method (such as hot pressing), and the metal layer 270 is semi-etched ( half-etching) to form a plurality of recesses at a predetermined position. In the half-etching process, the plurality of convex portions 2 72 that are not eroded will finally form the plurality of connection pads 2 30 ° Please refer to the thirteenth figure, a photoresist layer 28 0 is formed on the metal layer 2 70 and The photoresist, which is "half-removing" in a conventional manner, is left only in the plurality of recesses. It is worth noting that all the convex portions 272 are barely exposed to the remaining photoresist, and the surface of each concave portion is almost completely covered by the remaining photoresist.

Page 12 Ink 43264 3 V. Description of the Invention (ίο) Please refer to FIG. 14 and FIG. 7 to form the metal covering layer containing a layer of nickel 2 4 0 and a layer of gold (or saturated) 250 on the exposed convex portion 272 (see (Figure 13), and the photoresist layer 280 is removed. Referring to the fifteenth figure, the plurality of connection pads 230 are formed by etching a plurality of recesses (refer to the fourteenth circle) on the metal layer 270 which are not protected by the metal covering layer. Therefore, when the etching process is completed, the plurality of connection 塾 230 has a cross-section recessed inward. Then, the semiconductor wafer 21 is fixed to the carrier sheet 26 with an adhesive layer (not shown in the figure), and is electrically connected to the plurality of wires via a plurality of bonding wires 2] 2. Connection pads 230 »Finally, the sealant 220 is formed on the semiconductor wafer 210 and the plurality of connection pads 230 by a conventional plastic molding method; a separation step is performed to remove the carrier sheet 260; and electroplating A thin metal clock layer is formed on the lower surface of the plurality of connection pads 230 to obtain a low-pin-count semiconductor chip package structure 300 as shown in FIG. 11. In the present invention, the wafer holder and the plurality of connection pads have an inward = inward cross section, thereby increasing the water vapor infiltration path, thereby extending the time for the water vapor infiltration and the functional area in the “structure”. In addition, the direction The recessed profile can help to hold the wafer holder and the plurality of connection pads in position, thereby strengthening and fixing the wafer holder and the plurality of connection pads in the sealing body. Although the present invention has been described in the foregoing preferred embodiment, It is revealed, but it is not used to = invention, any person skilled in this art can make various changes without departing from it. Therefore, the value of the invention = will be determined by the scope of the attached patent application. page

Claims (1)

'^ 4 32 6 4 3 VI. Patent application scope 1 kind of low pin number semiconductor wafer package structure, which includes:-semiconductor wafer; a plurality of connection pads are arranged around the semiconductor chip, wherein the plurality of The connection pad has an inwardly recessed cross-section; a metal cover layer is formed substantially on the upper surface of the plurality of connection pads; the semiconductor wafer has a plurality of wafer pads electrically connected to the plurality of connection pads; The semiconductor wafer and the connection pad are exposed so that the lower surface of the connection pad is exposed to the sealing compound; and a thin metal plating (flash) is provided on the plurality of connection pads exposed to the lower surface of the sealing compound, wherein the inward recess The cut-in section helps to fix the plurality of connection pads in the sealing body. 2. The low-pin-count semiconductor chip package structure according to item 1 of the patent application scope, wherein the thin metal plating layer includes a layer of nickel covering the lower surface of the plurality of connection pads and a layer of gold or palladium covering the nickel layer. 3. The low-pin-count semiconductor chip package structure according to item 1 of the scope of the patent application, wherein the metal cover layer is formed approximately on the surface of the plurality of connection ridges and a portion of the side close to the upper surface. 4. The low-pin-count semiconductor chip package structure according to item 3 of the patent application scope, wherein the metal cover layer includes a layer of nickel to cover the plurality of connections Page 14 r 39 R 4 3_ 6. Scope of patent application The upper surface of the pad and the part close to the upper surface of the side, and a layer of gold or palladium covers the nickel layer. 5. A method for manufacturing a low-pin-count semiconductor chip package structure, comprising the following steps: providing a carrier sheet; laminating a metal layer on the carrier sheet; half-etching the metal layer in a preset A plurality of recesses are formed at positions; a photoresist layer is formed on the metal layer; half_removing the photoresist layer leaves only the photoresist in the plurality of recesses; forming a metal cover layer where the metal layer is not A photoresist-covered surface; removing the photoresist in the plurality of recesses; etching the metal layer to form a plurality of connection pads having an inwardly recessed cross-section; fixing a semiconductor crystal on the carrier sheet; electrically connecting the semiconductor Forming a chip to cover the plurality of connection pads; forming a gel covering the semiconductor wafer and the connection pads, wherein the inwardly recessed cross-section helps to fix the plurality of connection pads in the sealant; removing the carrier sheet; And forming a thin metal plating layer on the plurality of connection pads to be exposed on the lower surface of the sealing compound. Page 15 Step 4 3 2 6 4 3 VI. Patent Application Range 6: A method for manufacturing a low-pin-count semiconductor chip package structure in accordance with item 5 of the patent application range, wherein the metal thin ship layer includes a layer covering the The lower surface of the plurality of connection pads and a layer of gold or palladium cover the nickel layer. 7. The method for manufacturing a low-pin-count semiconductor wafer packaging structure according to item 5 of the scope of the patent application, wherein the carrier sheet is a polyimide tape having a silicone resin adhesive layer. 8. The method for manufacturing a low-pin-count semiconductor wafer packaging structure according to item 5 of the scope of the patent application, wherein the carrier sheet is a polyester ester tape having a silicone resin layer. 9. A method for manufacturing a low-pin-count semiconductor chip package structure according to item 5 of the scope of the patent application, wherein the metal cover layer includes a layer of nickel over the surface of the metal layer that is not covered with photoresist and a layer of gold or palladium over The nickel layer. 10. A low-pin-count semiconductor wafer package structure, comprising: a wafer socket and a plurality of connection pads disposed on the periphery of the wafer socket, wherein the wafer socket and the plurality of connection pads have inward recesses. A cross section; a metal cover layer is formed substantially on the wafer holder and the upper surface of the plurality of connection pads; J P.16 Step 4 32 6 4 3 Sixth, the scope of patent application is a Fengfeng conductor crystal; it is arranged on the crystal socket and is electrically connected to the plurality of connection pads; a colloid covers the semiconductor wafer and the connection pad so that the wafer seat and the connection pad The lower surface is exposed to the sealing compound; and a thin metal plating layer is provided on the chip holder and the connection pad is exposed to the lower surface of the sealing compound, wherein the inwardly concave section helps the chip holder and a plurality of The connection pad is fixed in the sealing body. Sealed nickel sheet, the crystal body, the cover is guided by a half-covered palladium cover, or a foot nickel-gold connection layer, the second lower layer is included, and the surface is coated with a thin layer of a standard pad. Lijin then specifically asked the applicants to apply for it, restore, build, and --- * construct. 1 Mounting layer Sealing film and crystal base. The guide is divided into half pieces, and the surface is connected to the bottom of the table. The surface is close to the large surface 1 ^ 1 layer side cover and the cover is covered by a normal face gold watch. The padding, connecting, and making up of 2 pieces of 1 piece of several pieces of the supporting piece of the crystal body of the body is guided on the surface of the cover half of the foot close to the lower side of the nickel abutment layer. The content and layer items are covered with nickel 2 series. The 1-layer surface is covered by the top cover. It is a pad of palladium or gold. Please contact the middle layer to apply for it. It consists of 3 structures, 1 seat and 4 IX. Page 17 glue 43264 3 6. The scope of the patent application covers the following steps: providing a carrier sheet; laminating a metal layer on the carrier sheet; semi-etching (ha 1 f-et ch i ng) the metal layer to be preset Forming a plurality of recesses at a position; forming a photoresist layer on the metal layer; half-removing the photoresist layer leaving only the photoresist in the plurality of recesses; forming a metal cover layer on the metal layer The surface not covered by the photoresist; removing the photoresist in the plurality of recesses; #etching the metal layer to form a wafer holder with an inwardly concave cross section and a plurality of connection pads; fixing a semiconductor wafer on the carrier sheet ; Electrically connecting the semiconductor wafer to the plurality of connection pads; forming a gel covering the semiconductor wafer and the connection pads, wherein the inwardly recessed cross-section helps to fix the plurality of connection pads in the sealing body; Removing the carrier sheet; and forming a thin metal plating layer on the wafer holder and the lower surface of the plurality of connection pads. Page 18 P4 326 4 3_ VI. The scope of patent application is on the crystal; the lower surface of the i seat and the plurality of connection pads and a layer of gold or palladium cover the nickel layer. 16. The method for manufacturing a low-pin-count semiconductor wafer packaging structure according to item 14 of the scope of patent application, wherein the carrier sheet is a polyimide tape with a silicon resin layer. Crystal lipid-conducting half-tree silicon feet have adapters. The lower area is the winning system r) The film te contains es 4 Cheng ly 1 The PO in the middle of the i (around its scope '), the application of the law requested by the special party, 7 pieces of 1 piece of plastic glue. 5 6 η ο The cover of the Japanese egg cover is covered with half a layer of nickel, and the covering item with a low-layer formation cover is 4 gold, which is the most important. Pack of 8 seals and 1 sheet of palladium or gold layer on the cover-and cover the surface with light blocking as unlayered gold. The layer of nickel page 19