JP3117688B2 - Semiconductor package for surface mounting - Google Patents

Semiconductor package for surface mounting

Info

Publication number
JP3117688B2
JP3117688B2 JP11334626A JP33462699A JP3117688B2 JP 3117688 B2 JP3117688 B2 JP 3117688B2 JP 11334626 A JP11334626 A JP 11334626A JP 33462699 A JP33462699 A JP 33462699A JP 3117688 B2 JP3117688 B2 JP 3117688B2
Authority
JP
Japan
Prior art keywords
surface mounting
insulating layer
semiconductor package
semiconductor chip
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP11334626A
Other languages
Japanese (ja)
Other versions
JP2000150717A (en
Inventor
公一 古賀
正巳 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP11334626A priority Critical patent/JP3117688B2/en
Publication of JP2000150717A publication Critical patent/JP2000150717A/en
Application granted granted Critical
Publication of JP3117688B2 publication Critical patent/JP3117688B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、表面実装用の半導
体パッケージに関し、電気機器に利用される半導体チッ
プを搭載する基板に、外部入出力の端子を形成した表面
実装用の半導体パッケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package for surface mounting, and more particularly to a semiconductor package for surface mounting in which external input / output terminals are formed on a substrate on which a semiconductor chip used in electric equipment is mounted.

【0002】[0002]

【従来の技術】従来、図7に示すような特開昭63−1
36655号公報に記載された表面実装用の半導体パッ
ケージが提案されている。
2. Description of the Related Art Conventionally, as shown in FIG.
No. 36655 proposes a semiconductor package for surface mounting.

【0003】図8に示す表面実装用の半導体パッケージ
は、半導体チップ1が上面に固定される良熱伝導性の金
属基材9と、この金属基材9の下面に絶縁性薄層16を
介して固着され、半導体チップ1の放熱を行うヒートシ
ンク14と、上面に半導体チップ1の端子部と電気接続
するための回路部5を有し、下面に金属基材9を、半導
体チップ1を固着した側を上方に向けて固着し、この半
導体チップ1の近傍において、この半導体チップ1の上
方を開放するような貫通孔18が設けられた配線基板1
7とから形成されている。
The semiconductor package for surface mounting shown in FIG. 8 has a metal substrate 9 of good thermal conductivity on which the semiconductor chip 1 is fixed on the upper surface, and an insulating thin layer 16 on the lower surface of the metal substrate 9. A heat sink 14 for dissipating heat of the semiconductor chip 1, a circuit portion 5 for electrical connection with a terminal portion of the semiconductor chip 1 on the upper surface, a metal substrate 9 on the lower surface, and the semiconductor chip 1 fixed thereto. The wiring board 1 having a through-hole 18 provided so as to open the upper side of the semiconductor chip 1 in the vicinity of the semiconductor chip 1.
7 are formed.

【0004】このような表面実装用の半導体パッケージ
において、半導体チップ1を金属基材9に固着し、この
半導体チップ1と回路部5とをボンディングワイヤ11
を介して電気接続する。そして、半導体チップ1及びボ
ンディングワイヤ11を保護するための封止樹脂などに
よる気密封止(図示せず)を施して、最終的に半導体装
置が形成できる。また、この半導体装置を外部回路板に
接続するための端子6が配線基板17の回路部5側に形
成され、回路部5と接続されている。
In such a semiconductor package for surface mounting, the semiconductor chip 1 is fixed to a metal substrate 9, and the semiconductor chip 1 and the circuit section 5 are bonded with bonding wires 11.
Electrical connection through. Then, the semiconductor chip 1 and the bonding wires 11 are hermetically sealed with a sealing resin or the like (not shown) for protecting the semiconductor wires, thereby finally forming a semiconductor device. Terminals 6 for connecting the semiconductor device to an external circuit board are formed on the circuit board 5 side of the wiring board 17 and are connected to the circuit board 5.

【0005】このような表面実装用の半導体パッケージ
によれば、半導体チップ1を直接支持した金属基材9に
よって一定の放熱が確保され、さらに、これに絶縁性薄
層16を介してヒートシンクを固着しているので、絶縁
性が確保されるとともに、充分高い放熱効果が得られ
る。
According to such a semiconductor package for surface mounting, a constant heat radiation is ensured by the metal substrate 9 directly supporting the semiconductor chip 1, and a heat sink is fixed to this through the insulating thin layer 16. As a result, insulation is ensured and a sufficiently high heat radiation effect is obtained.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、上記従
来の表面実装用の半導体パッケージを用いた半導体装置
を外部回路板に表面実装して用いる場合、封止樹脂の上
面よりも端子6の位置が高くないと、外部回路板に封止
樹脂が当接して端子6が外部回路板に接続できないた
め、封止樹脂の上面よりも端子6の位置を高くしなけれ
ばならない。したがって、回路部5におけるボンディン
グワイヤ11と接続されるボンディング接続部は封止樹
脂に覆われるため、このボンディング接続部と端子6の
接続部との高さを変える必要がある。この高さを変える
方法として、配線基板17の上面に段差を設け、段差の
低い側にボンディング接続部を設け、段差の高い側に端
子6を設けている。しかし、この方法では、高さの違う
ボンディング接続部と端子6とを接続する接続手段が必
要になる。
However, when a semiconductor device using the above-mentioned conventional surface mounting semiconductor package is mounted on an external circuit board and used, the position of the terminal 6 is higher than the upper surface of the sealing resin. Otherwise, the terminal 6 cannot be connected to the external circuit board due to the contact of the sealing resin with the external circuit board. Therefore, the position of the terminal 6 must be higher than the upper surface of the sealing resin. Therefore, since the bonding connection portion of the circuit portion 5 connected to the bonding wire 11 is covered with the sealing resin, it is necessary to change the height between the bonding connection portion and the connection portion of the terminal 6. As a method of changing the height, a step is provided on the upper surface of the wiring board 17, a bonding connection portion is provided on a side having a lower step, and the terminal 6 is provided on a side having a higher step. However, this method requires connection means for connecting the bonding connection portions having different heights to the terminals 6.

【0007】本発明は、上記事由に鑑みてなしたもの
で、その目的とするところは、半導体チップ及び回路部
を充分封止した状態で外部回路板に表面実装できる半導
体装置が形成できるとともに、接続信頼性の向上した端
子が容易に形成できる表面実装用の半導体パッケージを
提供することにある。
The present invention has been made in view of the above circumstances, and an object of the present invention is to form a semiconductor device which can be surface-mounted on an external circuit board with a semiconductor chip and a circuit portion sufficiently sealed. An object of the present invention is to provide a surface mounting semiconductor package in which terminals with improved connection reliability can be easily formed.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に、請求項1記載の発明は、半導体チップ1を搭載する
凹部2と、この凹部2周囲の肩部3に設けた回路部5と
を備える回路基板21を形成し、この回路基板21の回
路部5上に透孔7を有する絶縁層8を積層し、この透孔
7を貫通して下端部が回路部5に接続導通するととも
に、上端部が絶縁層8上面に突出するスルーホール導電
路4を形成し、このスルーホール導電路4は上端部およ
び下端部が一体に形成され、このスルーホール導電路4
の上端部を回路基板21上の凹部2および肩部3と同じ
側に設けた表面実装用の端子6に形成してなることを特
徴として構成している。
In order to achieve the above object, according to the present invention, there is provided a semiconductor device comprising: a concave portion for mounting a semiconductor chip; a circuit portion provided on a shoulder portion surrounding the concave portion; Is formed, an insulating layer 8 having a through hole 7 is laminated on the circuit portion 5 of the circuit board 21, and a lower end portion is connected to the circuit portion 5 through the through hole 7 so as to be electrically connected. to form a through-hole conductive path 4 the upper end projects into the insulating layer 8 top, the through-hole conductive path 4 Oyo upper portion
And the lower end thereof are integrally formed.
Is formed on the surface mounting terminal 6 provided on the same side as the concave portion 2 and the shoulder 3 on the circuit board 21.

【0009】このような表面実装用の半導体パッケージ
では、半導体チップ1に接続される回路部5を有する回
路基板21にスルーホール導電路4を有する絶縁層8を
積層しているため、スルーホール導電路4の上端部を端
子6として使用でき、スルーホール導電路4下端に接続
される回路部5と半導体チップ1とを封止するのに充分
な封止樹脂の厚みを確保できるとともに、端子6を外部
回路板へ密着固定して表面実装できる半導体装置が形成
できる。
In such a semiconductor package for surface mounting, since the insulating layer 8 having the through-hole conductive path 4 is laminated on the circuit board 21 having the circuit portion 5 connected to the semiconductor chip 1, the through-hole conductive The upper end of the path 4 can be used as the terminal 6, and a sufficient thickness of the sealing resin for sealing the circuit part 5 connected to the lower end of the through-hole conductive path 4 and the semiconductor chip 1 can be ensured. A semiconductor device that can be surface-mounted by tightly fixing the device to an external circuit board can be formed.

【0010】[0010]

【発明の実施の形態】以下、本発明の実施形態の表面実
装用の半導体パッケージを図1乃至図6に基づいて説明
する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor package for surface mounting according to an embodiment of the present invention will be described below with reference to FIGS.

【0011】図1は、本発明の実施形態の表面実装用の
半導体パッケージを示す斜視図である。また、図2は、
同上の表面実装用の半導体パッケージを用いた半導体装
置を示す縦断面図である。
FIG. 1 is a perspective view showing a semiconductor package for surface mounting according to an embodiment of the present invention. Also, FIG.
FIG. 3 is a longitudinal sectional view showing a semiconductor device using the same semiconductor package for surface mounting.

【0012】図1、図2に示すように、表面実装用の半
導体パッケージは、半導体チップ1を搭載する凹部2
と、この凹部2周囲の肩部3に設けた回路部5とを備え
る回路基板21を形成し、この回路基板21の回路部5
上に透孔7を有する絶縁層8を積層し、この透孔7を貫
通して下端部が回路部5に接続導通するとともに、上端
部が絶縁層8上面に突出するスルーホール導電路4を形
成し、このスルーホール導電路4の上端部を回路基板2
1上の凹部2および肩部3と同じ側に設けた表面実装用
の端子6に形成している。
As shown in FIGS. 1 and 2, a semiconductor package for surface mounting includes a recess 2 on which a semiconductor chip 1 is mounted.
And a circuit portion 21 provided on the shoulder portion 3 around the concave portion 2 to form a circuit portion 21 of the circuit portion 21.
An insulating layer 8 having a through hole 7 is laminated thereon. A through hole conductive path 4 penetrating through the through hole 7 and having a lower end connected to the circuit portion 5 and having an upper end protruding above the upper surface of the insulating layer 8 is formed. And the upper end of the through-hole conductive path 4 is connected to the circuit board 2.
1 are formed on the surface mounting terminals 6 provided on the same side as the concave portion 2 and the shoulder portion 3.

【0013】金属基材9は、良熱伝導性金属、例えば
銅、アルミニウム等から形成され、上面略中央に半導体
チップ1を組み込むための凹部2を設けている。この金
属基材9上面の凹部2周囲を肩部3とし、この肩部3に
基板絶縁層10を形成している。基板絶縁層10の材料
はエポキシ樹脂接着剤で、スクリーン印刷法により形成
する。この基板絶縁層10上に回路部5を形成する。こ
の回路部5の形成方法はステンレス板上に必要なパター
ン状の電気めっきを行い、その電気めっきでできた回路
部5を基板絶縁層10上に熱転写する方法である。
The metal substrate 9 is made of a good heat conductive metal, such as copper or aluminum, and has a concave portion 2 for mounting the semiconductor chip 1 at substantially the center of the upper surface. The periphery of the recess 2 on the upper surface of the metal base 9 is defined as a shoulder 3, and a substrate insulating layer 10 is formed on the shoulder 3. The material of the substrate insulating layer 10 is an epoxy resin adhesive, and is formed by a screen printing method. The circuit section 5 is formed on the substrate insulating layer 10. The method of forming the circuit portion 5 is a method of performing electroplating in a required pattern on a stainless steel plate and thermally transferring the circuit portion 5 formed by the electroplating onto the substrate insulating layer 10.

【0014】そして、図2に示すように、回路部5の上
に端子6を形成して表面実装用の半導体パッケージを形
成する。
Then, as shown in FIG. 2, terminals 6 are formed on the circuit section 5 to form a semiconductor package for surface mounting.

【0015】まず、回路部5の上に絶縁層8を形成す
る。この絶縁層8の材料は金属基材9上の基板絶縁層1
0と同じくエポキシ樹脂接着剤であり、スクリーン印刷
法により形成する。この絶縁層8は後で組み込む半導体
チップ1の樹脂封止が簡単にできるように、厚肉に形成
することが必要である。このために、材料的には無機フ
ィラー分を多くした配合にするとか、下地に無機フィラ
ー分の多い層を形成し、その上に無機フィラー分の少な
い材料を重ねて形成するといった対策が必要である。次
に、この絶縁層8の上に無電解めっきを全面に施し、そ
の上にめっきレジストでパターンを形成し、上から電気
めっきを行う。その後、レジストを除去し、全面を薄く
エッチングすることにより露出した無電解めっきを取除
きスルーホール導電路4を形成する。このスルーホール
導電路4を端子6としている。
First, an insulating layer 8 is formed on the circuit section 5. The material of the insulating layer 8 is the substrate insulating layer 1 on the metal base 9.
It is an epoxy resin adhesive like 0, and is formed by a screen printing method. The insulating layer 8 needs to be formed thick so that the semiconductor chip 1 to be incorporated later can be easily sealed with resin. For this reason, it is necessary to take measures such as mixing the material with a large amount of the inorganic filler or forming a layer with a large amount of the inorganic filler on the underlayer and overlaying a material with a small amount of the inorganic filler thereon. is there. Next, electroless plating is applied to the entire surface of the insulating layer 8, a pattern is formed thereon with a plating resist, and electroplating is performed from above. Thereafter, the resist is removed, the entire surface is thinly etched, and the exposed electroless plating is removed to form a through-hole conductive path 4. This through-hole conductive path 4 is a terminal 6.

【0016】さらに、図2に示すように、同上の表面実
装用の半導体パッケージを用いて、半導体装置を形成す
る方法を説明する。金属基材9上の凹部2に半導体チッ
プ1を密着載置する。次いで、ワイヤボンディングによ
り半導体チップ1と回路部5とを接続する。ボンディン
グワイヤ11には金線、アルミ線、銅線等を使用する。
この後、シリコン樹脂により、半導体チップ1、ボンデ
ィングワイヤ11を封止、保護する。更に上からエポキ
シ樹脂により封止する。これら封止樹脂12は場合によ
ってはどちらか一方だけですますこともある。
Further, as shown in FIG. 2, a method for forming a semiconductor device by using the above surface-mount semiconductor package will be described. The semiconductor chip 1 is placed in close contact with the recess 2 on the metal base 9. Next, the semiconductor chip 1 and the circuit section 5 are connected by wire bonding. As the bonding wire 11, a gold wire, an aluminum wire, a copper wire, or the like is used.
Thereafter, the semiconductor chip 1 and the bonding wires 11 are sealed and protected by the silicon resin. Further, sealing with an epoxy resin is performed from above. In some cases, only one of these sealing resins 12 may be used.

【0017】このようにして得られた半導体装置は、外
部回路板上にリードレスパッケージとして表面実装され
ている。封止樹脂12は、半導体チップ1と外部回路板
及び絶縁層8で囲まれた空間に配置されており、半導体
装置の外部回路板上への表面実装が可能になっている。
また、金属基材9表面の半導体チップ1と反対側にヒー
トシンク(図示せず)が密着固定される。このヒートシ
ンクにより、半導体チップ1からの発熱が金属基材9を
通して伝熱され、外部空間へと放熱している。
The semiconductor device thus obtained is surface-mounted as a leadless package on an external circuit board. The sealing resin 12 is disposed in a space surrounded by the semiconductor chip 1, the external circuit board, and the insulating layer 8, so that the semiconductor device can be surface-mounted on the external circuit board.
Further, a heat sink (not shown) is tightly fixed on the surface of the metal base 9 opposite to the semiconductor chip 1. With this heat sink, heat generated from the semiconductor chip 1 is transmitted through the metal base material 9 and is radiated to the external space.

【0018】図3は、本発明の実施形態の同上と異なる
表面実装用の半導体パッケージを用いた半導体装置を示
す縦断面図である。同上と異なる点は、絶縁層8及び端
子6の形成方法であり、金属基材9上の回路部5の形成
までは、図2に示す表面実装用の半導体パッケージと同
じ方法により行っている。
FIG. 3 is a longitudinal sectional view showing a semiconductor device using a semiconductor package for surface mounting different from the above embodiment of the present invention. The difference from the above is the method of forming the insulating layer 8 and the terminals 6, and the steps up to the formation of the circuit section 5 on the metal base 9 are performed in the same manner as the surface mounting semiconductor package shown in FIG.

【0019】端子6を形成するためにまず、図4に示す
ように、端子6を並べて必要形状にプレス打ち抜いたス
ルーホール基板20を形成する。図3に示すように、こ
のスルーホール基板20を回路部上に貼り付けるととも
に、回路部5と端子6とを接続する。そのために、スル
ーホール基板20の両面ははんだめっきを行うようにす
る。この半田めっきにおいて端子6の回路部5と接続さ
れる側には比較的高い融点を持つ組成の材料を、端子6
の外部回路板との接続側には低い融点の接合材料をめっ
きするようにする。そうすると外部回路板と端子6との
接合のとき、すでに接合されている端子6と回路部5と
の接合がはずれる等の問題を起こさない。
In order to form the terminals 6, first, as shown in FIG. 4, the through holes 20 are formed by arranging the terminals 6 and stamping out the required shapes. As shown in FIG. 3, the through-hole board 20 is attached on the circuit section, and the circuit section 5 and the terminal 6 are connected. For this purpose, both surfaces of the through-hole substrate 20 are plated with solder. In the solder plating, a material having a composition having a relatively high melting point is coated on the side of the terminal 6 to be connected to the circuit portion 5.
A bonding material having a low melting point is plated on the connection side with the external circuit board. Then, when the external circuit board and the terminal 6 are joined, there is no problem that the already joined terminal 6 and the circuit portion 5 are disconnected.

【0020】図5は、本発明の実施形態の同上と異なる
表面実装用の半導体パッケージを用いた半導体装置を示
す縦断面図である。同上と異なる点は、絶縁層8及び端
子6の形成方法であり、金属基材9上の回路部5の形成
までは、図2に示す表面実装用の半導体パッケージと同
じ方法により行っている。また、図6は、図5に示す表
面実装用の半導体パッケージに用いる絶縁層8を示す斜
視図である。
FIG. 5 is a longitudinal sectional view showing a semiconductor device using a semiconductor package for surface mounting different from that of the embodiment of the present invention. The difference from the above is the method of forming the insulating layer 8 and the terminals 6, and the steps up to the formation of the circuit section 5 on the metal base 9 are performed in the same manner as the surface mounting semiconductor package shown in FIG. FIG. 6 is a perspective view showing the insulating layer 8 used in the semiconductor package for surface mounting shown in FIG.

【0021】図6に示すような端子6を形成する部分に
予め透孔7を形成した板状の絶縁層8を回路部5上に貼
り付ける。その後、図5に示すように、透孔7に端子6
を取付ける。ここでは、球状端子6を示した。端子6は
例えば表面に半田等の複合材料をめっきした銅球であ
る。
As shown in FIG. 6, a plate-like insulating layer 8 in which a through hole 7 is formed in advance in a portion where a terminal 6 is to be formed is adhered on the circuit section 5. Thereafter, as shown in FIG.
Install. Here, the spherical terminal 6 is shown. The terminal 6 is, for example, a copper ball whose surface is plated with a composite material such as solder.

【0022】また、図6に示すような板状の絶縁層8を
貼って絶縁層8を形成するのではなく、図2に示すよう
な印刷によって絶縁層8を形成する方法もある。この後
の半導体チップ1の組み込み、樹脂封止は図2に示した
表面実装用の半導体パッケージと同様である。
Further, instead of pasting the plate-like insulating layer 8 as shown in FIG. 6 to form the insulating layer 8, there is also a method of forming the insulating layer 8 by printing as shown in FIG. Subsequent mounting of the semiconductor chip 1 and resin sealing are the same as those of the semiconductor package for surface mounting shown in FIG.

【0023】[0023]

【発明の効果】請求項1記載の発明では、半導体チップ
に接続される回路部を有する回路基板にスルーホール導
電路を有する絶縁層を積層しているため、スルーホール
導電路の上端部を端子として使用でき、スルーホール導
電路下端に接続される回路部と半導体チップとを封止す
るのに充分な封止樹脂の厚みを確保できるとともに、端
子を外部回路板へ密着固定して表面実装できる半導体装
置が形成できる。さらに、周囲を絶縁層で密着して覆わ
れているため、端子の接続信頼性が向上している。さら
に、基板上の半導体チップと同じ側に端子が設けられて
いるため、基板の下面に半導体チップを冷却するヒート
シンクを設けることができる。したがって、放熱性に優
れた信頼性の高い半導体装置を形成することができる。
According to the first aspect of the present invention, since the insulating layer having the through-hole conductive path is laminated on the circuit board having the circuit part connected to the semiconductor chip, the upper end of the through-hole conductive path is connected to the terminal. As a result, the thickness of the sealing resin sufficient to seal the circuit portion connected to the lower end of the through-hole conductive path and the semiconductor chip can be ensured, and the terminals can be fixed to an external circuit board and surface mounted. A semiconductor device can be formed. Furthermore, since the periphery is closely covered with the insulating layer, the connection reliability of the terminals is improved. Further, since the terminals are provided on the same side as the semiconductor chip on the substrate, a heat sink for cooling the semiconductor chip can be provided on the lower surface of the substrate. Therefore, a highly reliable semiconductor device having excellent heat dissipation properties can be formed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態の表面実装用の半導体パッケ
ージを示す斜視図である。
FIG. 1 is a perspective view showing a semiconductor package for surface mounting according to an embodiment of the present invention.

【図2】同上の表面実装用の半導体パッケージを用いた
半導体装置を示す縦断面図である。
FIG. 2 is a longitudinal sectional view showing a semiconductor device using the semiconductor package for surface mounting according to the first embodiment;

【図3】本発明の実施形態の同上と異なる表面実装用の
半導体パッケージを用いた半導体装置を示す縦断面図で
ある。
FIG. 3 is a longitudinal sectional view showing a semiconductor device using a semiconductor package for surface mounting different from the above according to the embodiment of the present invention.

【図4】同上の表面実装用の半導体パッケージの要部を
示す斜視図である。
FIG. 4 is a perspective view showing a main part of the semiconductor package for surface mounting according to the first embodiment;

【図5】本発明の実施形態の同上と異なる表面実装用の
半導体パッケージを用いた半導体装置を示す縦断面図で
ある。
FIG. 5 is a longitudinal sectional view showing a semiconductor device using a semiconductor package for surface mounting different from the above according to the embodiment of the present invention.

【図6】同上の表面実装用の半導体パッケージの要部を
示す斜視図である。
FIG. 6 is a perspective view showing a main part of the semiconductor package for surface mounting according to the first embodiment;

【図7】従来の表面実装用の半導体パッケージを用いた
半導体装置を示す縦断面図である。
FIG. 7 is a longitudinal sectional view showing a semiconductor device using a conventional semiconductor package for surface mounting.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 凹部 3 肩部 4 スルーホール導電路 5 回路部 6 端子 7 透孔 8 絶縁層 9 金属基材 10 基板絶縁層 11 ボンディングワイヤ 12 封止樹脂 13 外部回路板 14 ヒートシンク 16 絶縁性薄層 17 配線基板 18 貫通孔 19 接着剤 20 スルーホール基板 21 回路基板 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Depression 3 Shoulder part 4 Through-hole conductive path 5 Circuit part 6 Terminal 7 Through hole 8 Insulating layer 9 Metal substrate 10 Substrate insulating layer 11 Bonding wire 12 Sealing resin 13 External circuit board 14 Heat sink 16 Insulating thin layer 17 Wiring Board 18 Through Hole 19 Adhesive 20 Through Hole Board 21 Circuit Board

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 23/12 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/12

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体チップを搭載する凹部と、この凹
部周囲の肩部に設けた回路部とを備える回路基板を形成
し、この回路基板の回路部上に透孔を有する絶縁層を積
層し、この透孔を貫通して下端部が回路部に接続導通す
るとともに、上端部が絶縁層上面に突出するスルーホー
ル導電路を形成し、このスルーホール導電路は上端部お
よび下端部が一体に形成され、このスルーホール導電路
の上端部を回路基板上の凹部および肩部と同じ側に設け
た表面実装用の端子に形成してなることを特徴とする表
面実装用の半導体パッケージ。
1. A circuit board having a recess for mounting a semiconductor chip and a circuit section provided on a shoulder around the recess is formed, and an insulating layer having a through hole is laminated on the circuit section of the circuit board. The lower end portion penetrates the through-hole to connect and conduct with the circuit portion, and the upper end portion forms a through-hole conductive path protruding from the upper surface of the insulating layer .
And a lower end portion are integrally formed, and an upper end portion of the through-hole conductive path is formed on a surface mounting terminal provided on the same side as the concave portion and the shoulder portion on the circuit board. Semiconductor package.
JP11334626A 1999-11-25 1999-11-25 Semiconductor package for surface mounting Expired - Lifetime JP3117688B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11334626A JP3117688B2 (en) 1999-11-25 1999-11-25 Semiconductor package for surface mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11334626A JP3117688B2 (en) 1999-11-25 1999-11-25 Semiconductor package for surface mounting

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP9300474A Division JP3039485B2 (en) 1997-10-31 1997-10-31 Semiconductor package for surface mounting and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JP2000150717A JP2000150717A (en) 2000-05-30
JP3117688B2 true JP3117688B2 (en) 2000-12-18

Family

ID=18279493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11334626A Expired - Lifetime JP3117688B2 (en) 1999-11-25 1999-11-25 Semiconductor package for surface mounting

Country Status (1)

Country Link
JP (1) JP3117688B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006108261A (en) * 2004-10-01 2006-04-20 Sony Corp Function element package and its manufacturing method
KR102041625B1 (en) * 2012-12-13 2019-11-06 주식회사 두산 Semiconductor package and method of manufacturing thereof

Also Published As

Publication number Publication date
JP2000150717A (en) 2000-05-30

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