JPH1098127A - Semiconductor package for surface mounting - Google Patents

Semiconductor package for surface mounting

Info

Publication number
JPH1098127A
JPH1098127A JP8252113A JP25211396A JPH1098127A JP H1098127 A JPH1098127 A JP H1098127A JP 8252113 A JP8252113 A JP 8252113A JP 25211396 A JP25211396 A JP 25211396A JP H1098127 A JPH1098127 A JP H1098127A
Authority
JP
Japan
Prior art keywords
substrate
heat
hole
metal layer
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8252113A
Other languages
Japanese (ja)
Inventor
Kaoru Mukai
薫 向井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP8252113A priority Critical patent/JPH1098127A/en
Publication of JPH1098127A publication Critical patent/JPH1098127A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To obtain superior heat radiation by providing heat conductors inside a through-hole plating metal layer, connected to through-holes exposed at a semiconductor element-mounting part through a wiring circuit among through- holes exposed at parts, except the mounting part. SOLUTION: Thermal conductors 22 located inside a plating metal layer 21 of first through-holes 13 exposed on a semiconductor element mounting part 12 of a substrate 10 to efficiently transfer the heat of a semiconductor element 2 to the opposite surface to the semiconductor element-mounting surface of the substrate 10 through the conductors 22 and metal layer 21, thereby radiating the heat through electrodes 15 to a mother board. Of second through-holes 14a, 14b, heat conductors 22 are disposed inside the plating metal layer 21 of the holes 14a, connected to the first through-holes 13 through a wiring circuit 11 to thereby efficiently transfer heat to the opposite surface to the semiconductor element 2 mounting surface and radiate to the mother board. Thus it is possible to radiate much heat to the mother board.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
に使用される半導体パッケージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package used for manufacturing a semiconductor device.

【0002】[0002]

【従来の技術】表面実装用半導体装置とて、金属製のリ
ードフレームの上に半導体素子を接着した後、ボンディ
ングワイヤーを用いてリードフレームと半導体素子を電
気的に接続し、次いで、半導体素子全体及びリードフレ
ームの一部等を封止材で封止して製造した半導体装置
や、図3に示すような、有機系の基板30の一方の面に
は、半導体素子36を実装しようとする半導体素子配置
部32と、半導体素子36とボンディングワイヤー37
等で電気的に接続可能に形成したボンディング回路34
を有し、基板30の他方の面には、基板30を貫通して
形成したスルホール33a,33bや配線回路31を介
してボンディング回路34と電気的に接続した電極35
を有する半導体パッケージを用いて、半導体素子36を
実装した後、ボンディングワイヤー37を用いてボンデ
ィング回路34と半導体素子36を接続し、次いで、封
止材38で封止した後、電極35に母基板(半導体装置
を実装するプリント配線板)に実装するためのハンダバ
ンプ39を形成して製造した半導体装置が用いられてい
る。
2. Description of the Related Art As a semiconductor device for surface mounting, a semiconductor element is bonded onto a metal lead frame, and then the lead frame and the semiconductor element are electrically connected using bonding wires. In addition, a semiconductor device manufactured by sealing a part of a lead frame or the like with a sealing material, or a semiconductor on which a semiconductor element 36 is to be mounted on one surface of an organic substrate 30 as shown in FIG. The element arrangement part 32, the semiconductor element 36 and the bonding wire 37
Bonding circuit 34 formed electrically connectable by
And an electrode 35 electrically connected to a bonding circuit 34 via through holes 33 a and 33 b formed through the substrate 30 and the wiring circuit 31 on the other surface of the substrate 30.
After the semiconductor element 36 is mounted using a semiconductor package having the following, the bonding circuit 34 and the semiconductor element 36 are connected using the bonding wires 37, and then sealed with the sealing material 38, and then the mother board is attached to the electrode 35. A semiconductor device manufactured by forming solder bumps 39 for mounting on a (printed wiring board on which the semiconductor device is mounted) is used.

【0003】近年の半導体装置の高機能化により、半導
体素子の発生する熱が増加する傾向にある。半導体素子
の発生する熱が増加して半導体素子の温度が高くなる
と、半導体装置の動作が不安定になり、信頼性が低下す
るという問題があった。特に有機系の基板に半導体素子
を実装した半導体装置は、リードフレームを用いた半導
体素子と比較して放熱性が低く、半導体装置の動作が不
安定になりやすいため、放熱性の優れた半導体装置が望
まれている。
[0003] In recent years, semiconductor devices have become more sophisticated, and the heat generated by semiconductor elements tends to increase. When the heat generated by the semiconductor element increases and the temperature of the semiconductor element increases, the operation of the semiconductor device becomes unstable, and the reliability is reduced. In particular, a semiconductor device in which a semiconductor element is mounted on an organic substrate has a lower heat radiation property than a semiconductor element using a lead frame, and the operation of the semiconductor device is likely to be unstable. Is desired.

【0004】そのため、図3に示すような、有機系の基
板30を表裏に貫通して形成し、基板30と接する部分
に円筒形のメッキ金属層を有するスルホール33bを、
基板30の表面のうち半導体素子配置部32に露出する
部分に形成し、半導体素子36の発生する熱を、そのス
ルホール33bを通して基板30の半導体素子配置部3
2を形成した面と反対の面に効率よく伝え、その熱を母
基板に放熱させるようにした半導体装置や、上記半導体
素子配置部32に露出する部分に形成したスルホール3
3bの、円筒形メッキ金属層の内側にハンダ等の熱伝導
性の高い物質を充填し、更に放熱性を向上させた半導体
装置等が検討されている。
For this reason, as shown in FIG. 3, an organic substrate 30 is formed penetrating from the front to the back, and a through hole 33b having a cylindrical plated metal layer at a portion in contact with the substrate 30 is formed.
It is formed on a portion of the surface of the substrate 30 that is exposed to the semiconductor element placement section 32, and transfers heat generated by the semiconductor element 36 to the semiconductor element placement section 3 of the substrate 30 through the through hole 33b.
A semiconductor device in which heat is efficiently transmitted to the surface opposite to the surface on which the substrate 2 is formed and the heat is radiated to the mother substrate;
A semiconductor device 3b in which a material having high thermal conductivity such as solder is filled inside the cylindrical plating metal layer 3b to further improve the heat dissipation is being studied.

【0005】しかし、半導体素子配置部32に露出する
部分に形成したスルホール33bを通して半導体素子3
6が発生する熱を母基板に放熱させるようにした半導体
装置等の場合であっても、半導体素子の発生する熱が更
に増加すると放熱性が不十分となり、半導体装置の動作
が不安定となる場合があった。そのため、更に放熱性が
優れた半導体装置を製造することができる半導体パッケ
ージが求められている。
However, through the through holes 33b formed in the portions exposed to the semiconductor element arrangement part 32, the semiconductor elements 3
Even in the case of a semiconductor device or the like in which the heat generated by 6 is radiated to the mother substrate, if the heat generated by the semiconductor element further increases, the heat dissipation becomes insufficient, and the operation of the semiconductor device becomes unstable. There was a case. Therefore, there is a need for a semiconductor package that can manufacture a semiconductor device having even better heat dissipation.

【0006】[0006]

【発明が解決しようとする課題】本発明は、上記問題点
を改善するために成されたもので、その目的とするとこ
ろは、有機系基板を用いた表面実装用半導体パッケージ
であって、放熱性が優れた表面実装用半導体装置を製造
することができる表面実装用半導体パッケージを提供す
ることにある。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor package for surface mounting using an organic substrate, and An object of the present invention is to provide a surface-mount semiconductor package capable of manufacturing a surface-mount semiconductor device having excellent performance.

【0007】[0007]

【課題を解決するための手段】本発明の請求項1に係る
表面実装用半導体パッケージは、配線回路を有する有機
系基板の一方の面に形成した半導体素子配置部に露出す
ると共に、基板を表裏に貫通して形成した第一のスルホ
ールであって、基板と接する部分に円筒形のメッキ金属
層を有し、そのメッキ金属層の内側に導熱体を有する第
一のスルホールと、基板の上記一方の面のうち、半導体
素子配置部を除く部分に露出すると共に、基板を表裏に
貫通して形成し、基板と接する部分に円筒形のメッキ金
属層を有する第二のスルホールと、基板の他方の面に、
第二のスルホールが備えるメッキ金属層と接続して形成
した、母基板と接続を予定する電極とを備える表面実装
用半導体パッケージにおいて、第二のスルホールのう
ち、配線回路を介して第一のスルホールと接続した第二
のスルホールのメッキ金属層の内側にも、導熱体を有す
ることを特徴とする。
According to a first aspect of the present invention, there is provided a semiconductor package for surface mounting, which is exposed to a semiconductor element disposing portion formed on one surface of an organic substrate having a wiring circuit, and the substrate is mounted on both sides. A first through-hole formed through the first through-hole, the first through-hole having a cylindrical plated metal layer in a portion in contact with the substrate, and having a heat conductor inside the plated metal layer; A second through hole having a cylindrical plated metal layer in a portion exposed to a portion excluding the semiconductor element arrangement portion and penetrating the substrate from front to back and a surface in contact with the substrate, and the other of the substrate, On the surface,
In a surface-mount semiconductor package including a mother substrate and an electrode to be connected, formed by connecting to a plating metal layer provided in a second through hole, a first through hole of a second through hole is provided via a wiring circuit. A heat conductor is also provided inside the plated metal layer of the second through hole connected to the second through hole.

【0008】本発明の請求項2に係る表面実装用半導体
パッケージは、請求項1記載の表面実装用半導体パッケ
ージにおいて、導熱体が、金属粉含有樹脂であることを
特徴とする。
According to a second aspect of the present invention, there is provided a surface mounting semiconductor package according to the first aspect, wherein the heat conductor is a resin containing a metal powder.

【0009】本発明の請求項3に係る表面実装用半導体
パッケージは、請求項1記載の表面実装用半導体パッケ
ージにおいて、導熱体が、金属棒と金属粉含有樹脂の複
合体であることを特徴とする。
According to a third aspect of the present invention, there is provided a semiconductor package for surface mounting according to the first aspect, wherein the heat conductor is a composite of a metal rod and a resin containing metal powder. I do.

【0010】本発明の請求項4に係る表面実装用半導体
パッケージは、請求項1から請求項3のいずれかに記載
の表面実装用半導体パッケージにおいて、導熱体が、基
板の表面に形成された配線回路より、突出して形成され
ていることを特徴とする。
According to a fourth aspect of the present invention, there is provided a semiconductor package for surface mounting according to any one of the first to third aspects, wherein the heat conductor is formed on a surface of the substrate. It is characterized by being formed so as to protrude from the circuit.

【0011】本発明の請求項5に係る表面実装用半導体
パッケージは、請求項1から請求項4のいずれかに記載
の表面実装用半導体パッケージにおいて、金属放熱体
を、基板の上記一方の面のうち、第二のスルホールが露
出する部分に接着して成ることを特徴とする。
According to a fifth aspect of the present invention, there is provided a surface mounting semiconductor package according to any one of the first to fourth aspects, wherein a metal radiator is provided on the one surface of the substrate. Preferably, the second through hole is bonded to a portion where the second through hole is exposed.

【0012】本発明によると、第一のスルホールのメッ
キ金属層の内側に導熱体を有していると共に、第二のス
ルホールのうち、配線回路を介して第一のスルホールと
接続した第二のスルホールのメッキ金属層の内側にも導
熱体を有しているため、半導体素子の発生する熱を、多
くの導熱体及びメッキ金属層を通して基板の半導体素子
を実装する面と反対の面に効率よく伝熱し、その熱を電
極等を通じて母基板に放熱させることが可能となってい
る。
According to the present invention, the heat conductor is provided inside the plating metal layer of the first through hole, and the second through hole of the second through hole connected to the first through hole via the wiring circuit is provided. Since the heat conductor is also provided inside the plated metal layer of the through hole, the heat generated by the semiconductor element can be efficiently transferred to the surface of the substrate opposite to the surface on which the semiconductor element is mounted through many heat conductors and the plated metal layer. Heat can be transferred and the heat can be radiated to the motherboard through electrodes and the like.

【0013】そのため、第一のスルホールのみで母基板
側に伝熱する場合と比較して、多くの熱を伝熱して母基
板に放熱可能となり、この半導体パッケージを用いると
放熱性が優れた表面実装用半導体装置を製造することが
可能となる。
Therefore, as compared with the case where heat is transferred to the mother board only by the first through hole, a larger amount of heat can be transferred and heat can be dissipated to the mother board. A semiconductor device for mounting can be manufactured.

【0014】[0014]

【発明の実施の形態】本発明に係る表面実装用半導体パ
ッケージを図面に基づいて説明する。図1は本発明に係
る表面実装用半導体パッケージの一実施の形態を説明す
る断面図であり、図2は本発明に係る表面実装用半導体
パッケージの他の実施の形態を説明する断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor package for surface mounting according to the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor package for surface mounting according to the present invention, and FIG. 2 is a cross-sectional view illustrating another embodiment of a semiconductor package for surface mounting according to the present invention. .

【0015】本発明の表面実装用半導体パッケージは、
図1に示すように、配線回路11を有する有機系基板1
0の一方の面に形成した半導体素子配置部12に露出す
ると共に、基板10を表裏に貫通して形成され、基板1
0と接する部分に円筒形のメッキ金属層21を有する第
一のスルホール13と、基板10の上記一方の面のう
ち、半導体素子配置部12を除く部分に露出すると共
に、基板10を表裏に貫通して形成され、基板10と接
する部分に円筒形のメッキ金属層21を有する第二のス
ルホール14a,14bと、基板10の他方の面に、第
二のスルホール14a,14bが備えるメッキ金属層2
1と接続して形成され、母基板と接続を予定する電極1
5とを備える。
The semiconductor package for surface mounting according to the present invention comprises:
As shown in FIG. 1, an organic substrate 1 having a wiring circuit 11
The substrate 1 is exposed to the semiconductor element disposition portion 12 formed on one surface of the substrate 1 and penetrates the substrate 10 from front to back.
A first through-hole 13 having a cylindrical plated metal layer 21 at a portion in contact with a portion 0 and a first through-hole 13 exposing a portion of the one surface of the substrate 10 excluding the semiconductor element disposing portion 12 and penetrating the substrate 10 from front to back. Second through holes 14a and 14b having a cylindrical plating metal layer 21 at a portion in contact with the substrate 10, and a plating metal layer 2 having the second through holes 14a and 14b on the other surface of the substrate 10.
Electrode 1 formed to be connected to mother substrate 1 and to be connected to mother substrate
5 is provided.

【0016】そして、第一のスルホール13のメッキ金
属層21の内側には導熱体22を有しており、半導体素
子2の発生する熱を、その導熱体22及びメッキ金属層
21を通して基板10の半導体素子2を実装する面と反
対の面に効率よく伝熱し、その熱を電極15等を通じて
母基板に放熱させるようになっている。また、第二のス
ルホール14a,14bのうち、配線回路11を介して
第一のスルホール13と接続された第二のスルホール1
4aの、メッキ金属層21の内側にも導熱体22を有し
ており、半導体素子2の発生する熱を、配線回路11や
導熱体22及びメッキ金属層21を通して基板10の半
導体素子2を実装する面と反対の面に効率よく伝熱し、
その熱を電極15等を通じて母基板に放熱させるように
なっている。
A heat conductor 22 is provided inside the plating metal layer 21 in the first through hole 13, and heat generated by the semiconductor element 2 is transferred to the substrate 10 through the heat conductor 22 and the plating metal layer 21. The heat is efficiently transferred to the surface opposite to the surface on which the semiconductor element 2 is mounted, and the heat is radiated to the mother board through the electrodes 15 and the like. Also, of the second through holes 14a and 14b, the second through hole 1 connected to the first through hole 13 via the wiring circuit 11 is provided.
4a, a heat conductor 22 is also provided inside the plated metal layer 21. The heat generated by the semiconductor element 2 is transferred to the semiconductor element 2 of the substrate 10 through the wiring circuit 11, the heat conductor 22, and the plated metal layer 21. Efficiently transfer heat to the surface opposite to
The heat is radiated to the mother board through the electrodes 15 and the like.

【0017】そのため、第一のスルホール13のみで母
基板側に伝熱する場合と比較して、多くの熱を伝熱して
母基板に放熱可能となり、この半導体パッケージを用い
ると放熱性が優れた表面実装用半導体装置を製造するこ
とが可能となる。
Therefore, as compared with the case where heat is transferred to the mother board only by the first through hole 13, a larger amount of heat can be transferred and heat can be radiated to the mother board. A semiconductor device for surface mounting can be manufactured.

【0018】なお、第二のスルホール14a,14bの
うち、配線回路11を介して第一のスルホール13と接
続された第二のスルホール14aから、更に配線回路1
1を介して接続された第二のスルホール(図示せず)で
あって、第一のスルホール13とは直接接続していない
第二のスルホールが存在する場合、その第二のスルホー
ルのメッキ金属層21の内側にも導熱体22を有してい
ると、更に放熱性が優れ好ましい。
The second through hole 14a, which is connected to the first through hole 13 via the wiring circuit 11 among the second through holes 14a and 14b,
If there is a second through hole (not shown) connected via the first through hole 1 and not directly connected to the first through hole 13, the plating metal layer of the second through hole It is preferable that the heat conductor 22 is also provided inside 21 so as to further improve heat dissipation.

【0019】なお、導熱体22としては、熱伝導性が高
く、メッキ金属層21の内側に充填可能であり、かつ、
半導体装置を母基板に実装するときの半田付け温度等に
耐えるものであれば特に限定するものではなく、例えば
銀ペースト、銅ペースト等の金属粉含有樹脂や、図2に
示すような、金属棒221と金属粉含有樹脂の複合体等
が挙げられる。金属粉含有樹脂の場合、メッキ金属層2
1の径が小さい場合であっても、内部まで容易に充填す
ることができ好ましい。また、メッキ金属層21の内側
に金属棒221を挿入した後、メッキ金属層21と金属
棒221の間に金属粉含有樹脂を充填する方法等で金属
棒221と金属粉含有樹脂の複合体を充填すると、一般
に金属粉含有樹脂より金属棒221の方が熱伝導性が高
いため、導熱体22全体の放熱性が高くなり好ましい。
The heat conductor 22 has a high thermal conductivity and can be filled inside the plated metal layer 21.
There is no particular limitation as long as it can withstand the soldering temperature and the like when the semiconductor device is mounted on the motherboard. For example, a resin containing metal powder such as silver paste and copper paste, or a metal rod as shown in FIG. 221 and a metal powder-containing resin. In the case of a resin containing metal powder, the plating metal layer 2
Even if the diameter of 1 is small, it can be easily filled into the inside, which is preferable. Further, after inserting the metal rod 221 inside the plating metal layer 21, the composite of the metal rod 221 and the metal powder-containing resin is filled with the metal powder-containing resin between the plating metal layer 21 and the metal rod 221. When filled, since the metal rod 221 generally has higher thermal conductivity than the metal powder-containing resin, the heat dissipation of the entire heat conducting body 22 is high, which is preferable.

【0020】なお、導熱体22を形成する場合には、図
2に示すように、基板10の表面に形成された配線回路
11より突出するように、導熱体22を形成すると好ま
しい。第一のスルホール13が半導体素子配置部12に
露出する部分で配線回路11より突出して導熱体22が
形成されている場合、半導体素子2を実装したとき、突
出する導熱体22と半導体素子2が接して配線回路11
等と半導体素子2との間に隙間ができるため、その後封
止材で封止するときに、その隙間に封止材が侵入して封
止の信頼性を向上することができ好ましい。また、第二
のスルホール14aが半導体素子配置部12を形成した
面と反対の面に露出する部分で配線回路11より突出し
て導熱体22が形成されている場合、この半導体パッケ
ージを用いて製造した半導体装置を母基板に実装すると
きに、電極15と母基板の間に適度な隙間を形成できる
ため、半田付けの信頼性を向上することができ好まし
い。なお、これらの突出する部分は、金属棒221で形
成すると強度が優れ好ましい。
When the heat conductor 22 is formed, as shown in FIG. 2, it is preferable to form the heat conductor 22 so as to protrude from the wiring circuit 11 formed on the surface of the substrate 10. When the heat conductor 22 is formed so as to protrude from the wiring circuit 11 at a portion where the first through hole 13 is exposed to the semiconductor element disposition portion 12, when the semiconductor element 2 is mounted, the protruding heat conductor 22 and the semiconductor element 2 Wiring circuit 11
Since a gap is formed between the semiconductor element 2 and the like, when sealing with a sealing material thereafter, the sealing material enters the gap, which is preferable because the reliability of the sealing can be improved. In the case where the heat conductor 22 is formed so as to protrude from the wiring circuit 11 at a portion where the second through hole 14a is exposed on the surface opposite to the surface on which the semiconductor element arrangement portion 12 is formed, the semiconductor package is manufactured. When the semiconductor device is mounted on the motherboard, an appropriate gap can be formed between the electrode 15 and the motherboard, so that the reliability of soldering can be improved, which is preferable. In addition, it is preferable that these protruding portions have excellent strength when formed with a metal rod 221.

【0021】なお、第一のスルホール13及び第二のス
ルホール14a,14bが有する円筒形のメッキ金属層
21としては、基板10を表裏に貫通して形成され、基
板10と接する部分にメッキにより形成したものであれ
ば特に限定するものではなく、化学銅メッキや電気銅メ
ッキ等により形成したものが挙げられる。
The cylindrical plated metal layer 21 of the first through-hole 13 and the second through-holes 14a and 14b is formed by penetrating the substrate 10 from the front and back, and is formed by plating on the portion in contact with the substrate 10. The material is not particularly limited as long as it is formed, and may be formed by chemical copper plating, electrolytic copper plating, or the like.

【0022】また、本発明に用いられる基板10として
は、有機系であり、かつ、配線回路11が形成されてい
るものであれば特に限定するものではなく、例えば、エ
ポキシ樹脂系、フェノール樹脂系、ポリイミド樹脂系、
不飽和ポリエステル樹脂系、ポリフェニレンエーテル樹
脂系等の熱硬化性樹脂や、これらの熱硬化性樹脂に無機
充填材等を配合したもののシートの片面又は両面に金属
箔が張られている板や、ガラス等の無機質繊維やポリエ
ステル、ポリアミド、木綿等の有機質繊維のクロス、ペ
ーパー等の基材を、上記熱硬化性樹脂等で接着し、片面
又は両面に金属箔が張られている板等を用いて、金属メ
ッキを行った後、所定の部分をエッチングして配線回路
11を形成したもの、及び、金属箔が張られていない板
に金属メッキを行い、配線回路11を形成したもの等が
挙げられる。なお、配線回路11を形成する金属として
は、電気的信頼性より銅や、銅の表面に金めっき層を形
成したものが好ましい。
The substrate 10 used in the present invention is not particularly limited as long as it is organic and has a wiring circuit 11 formed thereon. Examples thereof include epoxy resin and phenol resin. , Polyimide resin,
Unsaturated polyester resin type, thermosetting resin such as polyphenylene ether resin type, or a sheet in which a metal foil is stretched on one or both sides of a sheet of a sheet obtained by blending an inorganic filler or the like with these thermosetting resins, or glass Insulation of inorganic fibers such as polyester, polyester, polyamide, and organic fibers such as cotton, and a substrate such as paper, using a thermosetting resin or the like, and bonding a metal foil on one or both surfaces using a plate or the like. A wiring circuit 11 formed by etching a predetermined portion after performing metal plating, and a wiring circuit 11 formed by performing metal plating on a plate not covered with metal foil. . The metal forming the wiring circuit 11 is preferably copper or a metal formed with a gold plating layer on the surface of copper from the viewpoint of electrical reliability.

【0023】なお、第一のスルホール13と第二のスル
ホール14aを接続する配線回路11は、基板10の内
層に形成された配線回路11により接続されているもの
でもよく、基板10の表面に形成された配線回路11に
より接続されているものでもよい。
The wiring circuit 11 for connecting the first through hole 13 and the second through hole 14a may be connected by the wiring circuit 11 formed on the inner layer of the substrate 10, or may be formed on the surface of the substrate 10. Connected by the wiring circuit 11 may be used.

【0024】また、半導体素子配置部12は、図1に示
すように、基板10に凹状に形成されていてもよく、図
2に示すように、周囲の部分と同じ高さの面に形成され
ていてもよい。
The semiconductor element disposing portion 12 may be formed in a concave shape on the substrate 10 as shown in FIG. 1, or formed on a surface having the same height as the surrounding portion as shown in FIG. May be.

【0025】また、銅板等の金属放熱体16を、基板1
0の上記一方の面のうち、第二のスルホール14a,1
4bが露出する部分に、エポキシ樹脂等の接着剤で接着
して形成した半導体パッケージの場合、金属放熱体16
からも放熱することが可能なため、更に放熱性が優れ好
ましい。なお、金属放熱体16の第二のスルホール14
a,14bと接触する部分には接着剤をつけずに、金属
放熱体16と第二のスルホール14a,14bが直接接
触するようにすると、放熱性が特に優れ好ましい。
A metal radiator 16 such as a copper plate is
0 of the one surface, the second through holes 14a, 1
In the case of a semiconductor package formed by bonding an exposed portion 4b with an adhesive such as an epoxy resin, the metal radiator 16
Since heat can also be dissipated, the heat dissipating property is further excellent and preferable. The second through hole 14 of the metal radiator 16
If the metal heat radiator 16 and the second through holes 14a and 14b are in direct contact with each other without applying an adhesive to the portions that come into contact with the holes a and 14b, the heat radiation properties are particularly excellent and preferable.

【0026】[0026]

【発明の効果】本発明に係る表面実装用半導体パッケー
ジは、第一のスルホールのメッキ金属層の内側に導熱体
を有していると共に、第二のスルホールのうち、配線回
路を介して第一のスルホールと接続した第二のスルホー
ルのメッキ金属層の内側にも導熱体を有しているため、
半導体素子の発生する熱を、多くの導熱体及びメッキ金
属層を通して基板の半導体素子を実装する面と反対の面
に効率よく伝熱し、その熱を電極等を通じて母基板に放
熱させることが可能となっているため、第一のスルホー
ルのみで母基板側に伝熱する場合と比較して、多くの熱
を伝熱して母基板に放熱可能となり、この半導体パッケ
ージを用いると放熱性が優れた表面実装用半導体装置を
製造することが可能となる。
The semiconductor package for surface mounting according to the present invention has a heat conductor inside the plated metal layer of the first through hole and the first through hole of the second through hole via the wiring circuit. Because it also has a heat conductor inside the plated metal layer of the second through hole connected to the through hole of
It is possible to efficiently transfer the heat generated by the semiconductor element through many heat conductors and plated metal layers to the surface opposite to the surface on which the semiconductor element is mounted on the substrate, and dissipate that heat to the mother substrate through electrodes and the like. As compared with the case where heat is transferred to the motherboard only by the first through hole, more heat can be transferred to the motherboard and heat can be radiated to the motherboard. A semiconductor device for mounting can be manufactured.

【0027】本発明の請求項4に係る表面実装用半導体
パッケージによると、上記の効果に加え更に、半導体素
子を実装した後封止材で封止するときの、封止の信頼性
が向上したり、この半導体パッケージを用いて製造した
半導体装置を母基板に実装するときの、半田付けの信頼
性が向上する。
According to the semiconductor package for surface mounting according to claim 4 of the present invention, in addition to the above-described effects, the reliability of the sealing when the semiconductor element is mounted and then sealed with a sealing material is improved. In addition, the reliability of soldering when a semiconductor device manufactured using this semiconductor package is mounted on a motherboard is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る表面実装用半導体パッケージの一
実施の形態を説明する断面図である。
FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor package for surface mounting according to the present invention.

【図2】本発明に係る表面実装用半導体パッケージの他
の実施の形態を説明する断面図である。
FIG. 2 is a cross-sectional view illustrating another embodiment of the semiconductor package for surface mounting according to the present invention.

【図3】従来の半導体パッケージを用いた半導体装置を
説明する断面図である。
FIG. 3 is a cross-sectional view illustrating a semiconductor device using a conventional semiconductor package.

【符号の説明】[Explanation of symbols]

2 ,36 半導体素子 10,30 基板 11,31 配線回路 12,32 半導体素子配置部 13 第一のスルホール 14a,14b 第二のスルホール 15,35 電極 16 金属放熱体 21 メッキ金属層 22 導熱体 37 ボンディングワイヤー 38 封止材 39 ハンダバンプ 2, 36 Semiconductor element 10, 30 Substrate 11, 31 Wiring circuit 12, 32 Semiconductor element arrangement part 13 First through hole 14a, 14b Second through hole 15, 35 Electrode 16 Metal radiator 21 Plated metal layer 22 Heat conductor 37 Bonding Wire 38 Sealant 39 Solder bump

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 配線回路(11)を有する有機系基板
(10)の一方の面に形成した半導体素子配置部(1
2)に露出すると共に、基板(10)を表裏に貫通して
形成した第一のスルホール(13)であって、基板(1
0)と接する部分に円筒形のメッキ金属層(21)を有
し、そのメッキ金属層(21)の内側に導熱体(22)
を有する第一のスルホール(13)と、基板(10)の
上記一方の面のうち、半導体素子配置部(12)を除く
部分に露出すると共に、基板(10)を表裏に貫通して
形成し、基板(10)と接する部分に円筒形のメッキ金
属層(21)を有する第二のスルホール(14a,14
b)と、基板(10)の他方の面に、第二のスルホール
(14a,14b)が備えるメッキ金属層(21)と接
続して形成した、母基板と接続を予定する電極(15)
とを備える表面実装用半導体パッケージにおいて、第二
のスルホール(14a,14b)のうち、配線回路(1
1)を介して第一のスルホール(13)と接続した第二
のスルホール(14a)のメッキ金属層(21)の内側
にも、導熱体(22)を有することを特徴とする表面実
装用半導体パッケージ。
A semiconductor element placement part (1) formed on one surface of an organic substrate (10) having a wiring circuit (11).
A first through hole (13) that is exposed to the substrate (2) and penetrates the substrate (10) from front to back,
0) has a cylindrical plated metal layer (21) at a portion in contact with the heat conductive body (22) inside the plated metal layer (21).
And a first through-hole (13) having a surface exposed on the one surface of the substrate (10) except for the semiconductor element disposing portion (12), and penetrating the substrate (10) from front to back. A second through hole (14a, 14a) having a cylindrical plated metal layer (21) at a portion in contact with the substrate (10).
b) and an electrode (15) which is formed on the other surface of the substrate (10) by being connected to the plated metal layer (21) provided in the second through holes (14a, 14b) and which is to be connected to the mother substrate.
In the semiconductor package for surface mounting provided with: the wiring circuit (1) in the second through holes (14a, 14b).
A semiconductor for surface mounting, comprising a heat conductor (22) also inside a plated metal layer (21) of a second through hole (14a) connected to a first through hole (13) via 1). package.
【請求項2】 導熱体(22)が、金属粉含有樹脂であ
ることを特徴とする請求項1記載の表面実装用半導体パ
ッケージ。
2. The semiconductor package for surface mounting according to claim 1, wherein the heat conductor is a resin containing metal powder.
【請求項3】 導熱体(22)が、金属棒(221)と
金属粉含有樹脂の複合体であることを特徴とする請求項
1記載の表面実装用半導体パッケージ。
3. The semiconductor package for surface mounting according to claim 1, wherein the heat conductor is a composite of a metal rod and a resin containing metal powder.
【請求項4】 導熱体(22)が、基板(10)の表面
に形成された配線回路(11)より、突出して形成され
ていることを特徴とする請求項1から請求項3のいずれ
かに記載の表面実装用半導体パッケージ。
4. The heat conductor (22) is formed so as to protrude from a wiring circuit (11) formed on a surface of a substrate (10). 2. The semiconductor package for surface mounting according to 1.
【請求項5】 金属放熱体(16)を、基板(10)の
上記一方の面のうち、第二のスルホール(14a,14
b)が露出する部分に接着して成ることを特徴とする請
求項1から請求項4のいずれかに記載の表面実装用半導
体パッケージ。
5. A metal radiator (16) is provided on a second through hole (14a, 14a, 14a, 14a) of the one surface of the substrate (10).
The semiconductor package for surface mounting according to any one of claims 1 to 4, wherein the semiconductor package is bonded to a portion where b) is exposed.
JP8252113A 1996-09-24 1996-09-24 Semiconductor package for surface mounting Pending JPH1098127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8252113A JPH1098127A (en) 1996-09-24 1996-09-24 Semiconductor package for surface mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8252113A JPH1098127A (en) 1996-09-24 1996-09-24 Semiconductor package for surface mounting

Publications (1)

Publication Number Publication Date
JPH1098127A true JPH1098127A (en) 1998-04-14

Family

ID=17232665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8252113A Pending JPH1098127A (en) 1996-09-24 1996-09-24 Semiconductor package for surface mounting

Country Status (1)

Country Link
JP (1) JPH1098127A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001308388A (en) * 2000-04-27 2001-11-02 Rohm Co Ltd Chip light-emitting element
JP2007134645A (en) * 2005-11-14 2007-05-31 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing the same
JP2007234303A (en) * 2006-02-28 2007-09-13 Minebea Co Ltd Planar lighting system
JP2010187031A (en) * 2010-05-31 2010-08-26 Rohm Co Ltd Chip type light emitting element
EP2472577A2 (en) 2011-01-04 2012-07-04 Napra Co., Ltd. Substrate for electronic device and electronic device
JP2012209537A (en) * 2011-03-16 2012-10-25 Napura:Kk Lighting apparatus, display, and signal light

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001308388A (en) * 2000-04-27 2001-11-02 Rohm Co Ltd Chip light-emitting element
JP2007134645A (en) * 2005-11-14 2007-05-31 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing the same
JP2007234303A (en) * 2006-02-28 2007-09-13 Minebea Co Ltd Planar lighting system
JP4654942B2 (en) * 2006-02-28 2011-03-23 ミネベア株式会社 Surface lighting device
JP2010187031A (en) * 2010-05-31 2010-08-26 Rohm Co Ltd Chip type light emitting element
EP2472577A2 (en) 2011-01-04 2012-07-04 Napra Co., Ltd. Substrate for electronic device and electronic device
CN102593100A (en) * 2011-01-04 2012-07-18 纳普拉有限公司 Substrate for electronic device and electronic device
US9704793B2 (en) 2011-01-04 2017-07-11 Napra Co., Ltd. Substrate for electronic device and electronic device
JP2012209537A (en) * 2011-03-16 2012-10-25 Napura:Kk Lighting apparatus, display, and signal light

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