TW432656B - Method for producing encapsulation structure of semiconductor chip - Google Patents

Abstract

A method for producing an encapsulation structure of a semiconductor chip is characterized in that the whole process uses a flexible film carrier (instead of a conventional lead frame or substrate) to support a semiconductor chip. The method comprises forming a plurality of through holes on the flexible film carrier; laminating a metal layer on the lower surface of the flexible film carrier; etching the metal layer to form a plurality of bonding pads corresponding to the plurality of through holes; forming a metal cover layer on the plurality of bonding pads not covered by the flexible film carrier; fastening a semiconductor chip on the upper surface of the flexible film carrier; electrically connecting the chip bonding pad of the semiconductor chip to the plurality of bonding pads; and forming an encapsulation covering the upper surface of the flexible film carrier and the semiconductor chip.

Description

r F432656 V. Description of the invention (1) Field of the invention: The present invention relates to a semiconductor wafer package structure and a manufacturing method thereof. Prior art: The first figure is a semiconductor wafer package structure 10 according to a preferred embodiment of the "Resin-Packaged Component and Manufacturing Method" according to the Patent of the Republic of China No. 348306, which includes a semiconductor wafer 110 with an adhesive It is fixed on a resin insulating layer 122. The semiconductor wafer 110 has a plurality of wafers 110a for electrically connecting its internal circuits. The resin insulating layer 122 has a plurality of through holes 122a provided around the semiconductor wafer u0. A plurality of connection pads i40a are provided on the lower surface of the resin insulating layer 122. The plurality of wafer bonding pads 110a of the semiconductor wafer 110 are connected to the plurality of connection pads 140a by a plurality of connection lines 130. The semiconductor wafer no, the upper surface of the resin insulation layer 122, and the plurality of connection lines 130 are covered with a single gel 150. The package structure 10 can be mounted on a substrate, such as a printed circuit board, in a manner similar to other leadless devices. The Republic of China Patent No. 348306 also discloses the manufacturing method of the low pin number semiconductor chip package structure 10, which mainly uses a metal lead frame 170 to simultaneously manufacture many semiconductor chip package structures 10 (refer to the second figure) 3 The manufacturing method includes: (A) covering a photoresist layer on the surface of the lead frame 170, transferring a desired pattern, and developing so that the area of the lead frame 170 corresponding to the plurality of connection pads 140a is not exposed to the light Resistive layer coverage. (B) a metal (such as gold or platinum) is plated on the lead frame 170

Page 4 r 14 32 6 d 6 V. Description of the invention (2) The area covered by the photoresist layer 'and forming the plurality of connection pads 140a e (C) to remove the photoresist layer. (D) A resin insulating layer 122 is formed on the lead frame 170 and the plurality of connection pads 140a. (E) is formed on the resin insulating layer 122. A plurality of through-holes 122a correspond to the plurality of connection pads i4〇a 0 (F). The back surface of the semiconductor wafer 110 is fixed on the lead frame with an adhesive layer. The far semiconductor wafer 110 has a plurality of wafer glow pads H0a on the front side. ((;) Electrically connect the plurality of wafer pads ^ 〇a of the semiconductor wafer 110 to the corresponding plurality of connection pads 130. (10 forms a gel 120 covering the semiconductor wafer 110. Finally, A separation step for removing the lead frame 17 is performed. As shown in the second figure, the separation step generally uses an etchant to selectively dissolve the lead frame 17 ° without dissolving the plurality of connection pads i40a. The manufacturing method of the low-pin-count semiconductor wafer package structure 10 uses a metal lead frame 170 to support a semiconductor wafer throughout the entire process, and finally dissolves and removes it with an etchant. Therefore, the manufacturing process is complicated and expensive. Summary of the invention: The main purpose of the present invention is to provide a manufacturing method of a semiconductor wafer package structure, which mainly uses a flexible film carrier to support a semiconductor wafer, thereby simplifying the manufacturing process and saving costs. A method for manufacturing a semiconductor chip package structure according to the present invention, comprising the following steps: forming a plurality of through holes on a flexible carrier board; - the metal layer is laminated (Laminating) below the surface of the flexible carrier plate; etching the metal layer to form a plurality of connection pads, each connecting the front of the pad with a line

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Partially exposed in the corresponding through-holes; forming a metal covering layer on the surfaces of the plurality of connection pads which are not covered by the flexible carrier board; fixing a semiconductor wafer to a wafer setting area on the surface of the flexible carrier board; The semiconductor wafer pads of the semiconductor chip are electrically connected to the front surfaces of the plurality of connection pads; a piece of gel covers the upper surface of the flexible carrier board and the semiconductor wafer. 30 According to the method for manufacturing a semiconductor chip package structure according to the present invention, since a flexible carrier board is used to support a semiconductor chip throughout the entire process, it is not necessary to dissolve and remove the metal lead frame with an etchant. The process is simple, low cost and time-saving. 'Illustration: In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiment of the present invention in detail with the accompanying illustration, as follows. FIG. 1: A cross-sectional view of a semiconductor chip package structure according to a preferred embodiment of the “Resin Package Element and Manufacturing Method” according to the Republic of China Publication No. 3 48 3 0 6; A cross-sectional view of a separation step in a method of manufacturing a semiconductor wafer package structure; FIGS. 3 to 8 disclose a method of manufacturing a semiconductor wafer package structure according to the present invention; and FIG. 9: A preferred embodiment according to the present invention A cross-sectional view of a semiconductor wafer sealing structure. Figure number description:

Page 6 VMT · 14 32 6 5 6 V. Description of the invention (4) 10 Wafer 11 Silver glue 12 13 Wafer pad 14 Connection line 1 5 16 Outer foot 17 Inner foot 100 Semiconductor chip package structure 110 Wafer 110a Wafer fresh塾 112 120 Flexible carrier plate 120a Through hole 120b Wafer setting area 122 Resin insulation layer 122a Through hole 130 140 Metal layer 140a Connecting pad 144 150 Sealant 170 Metal lead frame Description of the invention: Wafer socket sealing gel silver glue connection wire metal The ninth figure of the cover layer reveals a half-packed structure 100 according to a preferred embodiment of the present invention, which includes a half of the guide wafer 110 fixed to an upper surface of a flexible carrier plate 120 with an adhesive layer such as 03 / seal 112. The semi-conductor: 1 10 has a plurality of wafer pads 1 10a for electrically connecting its internal electrical circuits. The flexible carrier board 120 has a plurality of through holes (through hQle) / μ provided on the periphery of the semiconductor wafer 110. A plurality of connection pads 140a are provided on the lower surface of the flexible carrier plate 20. The front surface of each connection pad i4〇a is partially exposed in the corresponding through hole 120a. The surface of each connection pad 14a that is not covered by the flexible carrier plate 120 has a metal covering layer 144. The plurality of wafer pads 1 10a of the semiconductor wafer 110 are connected to the front side of the plurality of connection pads 140a by a plurality of connection lines 130, wherein the metal covering layer is used to promote the connection between the connection lines 130 and the connection pads 140a. Of adhesion. The half

P.7 Description of the invention (5) The upper surface of the conductor chip 110, the flexible carrier plate 120, and the plurality of connection lines 130 are covered with a piece of colloid 150. The package structure 100 can be mounted on a substrate 'such as a printed circuit board in a manner similar to other leadless devices. The printed circuit board may be first screen-printed with a solder paste into a pattern corresponding to the connection pad 14a at the bottom of the package structure 100. The package structure is then placed on the printed circuit board and re-soldered. It can be understood that 'the connection pad 130 at the bottom of the package structure can also be printed with solder paste to form a solder ball' before being mounted on the substrate. The third to eighth figures are for explaining a method of manufacturing the semiconductor chip package structure 100 according to the present invention. The third aspect discloses a flexible carrier plate 120 »The flexible carrier plate 120 may be a resin sheet (r e s i n f i 1 m). Preferably, the flexible carrier plate 120 is made of polyimide, so that it has better characteristics of the carrier plate and fully meets various reliability tests. Referring to the fourth figure, a plurality of through holes 1220a are formed in the flexible carrier plate 120, which can use a conventional punching technique. The intermediate region surrounded by the plurality of through-holes 120a in the flexible carrier plate 120 is a wafer setting region 1 2 0 b. Referring to the fifth figure, the metal layer 140 (for example, a copper foil) is laminated on the flexible supporting plate 120 by a conventional method (for example, a hot pressing method). Please refer to the sixth figure. The plurality of connections 塾 1 2 0 a are formed in a photolithography and etching manner.

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^ Step (A) applies a photoresist layer on the surface of the metal layer, and Ϊ @ ί f ΐ pattern transfer '(C) uses # 刻 to remove the metal layer which is not protected by photoresist and forms a corresponding (D) removing the photoresist layer. Referring to the seventh figure, the metal covering layer 144 is formed on the plurality of connection pads 140a, and the surface not covered by the flexible carrier plate 120. The metal covering layer 144 can be formed on the plurality of connection pads by a conventional electroplating method. 14〇 &, for example, a layer of nickel (Ni) is plated first, and then a layer of gold (Au) is plated. Since the metal cover layer 134 is coated on a plurality of connection pads for electrically connecting to a semiconductor wafer, it must be selected with a material that has better bonding force and conductivity with a conventional connection wire (bonding wi re). . Please refer to the seventh figure. The back side of the wafer is fixed with an adhesive layer, such as silver glue 112, on the flexible carrier board 120. The through-holes 120 are surrounded by the wafer setting area 120b. . The plurality of bonding wires (bonding w 1 re) 1 3 0 are connected between the plurality of chip pads 11 0 a of the chip π and the plurality of connection pads 14 0 a by using a conventional bonding technology. Referring to FIG. 8, the sealing compound 150 is formed on the upper surface of the semiconductor wafer 110 and the flexible carrier plate 120 by a conventional plastic molding method (such as transfer molding). The semiconductor chip package structure 100 is obtained. According to the method for manufacturing a semiconductor wafer package structure according to the present invention, a flexible carrier board is used to support a semiconductor wafer during the entire process, so no additional separation step is required; on the contrary, since the Republic of China Patent No. 348306 mainly deals with Using a metal lead frame to simultaneously manufacture many halves

Γ 14 32 6 5 6 V. Description of the invention (7) The conductor chip package structure needs a separation step at the end, that is, the lead frame is selectively dissolved with an etchant. Therefore, the manufacturing method according to the present invention is simple, inexpensive, and time-saving. Although the present invention has been disclosed with the aforementioned preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

Claims (1)

M 32 6 5 6 VI. Patent application scope 1. A method for manufacturing a semiconductor chip package structure, comprising the following steps: providing a flexible carrier board with an upper surface and a lower surface, the surface of the flexible carrier board having a Wafer setting area; forming a plurality of through holes in the flexible carrier plate around the wafer setting area; laminating—a metal layer on the lower surface of the flexible carrier plate; etching the metal layer to form a plurality of connections Pads, the front side of each connection pad is partially exposed at the corresponding through hole; a metal cover is formed on the surface of the plurality of connection pads which is not covered by the flexible carrier plate; a semiconductor wafer is fixed on the flexible carrier A wafer setting area on the board surface, the semiconductor wafer has a plurality of wafer pads; electrically connecting the plurality of wafer pads of the semiconductor wafer to the front side of the plurality of connection pads; forming a colloid to cover the flexible carrier board On the top surface and on the semiconductor wafer. 2. The method for manufacturing a semiconductor chip package structure according to item 1 of the scope of patent application, which further includes printing solder paste on the back of the plurality of connection pads. The structure of the packaged cover lens is semi-conducted. Copper foil making item 1 is the first type of enclosing layer. Fan Lijin should apply for it in accordance with the law. Page 11 f ¢ 4 326 5 6_ VI. Patent application scope 4: The method for manufacturing a semiconductor wafer package structure according to item 1 of the patent application scope, wherein the metal covering layer includes a layer of nickel (Ni) covering the wafer holder And the surface of the plurality of connection pads not covered by the flexible carrier plate, and a layer of gold (Au) covering the surface of the nickel layer. 5. The method for manufacturing a semiconductor wafer package structure according to item 1 of the scope of the patent application, wherein the flexible carrier board is a resin sheet (resin film). 6. The method for manufacturing a semiconductor wafer package structure according to item 1 of the patent application, wherein the flexible carrier board is made of polyimide. P. 12 i