CN105161424A - 半导体叠层封装方法 - Google Patents
半导体叠层封装方法 Download PDFInfo
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Abstract
本发明提供一种半导体叠层封装方法,包括A:制作上封装体,B:制作封装有芯片的中层封装体,C:将上、中、下封装体叠层封装,步骤B包括:S101:提供金属板;S102:对金属板的正面半蚀刻形成第一开口;S103:将待装载的芯片加装在第一开口内并打线;S104:用塑封底填料将芯片固定和封装于金属板上形成塑封体;S105:对金属板的背面进行半蚀刻形成第二开口;S106:在塑封体的正面边缘或者背面边缘处形成焊球。本发明提供的封装方法,将金属板改进形成QFN框架,利用两侧L形金属片作为中层封装体的电极,从而实现堆叠的芯片在一个封装体中实现上下导通;节省封装空间,有利于实现多层塑封体堆叠时芯片封装的微型化,提高芯片封装的集成度。
Description
技术领域
本发明涉及一种半导体封装方法,尤其涉及一种半导体叠层封装方法。
背景技术
随着半导体制造技术以及立体封装技术的不断发展,电子器件和电子产品对多功能化和微型化的要求越来越高,同时要求芯片的封装尺寸不断减小。为了实现芯片封装的微型化,提高芯片封装的集成度,叠层芯片封装(stackeddiepackage)技术逐渐成为技术发展的主流。
叠层芯片封装技术,又称三维封装技术,具体是在同一个封装体内堆叠至少两个芯片的封装技术。叠层芯片封装技术能够实现半导体器件的大容量、多功能、小尺寸、低成本等技术需求,因此叠层芯片技术近年来得到了蓬勃发展。以使用叠层封装技术的存储器为例,相较于没有使用叠层技术的存储器,采用叠层封装技术的存储器能够拥有两倍以上的存储容量。此外,使用叠层封装技术更可以有效地利用芯片的面积,多应用于大存储空间的U盘、SD卡等方面。
叠层芯片封装技术能够通过多种技术手段来实现,例如打线工艺、硅通孔(throughsiliconvia,简称TSV)技术、或者塑封通孔(throughmoldingvia,简称TMV)技术。
例如,硅通孔(TSV)技术,就是在芯片上形成通孔,在通孔侧壁形成金属层再填充导电物质形成通孔效果实现上下连接。该工艺成本高,良品率低,直接在硅片上开口易对芯片造成损伤或是令整片晶元强度减低导致破片等问题,实现难度较大。
又如,塑封通孔(TMV)技术是指在塑封层开口,即塑封后使用激光等方法打通塑封层,填充导电物质,但该工艺在塑封层开口深度方面以及打通塑封层的孔边缘绝缘层方面不易控制。
其余的就是一些先预制可导通材质如凹型架构,进行打磨、打线等工艺用于连接。
上上述工艺在堆叠芯片的过程中,通过孔内填充介电质形成电极较难,特别是在多个塑封体连接形成整个封装体的过程中,通过传统工艺方法中间的塑封体不易实现上下封装体的导通,从而实现芯片在一个封装体上下导通的难度较大,且成本较高。
发明内容
在下文中给出关于本发明的简要概述,以便提供关于本发明的某些方面的基本理解。应当理解,这个概述并不是关于本发明的穷举性概述。它并不是意图确定本发明的关键或重要部分,也不是意图限定本发明的范围。其目的仅仅是以简化的形式给出某些概念,以此作为稍后论述的更详细描述的前序。
本发明的目的是提供一种半导体叠层封装方法,解决现有封装工艺(例如TSV、TMV等工艺)中形成电极较难,特别是在多个塑封体连接形成封装体的过程中,通过中间的塑封体不易实现上下封装体的导通,从而不易实现芯片在一个封装体上下导通的问题。
本发明提供了一种半导体叠层封装方法,包括:
A:制作上封装体,
B:制作封装有芯片的中层封装体,
C:将所述上封装体、所述中层封装体和所述下封装体叠层封装,
其中,步骤B包括:
S101:提供制备上述中层封装体的金属板;
S102:对所述金属板的正面半蚀刻形成第一开口,所述第一开口的深度大于待装载的芯片的厚度;
S103:将上述待装载的芯片加装在所述第一开口内并在所述第一开口内进行打线;
S104:用塑封底填料将芯片固定和封装于所述金属板上形成塑封填料层;
S105:对所述金属板的背面进行半蚀刻至塑封填料层,形成第二开口;
S106:在步骤S105处理后形成的塑封体的正面边缘或者背面边缘处形成焊球。
本发明提供的一种半导体叠层封装方法,对金属板进行改进形成四边扁平无引脚(QFN)框架,利用边缘的金属凸起作为中层封装体的电极,实现中层封装体与上封装体、下封装体的连通,从而实现堆叠的多个芯片在整个封装体中实现上下导通;利用QFN框架形式形成的中层封装体节省封装空间,有利于多层塑封体堆叠时实现芯片封装的微型化,提高芯片封装的集成度。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明制作封装有芯片的中层封装体的流程图;
图2-图6为本发明制作封装有芯片的中层封装体的过程示意图;
图7为本发明叠层封装结构示意图;
图8为本发明提供的步骤S105形成的芯片封装体用于表面贴装技术中的结构示意图。
附图标记:
1-金属板2-第一开口3-芯片
4-塑封填料层5-第二开口6-金属层
7-金属片8-下封装体9-上封装体
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。在本发明的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。应当注意,为了清楚的目的,附图和说明中省略了与本发明无关的、本领域普通技术人员已知的部件和处理的表示和描述。基于本发明中的实施例,本领域普通技术人员在没有付出创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明提供一种半导体叠层封装方法,包括:
A:制作上封装体,
B:制作封装有芯片的中层封装体,
C:将所述上封装体、所述中层封装体和所述下封装体叠层封装,
其中,如图1所示为制作封装有芯片的中层封装体的步骤B包括:
S101:提供制备上述中层封装体的金属板;
S102:对所述金属板的正面半蚀刻形成第一开口,所述第一开口的深度大于待装载的芯片的厚度;
S103:将上述待装载的芯片加装在所述第一开口内并在所述第一开口内进行打线;
S104:用塑封底填料将芯片固定和封装于所述金属板上形成塑封填料层;
S105:对所述金属板的背面进行半蚀刻至塑封填料层,形成第二开口;
S106:在步骤S105处理后形成的塑封体的正面边缘或者背面边缘处形成焊球。
上述步骤提供了一种制作封装有芯片的中层封装体的方法,如图2所示,实施步骤S101,提供制备上述中层封装体的金属板1。
可选的,为方便后续在金属板1上形成电极,金属板1材料为具有高导电和高熔点的金属材料,如铜。在本实施例中,铜板的厚度需大于待装载芯片的厚度但也不需要太高,节省材料的同时还得便于接下来在金属板上下表面形成开口以及加装芯片。
如图3-图4所示,接着实施S102-S103:对上述金属板的正面半蚀刻形成第一开口2,第一开口2的深度大于待装载的芯片的厚度;
将上述待装载的芯片3加装在上述第一开口2内并在第一开口2内进行打线,形成如图4所示的结构。
进一步地,步骤S102中对所述金属板的正面半蚀刻形成第一开口具体包括:
在金属板的正面贴膜,进行曝光显影;
对曝光显影的部位进行蚀刻形成第一开口,还在金属板1正面的两侧边缘形成凸起,如图3所示的两侧高出的部分;
去除上述曝光显影后剩余的膜,经过上述处理上述金属板呈凹形结构。
接着进行步骤S104,用塑封底填料将上述芯片3固定和封装于上述金属板上形成塑封填料层4,如图5所示。
可选的,步骤S104塑封填料层4的高度与上述凸起平齐,且芯片3以塑封底填料固定于上述金属板上并且包封在图5所示的塑封体内部。芯片的封装采用模塑底部填充技术,将芯片和所述金属凸点都包在塑封体内部。
上述用于模塑底部填充技术的胶为一种化学胶,主要成分可为环氧树脂,将芯片与上述凹形结构的金属板的空隙填满,并且包裹所述芯片,对填充胶进行加热固化,即可达到加固的目的,有保证了焊接工艺的电气安全性。
然后实施步骤S105,对上述金属板的背面进行半蚀刻至塑封填料层4,形成第二开口5,如图6所示。
可选的,步骤S105中对金属板的背面进行半蚀刻至所述塑封填料4层,形成第二开口具体包括:
在上述金属板的背面贴膜,进行曝光显影;
对曝光显影的部位进行蚀刻,形成第二开口,所述第二开口将上述金属板分隔成形成多个相互隔离的金属板;
去除上述曝光显影后剩余的膜。
可选的,上述第一开口2的面积大于所述第二开口5的面积,且所述第二开口5位于所述第一开口2对应的金属板的区域内。
可选的,上述多个相互隔离的金属板包括一金属层6以及对称设置在金属层6两侧的L型金属片7,所述金属片7包括上述凸起;芯片3连接在金属层6上。
最后,实施步骤S106,在经步骤S105处理后形成的塑封体的正面边缘或者背面边缘处形成焊球。本方案中,焊球即设置在L型金属片的正面或者背面,通过第一开口、第二开口形成的与金属层分隔的L型金属片即为中层封装体的电极。
经过上述步骤,封装有芯片的中层封装体制作完成,接着进行步骤C:,需要将上封装体和所述下封装体与中层封装体对接,再进行回流焊接以形成半导体叠层封装结构。如图6所示,本发明中上封装体9的基板底面为金属板,以作为上封装体的导电连接部位;所述下封装体8下表面用于连接的部位为金属凸点,例如铜柱,以作为下封装体的导电连接部位。
可选的,步骤S107中在图6所示的塑封体两侧的金属片的下表面形成焊球,上述中层封装体通过在金属片7下表面的形成焊球与下封装体8的导电连接部位对接,再进行回流焊接;上述中层封装体通过两侧的金属片的上表面与基板上设置有焊球的上封装体9对接,再进行回流焊接,最终形成如图7所示的半导体叠层封装结构。
又或者在步骤S107中在图6所示的塑封体两侧的金属片的上表面形成焊球,上述中层封装体通过金属片7与上表面设置有焊球的下封装体8对接,再进行回流焊接;上述中层封装体通过在金属片7的上表面形成的焊球与上封装体9导电连接部位对接,再进行回流焊接,最终形成如图7所示的半导体叠层封装结构。
图7为本发明叠层封装结构示意图,通过改进金属板,在金属板上蚀刻第一开口、第二开口形成QFN框架,利用两侧的金属片作为中层封装体的电极,实现上封装体9和下封装体8的电互连,叠层封装的多个芯片在整个封装体中实现上下导通。本发明中通过改进金属板利用QFN框架制备中层封装体,封装结构简单,节省封装空间,有利于多层塑封体堆叠时实现芯片封装的微型化,提高芯片封装的集成度。
同时,本方案提出的叠层封装为上、中、下三个封装体的连接,当然根据实际的需要,叠层封装的封装体个数可以根据实际情况决定,可以在上封装体与下封装体之间叠层封装更多的芯片封装层,增加叠层封装的结构,形成三层芯片封装或者更多层的芯片封装。
另外,上述封装方法中,经步骤S105处理后所得的塑封体可用于表面贴装(SMT)工艺。如图8所示,在步骤S105处理后所得封装有芯片的塑封体的背面刷导电胶,直接贴在基板或其他器件上,电学性能较高,且节省空间,成本较低。
在本发明上述各实施例中,实施例的序号和/或先后顺序仅仅便于描述,不代表实施例的优劣。对各个实施例的描述都各有侧重,某个实施例中没有详述的部分,可以参见其他实施例的相关描述。
本领域普通技术人员可以理解:实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成,前述的程序可以存储于一计算机可读取存储介质中,该程序在执行时,执行包括上述方法实施例的步骤;而前述的存储介质包括:只读存储器(Read-OnlyMemory,简称ROM)、随机存取存储器(RandomAccessMemory,简称RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
在本发明的装置和方法等实施例中,显然,各部件或各步骤是可以分解、组合和/或分解后重新组合的。这些分解和/或重新组合应视为本发明的等效方案。同时,在上面对本发明具体实施例的描述中,针对一种实施方式描述和/或示出的特征可以以相同或类似的方式在一个或更多个其它实施方式中使用,与其它实施方式中的特征相组合,或替代其它实施方式中的特征。
应该强调,术语“包括/包含”在本文使用时指特征、要素、步骤或组件的存在,但并不排除一个或更多个其它特征、要素、步骤或组件的存在或附加。
最后应说明的是:虽然以上已经详细说明了本发明及其优点,但是应当理解在不超出由所附的权利要求所限定的本发明的精神和范围的情况下可以进行各种改变、替代和变换。而且,本发明的范围不仅限于说明书所描述的过程、设备、手段、方法和步骤的具体实施例。本领域内的普通技术人员从本发明的公开内容将容易理解,根据本发明可以使用执行与在此所述的相应实施例基本相同的功能或者获得与其基本相同的结果的、现有和将来要被开发的过程、设备、手段、方法或者步骤。因此,所附的权利要求旨在在它们的范围内包括这样的过程、设备、手段、方法或者步骤。
Claims (10)
1.一种半导体叠层封装方法,包括:
A:制作上封装体,
B:制作封装有芯片的中层封装体,
C:将所述上封装体、所述中层封装体和所述下封装体叠层封装,
其特征在于,所述步骤B包括:
S101:提供制备上述中层封装体的金属板;
S102:对所述金属板的正面半蚀刻形成第一开口,所述第一开口的深度大于待装载的芯片的厚度;
S103:将上述待装载的芯片加装在所述第一开口内并在所述第一开口内进行打线;
S104:用塑封底填料将芯片固定和封装于所述金属板上形成塑封填料层;
S105:对所述金属板的背面进行半蚀刻至塑封填料层,形成第二开口;
S106:在步骤S105处理后形成的塑封体的正面边缘或者背面边缘处形成焊球。
2.根据权利要求1所述的方法,其特征在于,所述步骤C包括:上述中层封装体通过焊球与所述上封装体和所述下封装体的导电连接部位对接,再进行回流焊接形成半导体叠层结构。
3.根据权利要求1所述的方法,其特征在于,步骤S101所述金属板为铜板。
4.根据权利要求1所述的方法,其特征在于,步骤S102:对所述金属板的正面半蚀刻形成第一开口具体为:
在所述金属板的正面贴膜,进行曝光显影;
对曝光显影的部位进行蚀刻形成第一开口,还在所述金属板正面的两侧边缘形成凸起;
去除上述曝光显影后剩余的膜。
5.根据权利要求4所述的方法,其特征在于,步骤S104所述塑封体中塑封填料层的高度与所述凸起平齐,所述芯片以塑封底填料固定于所述金属板上并且包封在所述塑封体内部。
6.根据权利要求4所述的方法,其特征在于,步骤S105:对所述金属板的背面进行半蚀刻至所述塑封填料层,形成第二开口,具体为:
在所述金属板的背面贴膜,进行曝光显影;
对曝光显影的部位进行蚀刻,形成第二开口,所述第二开口将上述金属板分隔成形成多个相互隔离的金属板;
去除上述曝光显影后剩余的膜。
7.根据权利要求6所述的方法,其特征在于,所述第一开口的面积大于所述第二开口的面积,且所述第二开口位于所述第一开口对应的金属板的区域内。
8.根据权利要求7所述的方法,其特征在于,所述多个相互隔离的金属板包括一金属层以及对称设置在所述金属层两侧的L型金属片,所述芯片连接在所述金属层上;
所述金属片包括上述凸起。
9.根据权利要求8所述的方法,步骤S107中所述焊球设置在所述L型金属片的正面或者背面。
10.根据权利要求1-9任一所述的方法,其特征在于,在所述上封装体与所述下封装体之间设置一个或多个中层封装体。
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