JP2009152503A - 半導体装置及びその製造方法 - Google Patents
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06551—Conductive connections on the side of the device
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
【解決手段】導電性の材料からなる半導体チップ30と、半導体チップ30の周辺領域に設けられ、半導体チップ30と同じ材料からなる接続端子32と、半導体チップ30と接続端子32とを電気的に絶縁する絶縁部材24と、半導体チップと接続端子とを電気的に接続する第1接続部材20と、を具備することを特徴とする半導体装置。接続端子32の製造工程を簡略化することにより、半導体装置の製造工程を簡略化することができる。
【選択図】図3
Description
12 ダイシングライン
14 チップ領域
16 ダイシング領域
20 再配線
21 絶縁層
22 溝部
24 絶縁性樹脂
30 半導体チップ
32 接続端子
40 金属層
41 Ti層
42 Au層
50 中継基板
52 封止樹脂
54 半田ボール
56 ボンディングワイヤ
60 金属ペースト
62 接着剤
64 側面配線
100 半導体装置
110 積層型半導体装置
Claims (10)
- 導電性の材料からなる半導体チップと、
前記半導体チップの周辺領域に設けられ、前記半導体チップと同じ材料からなる接続端子と、
前記半導体チップと前記接続端子とを電気的に絶縁する絶縁部材と、
前記半導体チップと前記接続端子とを電気的に接続する第1接続部材と、
を具備することを特徴とする半導体装置。 - 前記絶縁部材は、前記半導体チップと前記接続端子とが直接接触しないように、前記半導体チップ及び前記接続端子の側面を覆って設けられていることを特徴とする請求項1に記載の半導体装置。
- 前記接続端子は、前記半導体チップの少なくとも1以上の辺に沿って複数配列して設けられ、
前記絶縁部材は、前記複数の接続端子同士が直接接触しないように、前記複数の接続端子のそれぞれの側面を覆って設けられていることを特徴とする請求項1または2に記載の半導体装置。 - 前記接続端子の表面は金属層で覆われており、
前記接続部材は、前記金属層を介して前記接続端子と電気的に接続されていることを特徴とする請求項1から3のうちいずれか1項に記載の半導体装置。 - 前記半導体チップ及び前記接続端子は、導電性のシリコンからなることを特徴とする請求項1から4のうちいずれか1項に記載の半導体装置。
- 前記接続部材は、再配線層またはボンディングワイヤであることを特徴とする請求項1から5のうちいずれか1項に記載の半導体装置。
- 請求項1から6のうちいずれか1項に記載の半導体装置が複数積層され、
複数積層された前記半導体装置のうち、上下に隣接する2つの半導体装置は、上側の前記半導体装置における前記接続端子の下面と、下側の前記半導体装置における前記接続端子の上面とが、第2接続部材により電気的に接続されていることを特徴とする積層型の半導体装置。 - 請求項1から6のうちいずれか1項に記載の半導体装置が複数積層され、
複数積層された前記半導体装置のうち、上下に隣接する2つの半導体装置は、上側の前記半導体装置における前記接続端子の側面と、下側の前記半導体装置における前記接続端子の側面とが、第3接続部材により電気的に接続されていることを特徴とする積層型の半導体装置。 - 切断後に半導体チップとなる第1領域と、前記第1領域の周辺領域であって切断後に前記半導体チップとならない第2領域と、を有する導電性の材料からなる半導体ウェハに対し、前記第2領域の一部を少なくとも1以上の接続端子に形成する工程と、
前記第1領域と前記接続端子とを電気的に絶縁する工程と、
前記第1領域と前記接続端子とを電気的に接続する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 前記第2領域の一部を少なくとも1以上の接続端子に形成する工程は、前記半導体ウェハにおける前記第1領域と前記第2領域との間に、前記第1領域と前記第2領域とが直接接触しないように溝部を形成する工程を含み、
前記第1領域と前記接続端子とを電気的に絶縁する工程は、前記溝部に絶縁部材を充填し、前記半導体チップ及び前記接続端子の側面を前記絶縁部材で覆う工程を含む
ことを特徴とする請求項9に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007331183A JP5358089B2 (ja) | 2007-12-21 | 2007-12-21 | 半導体装置 |
US12/341,863 US8097961B2 (en) | 2007-12-21 | 2008-12-22 | Semiconductor device having a simplified stack and method for manufacturing thereof |
US13/323,370 US8361857B2 (en) | 2007-12-21 | 2011-12-12 | Semiconductor device having a simplified stack and method for manufacturing thereof |
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JP2007331183A JP5358089B2 (ja) | 2007-12-21 | 2007-12-21 | 半導体装置 |
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JP2009152503A true JP2009152503A (ja) | 2009-07-09 |
JP5358089B2 JP5358089B2 (ja) | 2013-12-04 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012513128A (ja) * | 2010-04-30 | 2012-06-07 | ウエイブニクス インク. | 端子一体型金属ベースパッケージモジュールおよび金属ベースパッケージモジュールのための端子一体型パッケージ方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US8513119B2 (en) | 2008-12-10 | 2013-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bump structure having tapered sidewalls for stacked dies |
US20100171197A1 (en) | 2009-01-05 | 2010-07-08 | Hung-Pin Chang | Isolation Structure for Stacked Dies |
US8791549B2 (en) | 2009-09-22 | 2014-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside interconnect structure connected to TSVs |
US8304917B2 (en) * | 2009-12-03 | 2012-11-06 | Powertech Technology Inc. | Multi-chip stacked package and its mother chip to save interposer |
US8466059B2 (en) | 2010-03-30 | 2013-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer interconnect structure for stacked dies |
US8963312B2 (en) * | 2010-05-11 | 2015-02-24 | Xintec, Inc. | Stacked chip package and method for forming the same |
US8900994B2 (en) | 2011-06-09 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for producing a protective structure |
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JP2000012589A (ja) * | 1998-06-18 | 2000-01-14 | Toyota Motor Corp | バンプ電極形成方法 |
JP2000114516A (ja) * | 1998-10-02 | 2000-04-21 | Toshiba Corp | 半導体装置およびその製造方法 |
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JP2012513128A (ja) * | 2010-04-30 | 2012-06-07 | ウエイブニクス インク. | 端子一体型金属ベースパッケージモジュールおよび金属ベースパッケージモジュールのための端子一体型パッケージ方法 |
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US20090321958A1 (en) | 2009-12-31 |
JP5358089B2 (ja) | 2013-12-04 |
US8097961B2 (en) | 2012-01-17 |
US8361857B2 (en) | 2013-01-29 |
US20120083096A1 (en) | 2012-04-05 |
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