TW511399B - Semiconductor device and its manufacture method - Google Patents
Semiconductor device and its manufacture method Download PDFInfo
- Publication number
- TW511399B TW511399B TW90103576A TW90103576A TW511399B TW 511399 B TW511399 B TW 511399B TW 90103576 A TW90103576 A TW 90103576A TW 90103576 A TW90103576 A TW 90103576A TW 511399 B TW511399 B TW 511399B
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- Prior art keywords
- semiconductor device
- conductive
- semiconductor element
- semiconductor
- electrode
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Classifications
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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Description
511399 A7 經濟部智慧时產局員工消費合作社印製 五、發明說明(1 ) 【技術領域】 本發明係相關半導體裝置及其製造方法,特別係關於 可將源自半導體元件的熱量’良好釋放出的半導體裝置及 其製造方法。【習知技術】 按近年來1C封裝隨在行動機器或小型❿高密度安 裝機器採用的演進,習知IC封裝及其安裝概念已產生大 幅度的變化。較詳細内容,如電子材料(1998 I 9月刊第22頁〜)中相關「csp &術與其封裝材料、裝置」特刊中 所載述。 第10圖表示採用柔性板50作為中介基板(interp〇ser board) ’在該柔性板5〇上,利用接著劑貼合上銅箔圖案η 後更進一步固接上Ic晶片52。然後以形成於該工c晶 片52周圍上的黏接用墊(b〇nding pad)53,作為導電圖案 51。此外,透過與該黏接用墊53形成一體的配線5ib, 而形成焊錫球連接用墊54。 在該焊錫球連接用墊54内側,設置將柔性板開口的 開口邛5 6,並透過該開口部5 6而形成焊錫球5 5。然後將 柔眭板50置於基板上,整體使用絕緣性樹脂58予以密封。 【發明欲解決課題】 惟,設置於1C晶片52背面上的柔性板5〇係屬非常 Φ貝的’所以有產生成本上昇的問題、封裝體厚度增厚的 問題、重量增加的問題。 此外’因為支撐基板係由金屬以外材料所形成,將產 木紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 312146 (請先閱讀背面之注意事項再填寫本頁) pi裝----- 訂---------線· 511399 A7 五、發明說明(2 ) C請先閱讀背面之注意事項再填寫本頁} 生由1C晶片背面傳達至封裝體背面的熱阻抗將變大的問 題。該支撐基板為柔性板'陶:是基板、或印刷電路板。此 外,由熱導性佳之材料所形成的熱導通路,乃為金屬細綠 57、導電圖案51、及焊錫球55,屬驅動時無法充分散熱 的構造。所以,將造成驅動肖IC晶片的溫度上昇,且驅 動電流無法充分流通的問題發生。 【課題解決之手段】 本發明為有馨於上述諸項課題’第1項解決手段,係 具借有對應半導體元件之黏接電極而設置的黏接墊、設置 於該半導體元件配置區域上的散熱用電極、以面向下黏接 法電性連接於該黏接塾的該半導體元件、至少設置於該半 導體元件下面的底填充材料、裸露出該黏接塾背面與該底 填充材料背面且-體化的將該半導體元件密封的絕緣性樹
脂。 T 第2項解決手段,係具備有對應半導體元件之黏接電 極而設置的黏接墊、設置於該半導體元件配置區域上的散 熱用電極、以面向下連接、兵雷卜士、志 經濟部4°慧財'1局員工消費合作社印製 Γ逆按性連接於該黏接墊的該半導 ,元件、至少設置於該半導體元件下面並裸露出該黏接塾 背面而一體化密封的底填充材料。 第3項解決手#,乃該底士真充材肖係頂吹半導體元件 側面,而填充於鄰接該黏接塾間的分離溝、該黏接塾與該 散熱用電極間的分離溝。 第4項解決手段,係具備有對應半導體元件之黏接電 極而設置的黏接塾、設置於與該黏接塾一體之配線上 A7 五、發明說明(3 接私極包圍該外接電極的散熱用電極、以面向下之方式 ^ 1±連接於該黏接墊的該半導體元件、至少設置於該 70下面的底填充材料 '裸露出該外接電極背面與該底 、 料者面且一體化的將該半導體元件密封的絕緣性樹 月旨。 第5項解決手段,係具備有對應半導體元件之黏接電 柽而5又置的黏接墊、設置於與該黏接墊一體之配線上的外 接電極、包圍該外接電極的散熱用電極、以面向下連接法 電性連接於該黏接塾的該半導體元件、至少設置於該半導 體元件下面的底填充材料。 第6項解決手段,乃該底填充材料係頂吹半導體元件 側:’而填充於鄰接該黏接墊間的分離溝、鄰接該配線間 的刀離溝、該外接電極與該散熱用電極間的分離溝。 ^ ^解決手’又’乃連接該半導體元件與該黏接墊之 、接構件,係為焊接材料、導電糊劑、或非等 樹脂。 守宅丨王 第8項解決手段’乃該黏接墊的側面,係形成彎 造。 # 項解決手段,乃該黏接塾、與該黏接塾-體的配 與該配線-體的外接電極側面,係形成彎曲構造。 第項解決手段,係準備導電落、施行半蝕刻處理, 俾使導電圖案形成凸狀; 以面向下連接法,將該導電圖案與半導體元件予以連 接, 張尺度適❼_家標準(CNS)A以格⑵Q X 297公髮) 312146 1 丁 經 濟 部 智 .¾ 財 產 局 消 費 合 作 社 印 製 線 3 B7 五、發明說明(4 使底填充材料$ 間; ^ ^入於該半導體元件與該導電箔之 二電予=置絕緣性樹脂,俾將該半㈣件、 裸路出該底填充材料背面,並去 將導電圖案分離。 命兒 >白月面,俾 第1 1項解決手段,係準備導 俾使導電圖案形成凸狀; ^了^刻處理, 接;以面向下連接法’將該導電圖案與半導體元件予以連 間;使底填充材料至少滲入於該半導體元件與該導電落之 八雜裸露出該底填充材料背面,並去除該導電ϋ背面,俾 勿離而供作為導電圖案。 第12項解決手段,乃在將該導電圖案分 壓模法予以分離。 交才i用 第13項解決手段,乃在該導電落上,乃構成單元之 導電圖案係呈矩陣狀’並分別在各單元上設置該半導體元 第14項解決手段,乃在將該導電圖案分離後,利用 切割’將該單元與該單元之間予以分離。 藉由提供本半導體裝置,便可將半導體元件的熱量, 傳導於散熱用電極。此外,含該散熱用電極的導電圖案, 因為毋需採用支撐基板,所以成本將降低,且半導體芽置 本紙張尺度剌巾閱家鮮(CNS)A4祕⑵G X 297公t ) -- A7 五、發明說明(5 ) 的厚度亦可變薄。 【發明實施態樣】 首先,針對本發明之半導體裝置,請參閱第1圖對比 誶細說明。其中1 1A圖所示係半導體裝置的平面示意 圖。第1B圖表示A-A線剖面示意圖。 第1圖表示在絕緣性樹脂10中,埋入下列構成要件。 即’埋入黏接髮* 11、與該黏接螯體的配線11B、 與該配'線ΠΒ形成一體化且設置於該配線UB另一端上 的外接電極11C。更進-步埋入設置於圍繞該導電圖案11A 至11C之-區域的散熱用電極11D、與設置於 r上的半導體元件12。另外,半導體元…利用電 占、充材枓AF’而與該散熱用電極UD固接第1A圖 中虛線所示部分。 再者’半導體元件12之黏接電極13,與黏接墊nA, 因為半導體元件12係 囬朝下之方式女裝,所以透過焊 等焊接材料SD、Ag糊劑等導+細爲 b w寻V包鞠劑、非等向性導電性 樹月曰,而電性連接。 經濟部智慧財產局員工消費合作社印製 其次’該導電圖案11A i 11D #]面,經等向性蚀刻 =,此處因施行濕式姓刻。在此因為經濕 effect)。 構…生銷釘效果(an-r 本結構係由半導體元件12、%奴戈 11〇 複數導電圖案11A至 UC、散熱用電極11D、底壌右从丄, # „ -異充材料AF、埋藏該等的絕緣 性樹脂10等4項材料所構成。姓^〆 ^ 特別係在半導體元件12的 枣砥iR國國家標準(CNS)A4規格⑵ 312146 511399 絕緣性樹脂10密封, ^ 列用 Ί η、☆试 > ,… 形成封裝體。所以’由絕緣性樹I閱 ° t# 背 面 訂 經 濟 部 -智 U 1 “財 ,產 -局 消 費 .合 作 社 -印 η A7
BY 五、發明說明(6 配置區域中,在導 分離溝14中,形成至11D上、及該等之間的 填充材料上羞材:斗AF。特別係在經填充底 /冓14的背面,呈裸露狀態下,利用 ^ U) ^ ^ ^ q π姐 厂/丨从^出、吧緣性樹 月日10、底填充材料AF,^ ^ 而支撐該黏接塾11Α…、半導 元件1 2 - 干命篮 底填充材料AF择i -r$
。 τ、由可滲入狹窄間隙中的絕緣材料所I 形成,攻好採用如第4国— 5· 側面的材料。另外,介 孓裝 ’、w在半導體元件1 2背面形成薄薄I頁 、&填充材料AF,並利用絕緣性樹脂10密封。
'另外,由後述製造方法(請參閱第7圖)中得知,若 半V體70件1 2背面亦形成底填充材料AF的話,便可來 成省略絕緣性樹脂10的半導體裝置。 V 絕緣性樹脂1〇係可採用如環氧樹脂等熱硬化性樹 脂、聚醯胺樹脂、聚苯撐亞硫酸醋等熱可塑性樹腊。另外, =性樹脂,只要是為採用模具而可凝固的樹脂、可利用 次潰、塗敷而被覆的樹脂的話,所有的樹脂均可採用。 此外’導電圖案11Α至UD可採用以Cu為主材料的 導電箱、或Fel合金、A1_Cu疊層物、a1_Cu_ai疊層物 等。當然亦可採用其他導電材料,特別係以可蝕刻的導電 材料、以雷射蒸發的導電材料為更佳。此外,若考慮半2 d f生黾鍍成形性、熱應力等因素的話,最好採用以札延 所形成的Cu為主材料的導電材料。 在本發明中之第1 B圖中,絕緣性樹脂1 〇與底填充材 本紙張尺度適用中國國家標準(CNS)A4規烙(210 x 297公复) ° )12146 A7 五、發明說明(7 ) 料AF亦填充於該分離溝15巾,而在第7圖巾,因為底 填充㈣AF填充於分離溝15巾,所以便具有防止導電 圖案脫洛的特徵。另外,钱刻處理係採用乾式敍刻法或濕 式飿刻法,而施行等向性姓刻處理,而使黏接塾m··側 面、配線11B ···側面、外接電極uc…側面 極iid側面形成彎曲槿! ^ ^ ^ ^ 风穹曲構仏,而可產生錨釘效果。結果, 便可產生導電圖幸11Δ $ 电口茶11Α至11D不致由絕緣性樹脂ι〇上脫 落的構造。 同時^电圖案11Α至11D背面係由絕緣性樹脂J 〇 的背面裸路出。在第1B圖中,雖形成絕緣被覆膜W,但 亦可省略此絕緣被霜瞪 覆膜16,而將散熱用電極11D背面、 與安裝基板上的電極書技 一 蚀置接固接。精由此種構造,由半導體 元件12所產生的執旦 的熱里’便可散熱於安裝基板上的電極, 而可達防止半導體元件12溫度上升,及增加該半導體元 件12之驅動電流或驅動頻率之功效。此外,亦可將外接 電極llcf半導體元件Π電性連接。
半V肚裝置,因為利用係以屬導電圖案11A至11D 之遂、封樹腊的絕緣性爲+匕 樹月曰10支撐,所以不需要支撐基板。 此種結構屬本發明特微一 试之一。如習知技術段中所說明般, 習知半導體裝置的導雷敗 包路,乃利用支撐基板(如柔性板、 印刷電路板、或陶奢其k 充暴板)支撐,或利用導線框支撐,而 本發明則屬不需採用亦 乃J的構造。所以,本電路裝置便以
最少必要元件構成,因A u马不需要支撐基板,不僅可達薄型、 輕量化’同時因為亦可 __ _ 抑制材料費而具廉價之功效者。 本紙張尺度適网φ國國家標準^----- 7
請 先 閱 讀 背 之 注 意 事 項J Μ 填 寫裝 本衣 頁I 訂 線 經濟部智慧財產局員工消費合作社印製 312146 丄丄 丄丄 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明(8 ) 在封裝體的背面上將裸露出導 、 外分四命電圖案11A至11D。若 在此區域中,被覆如焊錫箄煜 炫金 枓的話,則因散熱用電 極11D面積較廣,所以焊 坪接材枓便沾潤較厚。故,當在 固接於安裝基板上時,外接雷錳nr 田社 +、 卜接電極UC背面的焊接材料並 未沾潤到安裝基板上的電福 現象。 w $極所以假設將產生連接不良的 為解決此種不良現象,便在 长平導體裝置15背面形成 絕緣被覆膜16。第1Α圖中斤魂夕 Λ α τ虛線之〇部分,係表露出於 緣被覆膜16外的外接雷榀"r 「强包極lie…、散熱用電極11D。即, 因為該〇記號以外部分覆蓋 絶緣破覆獏16,且該〇記號 部为的大小實質上相同,所 所乂在此邛份所形成的焊錫材料 厚度便實質上相同。此情开j,. ^ 在4錫印刷後、回流後亦均 將相同。另外,可認為如 8 Au ' Ag-Pd等導電糊劑亦 同。藉由此種結構便可抑制恭 仰制毛性連接不良。此外,散熱用 電極11D之露出部17的尺寸,在考慮半導體元件的散熱 性因素下,可形成較大於外接電極lie t露出尺寸。因 為外接電極11C全部為竇_暂μ 巧貫質上相同尺寸,故亦可將外接 電極11C…跨過全區裰霞φ 露出’且依與散熱用電極11D背面 之其中一部份實質上相同的尺+ 、雨 N的尺寸,稞露出於絕緣被覆膜 116 外。 再者,藉由設置絕緣祜 I破覆獏16,便可將安裝基板上 所設置的配線,延伸於太主道祕# 本丰導體裝置背面。一般設於安裝 基板上的配線’係採迁迪兮坐彳首 疋避該丰導體裝置的固接區域而配 置,但藉由該絕緣被覆膜】6沾 [_2联16的形成,便可不需迂迴配置。 本紙張尺度適用中國國家標準:CNS)A4規格 -------------裝--------訂i m ϋ 11 i ϋ— I (請先閱讀背面之注意事項再填寫本頁) B 312146 A7 五、發明說明(9 ) 樹脂10與底填充材料af均較導電圖 成在安裝基板的配線與導電圖案之間形 說明半導體裝置之製造方法的第2實施態樣 本製造方法係第i圖之半導體裝置15的製造方法, 6圖所示係對應第1A圖A-A線剖面示意圖。 首先,準傷如第2圖所示的導電f|2〇。最好厚度為 至⑽# m左右’此處採用7〇 #瓜的軋延銅箔。接著, :該導電箱20表面上’形她刻罩幕的導電被覆臈η、 …且。另外,該圖案係與第1A圖之黏接墊ιια·.、配 UB...、外接電極UC...、散熱用電極11D為同—圖 案。當取代導電被覆膜21 @改用光阻時,在光阻下層, 至少在對應黏接塾的部分位置處,形成Au、Ag、pd 等“被覆膜。此乃為防止Cu氧化’與可進行焊錫材 料的連接(以上請參閱第2圖所示)。 …接者’透過該導電被覆膜21或光阻,對導電箔20施 订半姓刻處理。钱刻的深度,只要淺於導電帛2〇的厚度 便可。另外,敍刻深度越淺的話,越可能形成細微圖案二 然後,利用半姓刻處理,而使導電圖案UA至ud 在導電20表面上表現出凸狀。另外,導電猪2〇,係如 前述、,採用經軋延而形成% Cu冑主材料之Cu箱。但, 亦可為由A1所形成的導電箱、由合金所形成的導 電猪、Cu-Al疊層體、A1_Cu-A1 φ層體。特別係Ai_Cu_Ai ,疊層體,可防止因熱膨脹係數差而造成撬曲現象的發生〇 乱紙張尺度適用中國國家標連(CNS)A4規格(210 x 297公釐) 9 312146
I 頁 訂 線 經 濟 部 智 慧 財 產 局 消 費 合 社 印 製 A7 五、發明說明(10 =向::,用軋延鋼落。此乃因為軋延鋼謂係x軸、γ 向的、”成長大於z軸方向 特別係當配線11B鲈具性 芎曲丨生較強所致。 ,^ 較長時,附加於此配線的應力便將_ 大,藉由採用此軋力便將〜 上請參閱第3圖)。 .應以應力的耐性(以 將黏接電極13與黏接塾UA 譬如利用谭錫材科SD而固接著。纟面對面配且方式, 設置有焊锡球的半導體元件12,在黏接墊 卞… 烊錫材料所形成的糊劑。此糊劑在燒結 =暫Z ’可將半導體元件12暫時黏接。然後,即在此 黏:狀態下…火爐中,將焊錫材㈣融= 半導體疋件12與黏接墊形成電性連接。 填充利用谭錫材料構成一定間隙的部分,形成底 :=二。此底填充㈣^屬較容易渗入半導體元 〃 ¥电圖案間之間隙的材料,且利用控 =成至半導體元件】2側面、或形成至半導^件^ 此底填充材料AF係在考慮與絕緣性樹腊1〇之黏接 性、及與導電圖案之黏接性下,而選擇者。 所以’底填充材料AF係設置於散熱用電極ud與外 接電極UC的分離溝14中、由黏接塾11A至外接電極11C 所幵/成導電圖案間的分離溝14中、以及該等之上。所以 不而使用上述支撐基板便可安裝半導體元件,且半導體元 件/2的尚度,可依面向下之黏接法安裝部分的低配置。 ^封錢外觀的厚度便可㈣(以上請參閱第4圖) I氏張尺度適用#國國家標準(CNS)A4規格(21Q X 297公髮)~-------- ί0 312146 訂 線 濟 部 智 財 產 局 消 費 ,合 作 社 ,印 製 A7 A7 經 濟 部 智 慧 財 產 局 消 費 合 社 印 製 1] 五、發明說明(η 然後’形成絕緣性樹脂10,俾覆蓋經半蝕刻處理而 所形成的導電圖案^至nD••…半導體^件12、及金 屬、’、田線1 4絕緣性樹脂可採用熱可塑性、熱硬化性中任 一者均可 ° 、再者可利用移轉模造、射出模造、浸潰或塗敷等方 式進订製以。樹脂材料可採用環氧樹脂等熱硬化性樹脂進 仃壓核^,或採用液晶高分子、$苯標亞硫酸醋等執可塑 性樹脂進行射出模造。 在本貝施態樣中,絕緣性樹脂的厚度,係 屬細線14頂部起往上覆笔约]ΛΛ ^ 巧你上復盍約l〇〇wm。該厚度在考量 體裝置強度下,可厚亦可薄。 在注入樹月旨的處理程序中,因為導電圖案11A至11D :與板狀導電箱2〇形成-體’所以只要導電H 20不產生 偏^該等導電圖案UA至11D的位置絕對不產生偏移。 1上,在絕緣性樹脂1G、底填充 a 成導電圖案11A至11D的^杜 入形 詩幻a 1D的凸件、以及半導體元件12,並 使較凸件更下方的導電箔2〇, 卫 第5圖所示)。 由“稞露出(以上請參閱 接著,去除裸露出於該絕緣_冑Μ Μ 2〇,而將導電圖案丨丨八至丨 泊 王Αΐυ分別隔開分離。 此項分離處理可採用各種 品土队. 法’亦採用利用蝕刻背面 一心 木用研磨或研削等方法,玄叮 一者合併使用。譬如若切削命 /、" 降7性 裸路出絕緣性樹脂10為止 情況時,將造成導電箔20的切削居4、 馮止 ------ 屑或外側較薄的毛邊肤
本紙張尺f適用ϋ國家標準(CNS)A4規格γ21〇 X 312146 丄 丄 經 濟 部 智 慧 財 產 局 消 費 合 社 印 製 A7 B7 五、發明說明(U ) 金屬,造成摻進絕緣性樹脂1 〇或底填充材料AF中的問 題產生。故,若利用姓刻處理而分離黏接塾〗丨…的話, 則位.於導電圖案11A至11D間的絕緣性樹脂1〇表面、或 底填充材料AF表面上,將不致產生導電箔2〇摻進金屬 的情況,藉此防止細微間隔之導電圖案UA至nD間產 生短路不良現象。 當複數個半導體裝置15單位形成一體時,在施行分 離處理後,追加施行切割處理(dicing)。 此處雖採用切割裝置施行個別分離處理,但亦可採用 巧克力壓製機、或沖床、剪床等。 此處,在將經分離並裸露於背面的導電圖案llA至 上,形成絕緣被覆膜16,並對絕緣被覆膜16進行圖案化 f理,俾使如帛1A目|線圓圈所示部分裸冑出。然後對 箭頭所示部分施行切割處理,而形成半導體裝置。 另外焊錫21亦可形成於施行切割前、或在經切割 處理後才形成。 藉由上述製造方法,便可將導電圖案、半導體元件, 埋入絕緣性樹脂内,而獲得輕薄短小的封裝體。 第7圖表示經改良第1圖後之半導體裝置,屬省略絕 緣性樹脂10者。在第4圖所示的處理程序中,使截至半 導體元件12 f面為止均形成底填充材料AF之方式,施 行塗敷並固化後,便省略絕緣性樹脂1()的形成,屬經切 割者°另外,在第7圖中,亦可裸露出半導體元件12背 I面。因為平面示意圖與圖所示相同,在此便省略。 本纸張尺度適用中國國家標準(CNS)八4現格(21〇 八髮、----— - “ 12 312146 (請先閱讀背面之注意事項再填寫本頁) 511399 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(I3 不致’ώ動/有的實把例中,均形成有供使焊錫材料SD ==c。譬如以焊錫為例,如第ib圖所 不般至乂在導電圖案11AS UD t其中 防止流_ DM,而阻止焊錫 开7成 i匕叙卜日级、u τ日 所明防止流動膜係 '知錫沾潤性較差的膜’譬如形成於高分子膜、咬妒成 於沁表面上的氧化膜等。 、或形成 、該防止流動膜的平面形狀,請參閱帛8圖所示。另外, 為圖式繪示的便利性,省略散熱用電極。 在第8圖中雖形成八至E五個圖案,但選擇其中一 個A所不圖案係在黏接塾1 i a與配線㈣邊界上,來 成防止流動膜DM’且在黏接塾nA實質: t連接構件。另外,亦可包含配線UB全區域、或2 %極lie,均形成防止流動膜dm〇b係在黏接墊上 防止流動膜DM,為去除設置電性連接構件的部分者二C 係^加型態B的形成區域,包含配線UB全區域、或外 接私極11 C上,均形成防止流動膜DM。D係型態c的開 口部’由矩形轉變成圓形者β E係在黏接 的防止流動膜DM。另外,黏接塾11A雖圖式矩形成^ 可為0形者。此防止流㈣應係'防止焊錫等焊接材料、 糊劑等導電糊劑、導電性樹月旨等的流動者,屬對該等 電性連接構件具沾潤性較差劣者。譬如當焊錫設置於型態 寺於¥錫溶融時’便利用防止流動膜dm堰擋,择由 張力而开> 成元美半球狀。另外,在附著該焊錫之半導 體元件的黏接電極13周圍上’因為形成鈍化 13 312146 (請先閱讀背面之注意事項,填寫本頁) .丨裝 · 線· 511399 經濟部智慧財產局員工消費合作社印製 "氏張尺度適用中國國家“(CNS)A4^^21〇x 297公爱 14 A7 五、發明說明(14 ) (Passivation),故僅黏接電極沾濕。藉此透過烊錫將半導 體元件與黏接墊予以連接的話,便可將,圓柱狀維持一定 高度。此外,因為利用焊錫量,可調整此高度,所以可在 半導體元件與導電圖案間,設置一定間隙,而可使洗淨液 滲入此間隙中。同時亦可使如底填充材料AF般之黏性較 低的黏接劑滲入。此外,藉由除連接區域外,全部均被覆 防止流動臈DM,而可達大幅提昇與絕緣性樹脂丨〇之黏 接性的功效。 其次,就上述製造方法產生的效果詳細說明於後。 首先’第1 ’係因為導電圖案係經半蝕刻處理,而與 導電箔形成一體而支撐著,所以毋須再採用習知支撐用美 板。 & 第2 ’係因為導電箔上形成有經半蚀刻處理而形成凸 件的黏接墊,所以黏接墊可細微化。因此,可將寬度、間 隔變窄’而形成平面尺寸更小的封裝體。 第3’係因為由導電圖案、半導體元件、黏接構件、 及密封材料所構成,可呈最少必要構成元件,無須浪費材 料’可大幅抑制成本的薄形半導體裝置。 第4 ’係黏接墊係經半蝕刻處理方式形成凸件,而個 別分離係在密封後再實施,所以不需使用撐棒(tie bar)或 懸吊線。故’對撐棒(懸吊線)的形成處理、撐棒(懸吊線) 的切斷處理,在本發明中完全不需要。 第5 ’因為係在將形成凸件的導電圖案埋入絕緣性樹 腊後’再由絕緣性樹脂背面去除導電箔,而將導電圖案分 312146 -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 511399 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(15 離,所以不致如習知導線框,在導線與導線間產生樹脂毛 邊的現象。 第6,因為半導體元件係利用底填充材料,而固接於 散熱用電極,且該散熱用電極由背面裸露出,故本半導體 裝置所產生的熱量,可有效率的由本半導體裝置背面釋: 出。此外,利用在絕緣性黏接構件中,混入以氧化膜、 或氧化銘等填充材料,而能更進一步提昇散熱性。另,若 將填充材料的大小統一的話,便可在半導體元件Η與導 電圖案間的間隙保持一定。 接著說明半導體裝置的第3實施態樣 第:圖表示本半導體裝置40。第9A圖係其平面示意 圖,而第9B圖係A-A線剖面示意圖。 ,第1圖表示黏接墊11A,與配線11B、外接電極uc 形成-體化,但此處則在黏接塾11A背面形成外接電極。 另因黏接塾11A背面形成矩形,所以由絕緣被覆膜 16裸露出的圖案,亦形成與該矩形相同的圖案。另,考 慮底填充材料AF的固接性,而形成將散熱用電極HD 分割成複數個的溝43。 【發明功效】 藉由上述說明得知,在本發明中,將形成未使用支撐 ^板也可形成島狀之導電圖案在具厚度的導電落(或導電 箔)中,埋入於絕緣性黏接構件與絕緣性樹脂中的構造。 並且,因為裸露出位於半導體元件背面的散熱用電極,所 以半導體元件的散执可择汝盖 π * m ^ ^ —. 後改善。同時,因為未使用支撐基 巧氏張尺度適㈣家標準(CNS)A4祕 15 312146 (請先閱讀背面之注意事項再填寫本頁) ·· 裝--------訂---------線 A7
五、發明說明(16 y 板’所以可產生薄形、輕量的封裝體。 Φ 再者,利用導電圖荦、本m+ _ ^ ^干夺體凡件、底填出材料、及 絕緣性樹脂等最少必要元件構成,所以形成無浪費資源的 電路裝置。藉此在完成之前並無多餘不必要的構成元件, 故可製造大幅降低成本的半導體裝置。 【圖式簡單說明】 第1(A)及(B)圖係本發明半導體裝置之說明圖。 第2圖係本發明半導體裝置之製造方法的說明圖。 第3圖係本發明半導體裝置之製造方法的說明圖。 第4圖係本發明半導體裝置之製造方法的說明圖。 第5圖係本發明半導體裝置之製造方法的說明圖。 第6圖係本發明半導體裝置之製造方法的說明圖。 第7圖係本發明半導體裝置之說明圖。 第8圖係本發明半導體裝置所採用之導雷圖案的説 明圖。 第9(A)及(B)圖係本發明半導體裝置之說明圖。 第10(A)及(B)圖係習知半導體裝置之說明圖。 【圖示符號說明】 Φ (請先閱讀背面之注意事項再填寫本頁) 裝---- 訂- -丨線. 黏接塾 配線
散熱用電極 黏接電極 分離溝 露出部 511399 A7 B7 、發明說明(17 ) 20 導電箔 21 焊錫 50 柔性板 51 銅羯圖案 52 IC晶片 53 黏接用墊 54 焊錫球連接用墊 55 焊錫球 56 開口部 57 金屬細線 58 絕緣性樹脂 AF 底填充材料 DM 防止流動膜 SD 焊接材料 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 17 312146
Claims (1)
- 經濟部中央標準局員工福利委員會印製 W年h /1 第90103576號專利申請案 申请專利範圍修正本 (91年9月19曰 1. -種半導料置,係具備有對應半導體元件之黏接電 極而》 又置的黏接墊、設置於該半導體元件配置區域上 的政熱用電極、以面向下之方式電性連接於該黏接墊 $該半導體元件、至少設置於該半導體元件下面並裸 露出該黏接墊背面而一體化密封的底填充材料。 2·如申請專利11圍帛1項之半導體裝置,具有將該黏接 墊奇面與該底填充材料背面裸露出而一體化的將該 半導體元件密封的絕緣性樹脂。 3·如申請專利範圍第丨項之半導體裝置,其中該底填充 材料係可上升至半導體元件側面而填充於鄰接該黏 接墊間的分離溝及該黏接墊與該散熱用電極間的分 離溝。 4· 一種半導體裝置,係具備有對應半導體元件之黏接電 極而設置的黏接墊、設置於與該黏接墊一體之配線上 的外接電極、包圍該外接電極的散熱用電極、以面向 下之方式電性連接於該黏接墊的該半導體元件、至少 設置於該半導體元件下面的底填充材料。 5 ·如申明專利範圍第4項之半導體裝置,具有將該外接 電極背面與該底填充材料背面裸露出而一體化的將 該半導體元件密封的絕緣性樹脂。 6·如申請專利範圍第4項或第5項之半導體裝置,其中 該底填充材料係可上升至半導體元件侧面而填充於 本紙張尺度適用中國國家標準(CNS) A4規格(210 x 297公釐) 1 312146 DU ¥接4黏接塾間的分離溝及鄰接該配線間的分離 溝、以及该外接電極與該散熱用電極間的分離溝。 7·如申凊專利範圍第4項之半導體裝置,其中連接該半 導體το件與該黏接墊之連接構件,係為焊接材料、導 電糊劑、或非等向性導電性樹脂。 8·如申請專利範圍第1至3項中任一項之半導體裝置, 其中该黏接墊的側面,係形成彎曲構造。 9·如申請專利範圍第4項之半導體裝置,其中該黏接 墊、與该黏接墊一體的配線、與該配線一體的外接電 極側面,係形成彎曲構造。 10·—種半導體裝置之製造方法,係準備導電箔、施行半 #刻處理,俾使導電圖案形成凸狀; 以面向下之方式,將該導電圖案與半導體元件予 以連接; 使底填充材料至少滲入於該半導體元件與該導 電箔之間; 在該導電箔上設置絕緣性樹脂,俾將該半導體元 件、該導電圖案予以密封; 經濟部中央標準局員工福利委員會印製 裸露出該底填充材料背面,並去除該導電箱背 面’俾將導電圖案分離。 11 一種何體裝置之製造m準料電_、施行半 #刻處理,俾使導電圖案形成凸狀; 以面向下之方式,將該導電圖案與半導體元 以連接; H填充材料至少滲入於該半導體元件與該導 本紐尺度適用中國標準(CNS) A4規格(21〇 χ 297公幻 2 312146 H3 H3 經濟部中央標準局員工福利委員會印製 電箔之間; 裸露出該底填充材料背面,並去除該導電箔背 面,俾分離而供作為導電圖案。 如申請專利範圍第10項或第u項半導體裝置之製造 方法,係在將該導電圖案分離後,利用切割(dicing) 予以分離。 13·如申請專利範圍第10項或第u項半導體裝置之製造 方法,係在該導電羯上,乃構成單元之導電圖案係呈 矩陣狀,並分別在各單元上設置該半導體元件。 14·如申請專利範圍第13項所述半導體裝置之製造方 法,係在將該導電圖案分離後1用切割(dicing), 將該單元與該單元之間予以分離。 本紙張尺度適用中國國家標準(CNS) A4規格(210 x 297公釐) 3 312146
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EP (1) | EP1187205A3 (zh) |
JP (1) | JP3945968B2 (zh) |
KR (1) | KR100404061B1 (zh) |
CN (1) | CN1266765C (zh) |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6562671B2 (en) * | 2000-09-22 | 2003-05-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device and manufacturing method thereof |
EP1500136A1 (en) | 2002-04-11 | 2005-01-26 | Koninklijke Philips Electronics N.V. | Semiconductor device and method of manufacturing same |
US7414858B2 (en) | 2002-04-11 | 2008-08-19 | Koninklijke Philips Electronics N.V. | Method of manufacturing an electronic device |
AU2003214578A1 (en) | 2002-04-11 | 2003-10-20 | Koninklijke Philips Electronics N.V. | Method of manufacturing an electronic device, and electronic device |
US7563990B2 (en) * | 2002-08-05 | 2009-07-21 | Koninklijke Philips Electronics N.V. | Electronic product, a body and a method of manufacturing |
DE10240461A1 (de) * | 2002-08-29 | 2004-03-11 | Infineon Technologies Ag | Universelles Gehäuse für ein elektronisches Bauteil mit Halbleiterchip und Verfahren zu seiner Herstellung |
JP2004186362A (ja) * | 2002-12-03 | 2004-07-02 | Sanyo Electric Co Ltd | 回路装置 |
JP3730644B2 (ja) * | 2003-09-11 | 2006-01-05 | ローム株式会社 | 半導体装置 |
JP2005109225A (ja) * | 2003-09-30 | 2005-04-21 | Sanyo Electric Co Ltd | 回路装置 |
JP4479209B2 (ja) * | 2003-10-10 | 2010-06-09 | パナソニック株式会社 | 電子回路装置およびその製造方法並びに電子回路装置の製造装置 |
JP4446772B2 (ja) * | 2004-03-24 | 2010-04-07 | 三洋電機株式会社 | 回路装置およびその製造方法 |
DE102005007643A1 (de) * | 2005-02-19 | 2006-08-31 | Assa Abloy Identification Technology Group Ab | Verfahren und Anordnung zum Kontaktieren von Halbleiterchips auf einem metallischen Substrat |
JP5550102B2 (ja) * | 2008-01-17 | 2014-07-16 | 株式会社村田製作所 | 電子部品 |
CN103682043A (zh) * | 2013-11-28 | 2014-03-26 | 天津金玛光电有限公司 | 一种水平式led芯片的固晶方法及采用该方法制备的led光源 |
CN105161425A (zh) * | 2015-07-30 | 2015-12-16 | 南通富士通微电子股份有限公司 | 半导体叠层封装方法 |
CN105161424A (zh) * | 2015-07-30 | 2015-12-16 | 南通富士通微电子股份有限公司 | 半导体叠层封装方法 |
DE102017106055B4 (de) * | 2017-03-21 | 2021-04-08 | Tdk Corporation | Trägersubstrat für stressempflindliches Bauelement und Verfahren zur Herstellung |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5350947A (en) * | 1991-11-12 | 1994-09-27 | Nec Corporation | Film carrier semiconductor device |
US5677246A (en) * | 1994-11-29 | 1997-10-14 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices |
JPH08335653A (ja) * | 1995-04-07 | 1996-12-17 | Nitto Denko Corp | 半導体装置およびその製法並びに上記半導体装置の製造に用いる半導体装置用テープキャリア |
DE19532755C1 (de) | 1995-09-05 | 1997-02-20 | Siemens Ag | Chipmodul, insbesondere für den Einbau in Chipkarten, und Verfahren zur Herstellung eines derartigen Chipmoduls |
US5744383A (en) * | 1995-11-17 | 1998-04-28 | Altera Corporation | Integrated circuit package fabrication method |
JPH09260552A (ja) * | 1996-03-22 | 1997-10-03 | Nec Corp | 半導体チップの実装構造 |
JPH09312355A (ja) * | 1996-05-21 | 1997-12-02 | Shinko Electric Ind Co Ltd | 半導体装置とその製造方法 |
JPH10256417A (ja) | 1997-03-07 | 1998-09-25 | Citizen Watch Co Ltd | 半導体パッケージの製造方法 |
JPH10335566A (ja) | 1997-04-02 | 1998-12-18 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置とそれに用いられる回路部材、および樹脂封止型半導体装置の製造方法 |
JPH10303336A (ja) | 1997-04-30 | 1998-11-13 | Nec Corp | フリップチップ型半導体素子の樹脂封止構造 |
JPH11163024A (ja) | 1997-11-28 | 1999-06-18 | Sumitomo Metal Mining Co Ltd | 半導体装置とこれを組み立てるためのリードフレーム、及び半導体装置の製造方法 |
JPH11186326A (ja) * | 1997-12-24 | 1999-07-09 | Shinko Electric Ind Co Ltd | 半導体装置 |
JP3219043B2 (ja) * | 1998-01-07 | 2001-10-15 | 日本電気株式会社 | 半導体装置のパッケージ方法および半導体装置 |
CN1134833C (zh) * | 1998-09-30 | 2004-01-14 | 精工爱普生株式会社 | 半导体装置及其制造方法、电路基板和电子装置 |
JP3395164B2 (ja) * | 1998-11-05 | 2003-04-07 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 半導体装置 |
JP3436159B2 (ja) | 1998-11-11 | 2003-08-11 | 松下電器産業株式会社 | 樹脂封止型半導体装置の製造方法 |
US6383846B1 (en) * | 2000-03-20 | 2002-05-07 | Chi-Chih Shen | Method and apparatus for molding a flip chip semiconductor device |
-
2000
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- 2001-02-15 CN CNB011045523A patent/CN1266765C/zh not_active Expired - Lifetime
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- 2001-02-24 KR KR10-2001-0009508A patent/KR100404061B1/ko active IP Right Grant
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EP1187205A2 (en) | 2002-03-13 |
EP1187205A3 (en) | 2004-06-23 |
CN1341963A (zh) | 2002-03-27 |
CN1266765C (zh) | 2006-07-26 |
JP3945968B2 (ja) | 2007-07-18 |
KR20020020170A (ko) | 2002-03-14 |
KR100404061B1 (ko) | 2003-11-03 |
US6963126B2 (en) | 2005-11-08 |
US20020048828A1 (en) | 2002-04-25 |
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