CN1578587A - 混合集成电路 - Google Patents
混合集成电路 Download PDFInfo
- Publication number
- CN1578587A CN1578587A CNA2004100319954A CN200410031995A CN1578587A CN 1578587 A CN1578587 A CN 1578587A CN A2004100319954 A CNA2004100319954 A CN A2004100319954A CN 200410031995 A CN200410031995 A CN 200410031995A CN 1578587 A CN1578587 A CN 1578587A
- Authority
- CN
- China
- Prior art keywords
- pad
- wiring layer
- terminal electrode
- conductive wiring
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 229910000679 solder Inorganic materials 0.000 claims abstract description 67
- 239000011347 resin Substances 0.000 claims abstract description 47
- 229920005989 resin Polymers 0.000 claims abstract description 47
- 239000000853 adhesive Substances 0.000 claims abstract description 23
- 230000001070 adhesive effect Effects 0.000 claims abstract description 23
- 230000004907 flux Effects 0.000 claims description 64
- 239000011248 coating agent Substances 0.000 claims description 25
- 238000000576 coating method Methods 0.000 claims description 25
- 239000007767 bonding agent Substances 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 5
- 238000004382 potting Methods 0.000 claims description 4
- 238000003466 welding Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 16
- 239000000758 substrate Substances 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 10
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- 230000004927 fusion Effects 0.000 description 5
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- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 2
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- 238000000926 separation method Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
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- 238000009826 distribution Methods 0.000 description 1
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- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000010257 thawing Methods 0.000 description 1
Images
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- H01L23/64—Impedance arrangements
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- A—HUMAN NECESSITIES
- A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
- A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
- A47J37/00—Baking; Roasting; Grilling; Frying
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Abstract
一种混合集成电路。目前在将片状部件钎焊焊接在导电配线层的焊盘上时,熔化的焊剂会使焊盘间发生短路。本发明的混合集成电路包括:在两端形成有端子电极39B的片状部件37B;对应所述端子电极设置多个焊盘40的导电配线层35;被覆除所述焊盘以外位置的所述导电电线层的外敷层树脂38,其中,用导电性粘接剂52将所述片状部件37B的端子电极39B粘接在焊盘40上,并且在所述焊盘40间设有绝缘性粘接剂53。
Description
技术领域
本发明涉及一种片状部件的端子电极安装在形成于导电配线层上的焊盘上的混合集成电路。
背景技术
最近,越来越要求便携式计算机或打印机等电子仪器上使用的片状部件小型化、薄型化和轻量化。为此具有作为片状部件将半导体元件安装在衬底上、用绝缘树脂将该衬底模制的封装型半导体电路。
图18是现有的封装型半导体集成电路。封装型半导体集成电路介由焊剂2将LSI等裸片3安装在连接垫1上,用金属细线6连接该裸片3的电极(未图示)和引线端子5。
然后,用绝缘性树脂层9被覆连接垫1和裸片3的周围。在所述封装型半导体电路中,引线端子5利用焊剂9A安装在印刷在安装衬底7上的印刷配线8上。
该封装型半导体集成电路由于引线端子5从绝缘性树脂层9露出到外部,故焊接容易,但是整体安装尺寸大,小型化、薄型化和轻量化上存在困难。
图19和图20是改良了所述的封装型半导体集成电路的混合集成电路的平面图和剖面图。
LSI等裸片10安装在形成于导电配线层11上的连接垫11A上。位于片状电容器17的两端的电极17A1、17A2直接钎焊焊接在导电配线层14A1上形成的焊盘15A1、15A2上。
其次,LSI等裸片10的电极13A1和形成于焊盘15A1上的焊盘15B1通过金属细线16A1连接。另外,LSI等裸片10的其他的电极13A2、13A3...13A7和形成于导电配线层14A1的焊盘15B2、15B3...15B7通过金属细线16A2、16A3...16A7...连接。
如图20(A)所示,导电配线层11、14A1...14A7...上部利用分离槽18A、18B...电气分离,而下部还连接着。
导电配线层11、14A1...14A7...、安装在导电配线层11上的裸片10和金属细线16A1...16A7...通过绝缘性树脂20被覆全体。然后将导电配线层11、14A1...14A7...下部连接的部分连同绝缘性树脂20一起如点划线所示切断,将导电配线层11和导电配线层14A1...14A7...完全地电气分离。
如图20(B)所示,导电配线层11、14A1...14A7...的下面形成由绝缘性树脂20露出的形状。导电配线层11、14A1、14A2...的露出部分为了和外部进行电连接,设置焊锡等焊剂,形成外部电极21A1...21A7...。另外,没有设置导电配线层11、14A1、14A2...14A7...的外部电极的位置为了达到保护导电配线层等的目的由保护膜23被覆。
图21是混合集成电路的主要部分的放大图。片状电容器17的端子电极17A1、17A2利用焊剂26固定在形成于导电配电层14A1、14A2上的焊盘15A1、15A2上。
专利文献1 特开平04-162691号公报
发明内容
形成混合集成电路的片状电容器17的端子电极17A1、17A2用焊锡等焊剂26安装在形成于导电配线层14A1、14A2上的焊盘15A1、15A2上。
如图22所示,混合集成电路的外部电极为了安装在印刷衬底24的印刷配线25A1、25A2...上而被加热。加热时,其热量传至焊盘15A1、15A2,安装端子电极17A1、17A2和焊盘15A1、15A2的焊剂26融化,使焊盘15A1、15A2间短路。
另外可以考虑利用比形成外部电极的焊剂熔点高的焊剂安装端子电极17A1、17A2..和焊盘15A1、15A2。
但是,在敷于端子电极17A1、17A2上的镀敷层中含有锡。当所述热传递至端子电极17A1、17A2上时,含在镀敷层中的锡融化,融入焊剂26中,降低焊剂26的熔点。因此即使使用高熔点的焊剂作为焊剂26,焊剂26也会融化,使焊盘15A1、15A2间短路。
另外可以考虑使用导电性粘接剂安装端子电极17A1、17A2和焊盘15A1、15A2。在使用导电性粘接剂安装端子电极17A1、17A2和焊盘15A1、15A2时,当导电粘接剂过多时就会流出,使焊盘15A1、15A2间短路。另外,当为了将外部电极安装在印刷衬底24的印刷配线25A1、25A2上而加热时,导电性粘接剂的粘接力退化,端子电极17A1、17A2和焊盘15A1、15A2的粘接不充分。
本发明提供一种混合集成电路,将片状部件的端子电极良好地安装在形成在导电配线层上的焊盘上,其设有:在两端形成有端子电极的片状部件;对应所述端子电极设有多个焊盘的导电配线层;被覆除所述焊盘以外的所述导电配线层的外敷层树脂;电连接在所述导电配线层并且露出至下面的外部电极,其中,由焊剂安装所述片状部件的端子电极的所述焊盘间的外敷层树脂中设有空间部。
本发明提供一种混合集成电路,其设有:在两端形成有端子电极的片状部件;对应所述端子电极设有多个焊盘的导电配线层;被覆除所述焊盘以外的所述导电配线层的外敷层树脂;电连接在所述导电配线层并且露出至下面的由焊剂形成的外部电极,其中,在由焊剂安装所述片状部件的端子电极的所述焊盘间设有绝缘性树脂。
本发明提供一种使用底部填充(アング—フイル)树脂作为所述焊盘间的绝缘性树脂的混合集成电路。
本发明提供一种混合集成电路,其设有:在两端形成有端子电极的片状部件;对应所述端子电极设有多个焊盘的导电配线层;被覆除所述焊盘以外的所述导电配线层的外敷层树脂;电连接在所述导电配线层并且露出至下面的由焊剂形成的外部电极,其中,对所述片状部件的端子电极实施不合锡的镀敷,使所述端子电极和焊盘粘接的焊剂用比形成所述外部电极的焊剂熔点高的焊剂进行安装。
本发明提供一种混合集成电路,包括:在两端形成有端子电极的片状部件;对应所述端子电极设有多个焊盘的导电配线层;被覆除所述焊盘以外的所述导电配线层的外敷层树脂,其中,在所述焊盘上设有导电性粘接剂,在所述焊盘间设有绝缘性粘接剂,利用所述绝缘性粘接剂将所述片状部件主体粘接在所述外敷层树脂上,并且将所述片状部件的端子电极用所述导电性粘接剂粘接在所述焊盘上。
附图说明
图1是本发明的混合集成电路的平面图;
图2是本发明的混合集成电路的剖面图;
图3是说明本发明的混合集成电路的制造方法的剖面图;
图4是说明本发明的混合集成电路的制造方法的剖面图;
图5是说明本发明的混合集成电路的制造方法的剖面图;
图6是说明本发明的混合集成电路的制造方法的剖面图;
图7是说明本发明的混合集成电路的制造方法的剖面图;
图8是说明本发明的混合集成电路的制造方法的剖面图;
图9是说明本发明的混合集成电路的制造方法的剖面图;
图10是说明本发明的混合集成电路的制造方法的剖面图;
图11是显示本发明的混合集成电路主要部分的平面图;
图12是显示本发明的混合集成电路主要部分的剖面图;
图13是显示本发明的混合集成电路主要部分的剖面图;
图14是显示本发明的混合集成电路主要部分的剖面图;
图15是显示本发明的混合集成电路主要部分的剖面图;
图16是显示本发明的混合集成电路主要部分的剖面图;
图17是显示本发明的混合集成电路主要部分的剖面图;
图18是显示现有的混合集成电路的剖面图;
图19是现有的混合集成电路的平面图;
图20是现有的混合集成电路的剖面图,图20(A)是显示制造过程的剖面图,图20(B)是完成后的剖面图;
图21是显示现有的混合集成电路主要部分的剖面图;
图22是显示现有的混合集成电路主要部分的剖面图。
具体实施方式
根据图1~图17说明本实施方式的混合集成电路。
图1和图2是本实施方式的混合集成电路的平面图和剖面图。薄片31由粘接在绝缘树脂膜32上的第一导电膜33和第二导电膜34构成。第一导电膜33和第二导电膜34通过多层连接部件42连接着。将第一导电膜33蚀刻成所需的图案,形成第一导电配线层35,安装有半导体电路元件37A和片状部件37B。
半导体电路元件37A是LSI或IC的裸片等,片状部件37B是片状电容器或片状电阻等电路元件。
第一导电配线层35及半导体电路元件37A与片状部件37B用密封树脂层43被覆着。另外,将第二导电膜34蚀刻成所需的图案,形成第二导电配线层36。在第二导电配线层36的所需位置上形成由焊剂形成的外部电极44。
半导体电路元件37A安装在形成于外敷层树脂38上的连接垫38A上。另外,位于片状电容器37B的两端的电极39B钎焊焊接在形成于导电配线层35的焊盘40上面。另外,本实施方式中,在焊盘40表面上形成镀膜52。
其次,半导体电路元件37A的电极39A1和焊盘39B1利用金属细线41A1连接。半导体电路元件37A的其他的电极39A2、39A3..39A7和焊盘39B2、39B3...39B7利用金属细线41A2、41A3...41A7连接。
根据图3~图10说明所述的混合集成电路的制造方法。
如图3所示,利用绝缘树脂层32粘接第一导电膜33和第二导电膜34,制成薄片31。
而后,如图4所示,在薄片31的所需部位的第一导电膜33和绝缘树脂膜32上形成贯通孔52,使第二导电膜34选择性地露出。
如图5所示,在贯通孔52形成多层连接部件42,将第一导电膜33和第二导电膜34电连接。
进一步,如图6~图7所示,将第一导电膜33蚀刻成所需的图案,形成第一导电配线层35、焊盘40。
而后,以使焊盘40露出的方式,用外敷层树脂38被覆其他的部分。
如图7所示,在焊盘40上考虑到焊接性,形成Au、Ag等的镀膜52。
如图8所示,第一导电配线层35上利用外敷层树脂38电气绝缘,将半导体电路元件37A、片状部件37B安装在连接垫38A、焊盘40上。半导体电路元件37A的各电极焊盘39A和焊盘40利用金属细线41连接。片状部件37B的端子电极39B安装在焊盘40上面。
如图9所示,利用密封树脂层43被覆第一导电配线层35和半导体电路元件37A等。
如图10所示,将第二导电膜34蚀刻成所需的布线图案,形成第二导电配线层36。然后,用外敷层树脂38被覆除去构成由焊剂形成的外部电极44的位置以外的地方,构成混合集成电路。
图11和图12是显示本实施方式的混合集成电路的特征的主要部分的平面图和剖面图。所述的片状部件37B是片状电容器或片状电阻等电气部件,具有镀覆在两端的端子电极39B。
如前所述,在第一导电配线层35对应端子电极39B形成有焊盘40。并且在焊盘40间形成使焊剂46逃逸的空间部47。空间部47的周围由外敷层树脂38包围。空间部47设定为宽0.23cm、长0.10cm,但根据安装的片状部件37不同,尺寸有别。
如图12所示,在用密封树脂密封之前,将端子电极39B安装在焊盘40上。安装时,预先在焊盘40上涂敷焊锡等焊剂46,当装载端子电极39B并加热时,焊剂46熔化,端子电极39B被安装在焊盘40上。
图2所示的混合集成电路组装在用户在电子仪器等中使用的印刷配线衬底50上使用。为此将混合集成电路的外部电极44装载在印刷配线衬底50的印刷配线51上并加热。因为外部电极44由焊锡等焊剂形成,故焊剂熔化,混合集成电路安装在印刷配线51上。
在如前所述为了安装进行加热时,热由第二导电配线层36经过第一导电配线层35向焊盘40传导。有可能使安装端子电极39B和焊盘40的焊剂46熔融,如图22所示,使焊盘40间短路。但是本实施方式中由于在焊盘40间设有由外敷层树脂38包围的空间部47,故流出的焊剂46流入空间部47,防止焊盘40间短路。
图13是说明本实施方式的混合集成电路的另一实施例的平面图。
在第一导电配线层35设有焊盘40,这和图11和图12相同。但是,形成于焊盘40间、使焊剂46逃逸的空间部47设有由安装在焊盘40的片状部件37B的侧面向外侧延伸的延伸部48。另外,和前述相同,空间部47的周围由涂敷于第一导电配线层35表面的外敷层树脂38包围着。
空间部47与前述相同,长为0.16cm,但具有比焊盘40凸出0.15cm的延伸部48。另外,空间部47的长度为0.10cm,但和前述相同,设有比焊盘40向外侧突出0.15cm的延伸部48。该空间部47的长度和延伸部48的长度根据安装的片状部件不同而不同。
将混合集成电路的外部电极44接合在设在印刷配线衬底50上的印刷配线51上之后,加热。通过加热,使由焊剂形成的外部电极44熔化,混合集成电路被安装在焊盘40上。
如前所述,热由第二导电配线层36经过第一导电配线层35向焊盘40传导。有可能安装端子电极39B和焊盘40的焊剂46熔化,导致焊盘间短路。但本实施方式中由于在焊盘40间设有由外敷层树脂38包围的空间部47,故流出的焊剂46流至空间部47。
流入空间部47的焊剂46,同助熔剂一起,从位于离片状部件37B的侧面的外侧的延伸部48被洗净除去。因而流出的焊剂46不会使焊盘间短路。而且,通过除去助熔剂,片状部件37B被牢固地安装在焊盘40上。
图14是显示本实施方式的混合集成电路的的另一个实施例的剖面图。和图1不同的是不形成空间部,在焊盘40间设有底部填充树脂55。
如图2所示,将混合集成电路的外部电极44接合在设在印刷配线衬底50上的印刷配线51之后,加热。通过加热,焊剂形成的外部电极44熔解,混合集成电路被安装在印刷配线51上。
如前所述,热从第二导电配线层36经过第一导电配线层35向焊盘40传导。有可能使安装端子电极39B和焊盘40的焊剂46熔融,使焊盘40间的短路。但是本实施方式中,由于在焊盘40间设有底部填充树脂55,故流出的焊剂46A由底部填充树脂50阻止,焊盘40间不会短路。
图15是显示本实施形态的混合集成电路的另一实施例的剖面图。将端子电极39B安装在焊盘40上的焊剂46A,使用比形成外部电极44的焊剂熔点高的焊剂。实际上,例如使用由Sn5%、Pb95%构成的、熔点为300℃的高熔点的焊剂。而形成外部电极44的焊剂是一种由Sn3%、Ag0.5%、Pb96.5%组成的熔点为238℃的焊剂。
如图2所示,为了将混合集成电路的外部电极44接合在设于印刷配线基板50上的印刷配线51上,需要进行加热。当加热至238℃以上时,形成外部电极44的焊剂熔化,混合集成电路被安装在印刷配线51上。热从第二导电配线层36经过第一导电配线层35向焊盘40传导。加热端子电极39B和焊盘40,有可能使焊剂46A熔融,使焊盘40间发生短路。但是安装焊盘40和片状部件39B的高熔点的焊剂46B不到熔点,不会熔化。
另外,为了将外部电极44安装在设于印刷配线衬底50的印刷配线51上而施加的热,从第二导电配线层36经过第一导电配线层35向焊盘40传导。进一步,该热传至端子电极39B,镀敷在端子电极39B的Sn熔化。当熔化的Sn熔入高熔点的焊剂46A中时,则使高熔点的焊剂46A的熔点降低。因此有可能使高熔点的焊剂46A的熔点下降而开始熔解。
本实施形态中,用不含Sn的镀金或镀铜形成片状部件37的端子电极39B。这样,虽然为了将外部电极44安装在设于印刷配线衬底50的印刷配线51上而施加的热,从第二导电配线层36经过第一导电配线层35向焊盘40传导,但是端子电极39B的镀层中不含有Sn。因此不会使高熔点的焊剂46A的熔点降低。
图16和图17是显示本实施形态的混合集成电路的另一的实施例的剖面图。
本实施例中,使用导电性粘接剂56例如Ag膏,将片状部件37B的端子电极39B粘接在焊盘40上。但当导电性粘接剂56量多时,则渗出,使焊盘40间发生短路。当为了使外部电极44安装在印刷配线51上而施加的热,从第二导电配线层36经过第一导电配线层35向焊盘40传导时。导电性粘接剂56由于热使其粘接力降低。
因此,本实施方式中,将绝缘性粘接剂57配置在导电性粘接剂56间。该绝缘性粘接剂57配置成其上面高出导电性粘接剂56。因此,为了将片状部件37B的端子电极39B粘接在焊盘40上,在放置片状部件37B时,首先使绝缘性粘接剂57接触片状部件37B主体。
当压下片状部件37B时,导电性粘接剂56接触端子电极39B,使端子电极39B和焊盘40粘接。这时,虽然导电性粘接剂56被压而散开,但因为绝缘性粘接剂57已经接触片状部件37B,故导电性粘接剂56不会使焊盘40间发生短路。
另外,为了将外部电极44安装在印刷配线51上而施加的热,从第二导电配线层36经过第一导电配线层35向焊盘40传导。但是因为片状部件37B利用绝缘性粘接剂57和外敷层树脂38粘接,故即使导电性粘接剂56的粘接力退化,也不受影响。
本发明的混合集成电路在导电配线层上形成的焊盘间设置由树脂包围的空间部。并且,为了使混合集成电路的外部电极安装在印刷衬底上而加的热会传导至焊盘上。这时,即使固定片状部件的端子电极和焊盘的焊剂熔化流出,也可以流入空间部,防止焊剂使焊盘间发生短路。
本发明的混合集成电路在形成于导电配线层的焊盘间设有绝缘性树脂。与前述相同,为了使混合集成电路的外部电极安装在印刷衬底上而加的热会传导至焊盘上。这时,即使固定片状部件的端子电极和焊盘的焊剂熔化流出,也可以通过绝缘性树脂阻止,防止焊剂使焊盘发生短路。
本发明的混合集成电路使用比将外部电极固定在印刷配线上的焊剂熔点高的焊剂固定片状部件的端子电极和焊盘。并且因为片状部件的端子电极使用不含锡的镀层,故即使热传至端子电极使镀层熔化,也不会使高熔点的焊剂的熔点降低。
本发明的混合集成电路使用导电性粘接剂将片状部件的端子电极安装在焊盘上。由于在焊盘间设有绝缘性粘接剂,故即使导电粘接剂过多而流出,也可以由绝缘性树脂阻止,防止焊剂使焊盘间发生短路。即使由于用于将外部电极安装在印刷衬底的印刷配线的热致使导电性粘接剂的粘接力退化,也可以由绝缘性粘接剂的粘接力,保持片状部件自身的粘接力。
Claims (6)
1、一种混合集成电路,其设有:在两端形成有端子电极的片状部件;对应所述端子电极设置多个焊盘的导电配线层;被覆除所述焊盘以外位置的所述导电配线层的外敷层树脂;电连接在所述导电配线层,露出至下面的外部电极,其特征在于,在通过焊剂安装所述片状部件的端子电极的所述焊盘间的外敷层树脂上设置空间部。
2、一种混合集成电路,其设有:在两端形成有端子电极的片状部件;对应所述端子电极设置多个焊盘的导电配线层;被覆除所述焊盘以外位置的所述导电配线层的外敷层树脂;电连接在所述导电配线层,露出至下面由焊剂构成的外部电极,其特征在于,在通过焊剂安装所述片状部件的端子电极的所述焊盘间设有绝缘性树脂。
3、如权利要求2所述的混合集成电路,其特征在于,使用底部填充树脂作为所述焊盘间的绝缘性树脂。
4、一种混合集成电路,其设有:在两端形成有端子电极的片状部件;对应所述端子电极设置多个焊盘的导电配线层;被覆除所述焊盘以外位置的所述导电配线层的外敷层树脂;电连接在所述导电配线层,露出至下面由焊剂构成的外部电极,其特征在于,对所述片状部件的端子电极实施不含锡的镀敷,使所述端子电极和焊盘粘接的焊剂是比形成所述外部电极的焊剂熔点高的焊剂。
5、一种混合集成电路,其包括:在两端形成有端子电极的片状部件;对应所述端子电极设置多个焊盘的导电配线层;被覆除所述焊盘以外位置的所述导电配线层的外敷层树脂,
其特征在于,在所述焊盘上设有导电性粘接剂,在所述焊盘间设有绝缘性粘接剂,利用所述绝缘性粘接剂将所述片状部件主体粘接在所述外敷层树脂上,并且将所述片状部件的端子电极用所述导电性粘接剂粘接在所述焊盘上。
6、如权利要求5所述的混合集成电路,其特征在于,所述绝缘性粘接剂以比所述导电性粘接剂先接触所述片状部件主体的高度配置。
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CN101452926B (zh) * | 2007-09-26 | 2011-04-06 | 三洋电机株式会社 | 混合集成电路装置 |
CN106469687A (zh) * | 2015-08-20 | 2017-03-01 | 爱思开海力士有限公司 | 具有嵌入式电路图案的封装基板其制造方法及半导体封装 |
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JP2006019361A (ja) * | 2004-06-30 | 2006-01-19 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
JP2007123539A (ja) * | 2005-10-27 | 2007-05-17 | Denso Corp | 配線基板 |
DE102006033711B4 (de) * | 2006-07-20 | 2012-06-14 | Epcos Ag | Verfahren zur Herstellung einer Widerstandsanordnung |
US11621220B2 (en) * | 2021-03-25 | 2023-04-04 | Advanced Semiconductor Engineering, Inc. | Assembly structure and method for manufacturing the same |
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JP3677429B2 (ja) * | 2000-03-09 | 2005-08-03 | Necエレクトロニクス株式会社 | フリップチップ型半導体装置の製造方法 |
JP2003007921A (ja) | 2001-06-19 | 2003-01-10 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
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JP2003158378A (ja) * | 2001-11-26 | 2003-05-30 | Hitachi Ltd | 多層回路基板を有する電子回路装置の製造方法 |
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CN101452926B (zh) * | 2007-09-26 | 2011-04-06 | 三洋电机株式会社 | 混合集成电路装置 |
CN106469687A (zh) * | 2015-08-20 | 2017-03-01 | 爱思开海力士有限公司 | 具有嵌入式电路图案的封装基板其制造方法及半导体封装 |
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