TWI232074B - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit Download PDF

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Publication number
TWI232074B
TWI232074B TW93105051A TW93105051A TWI232074B TW I232074 B TWI232074 B TW I232074B TW 93105051 A TW93105051 A TW 93105051A TW 93105051 A TW93105051 A TW 93105051A TW I232074 B TWI232074 B TW I232074B
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TW
Taiwan
Prior art keywords
pads
aforementioned
wiring layer
integrated circuit
conductive
Prior art date
Application number
TW93105051A
Other languages
English (en)
Other versions
TW200501843A (en
Inventor
Toshimichi Naruse
Nobuhisa Takakusaki
Hajime Kobayashi
Original Assignee
Sanyo Electric Co
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Publication date
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of TW200501843A publication Critical patent/TW200501843A/zh
Application granted granted Critical
Publication of TWI232074B publication Critical patent/TWI232074B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J37/00—Baking; Roasting; Grilling; Frying
    • A47J37/06—Roasters; Grills; Sandwich grills
    • A47J37/067—Horizontally disposed broiling griddles
    • A47J37/0682—Horizontally disposed broiling griddles gas-heated
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Description

1232074 玖、發明說明： 【發明所屬之技術領域】 本發明係關於晶片元件之端子電極安裝於配置在導電 配線層之焊墊的混合積體電路。 【先前技術】 最近使用於攜帶用電腦或印表機等的電子機器之晶片 70件，有著小型化、薄型化以及輕量化的迫切需求。因此， 在做為晶片元件中，有一種在基板上安裝半導體元件，並 將該基板以絕緣樹脂塑模（则⑷之封裝型半導體電路。 第18圖為傳統之封裝料導體㈣電路。封裝型半導
LSI(large scale integated circuit ： A 積體電則等裸晶片3介由焊材2安裝於晶粒焊墊】，並利 用金屬細線6使該禮曰y )从兩Λ 更哀裸曰曰片3的電極（未圖示）與引線端子5 連接。 此外，以絕緣性樹脂層9覆蓋晶粒焊墊1以及裸晶片 ^周圍;；在前述封裝型半導體電路中，引線端子5係以 、θ材9安裝於印刷在安裝基板7的印刷配線$上。 此封裝型半導體積體電路’由於其引線端子5係由絕 ;性樹脂層9露出於外部，因此雖較易進行焊接，但因其 整體的安裝尺寸偏大’而有不易達到小型化、薄型化以及 輕量化的問題。 第19圖以及第2〇圖，為改良前述封裝型半導體基體 電路後之混合積體電路之平面圖以及剖面圖。 等裸θ曰片1 0 ’係安裝在形成於導電配線層1 1上的 315544 5 1232074 晶粒焊墊1 1A。此外，位於晶片電容器1 7兩端之電極 17Α1、ΠΑ2，直接焊接於形成在導電配線層14Α1上的焊 墊 15Α1、15Α2。 接著，LSI等裸晶片10的電極13Α1與形成於焊塾 15A1之接合焊墊15B1，係藉由金屬細線16A1連接。此外， LSI等裸晶片1〇之其他電極13a2、13A3......13A7與形成 於導電配線層14A1的接合焊墊15B2、15B3......15B7，則 精由金屬細線16A2、16A3......16A7......連接。 如第20圖（A)所示，導電配線層η、14A1……14A7·.· 上部係藉由分離溝1 8A、1 8B…進行電性分離，但其下部 依然連接。 以絕緣性樹脂20覆蓋導電配線層丨丨、14A1… 1 4A7 ·、安裝於導電配線層丨丨的裸晶片丨〇以及金屬細線 16Α1.·.16Α7…的整體部分。之後，如一點鏈線所示，一起 切斷導電配線層η、14Α1".14Α7下部的連接部分與絕緣 性樹脂2〇,使導電配線層η與導電配線層ΐ4Αρ..ΐ4Α7... 得以達到完全電性分離。 如第20圖（Β)，在導電配線層u、14Ai…Μ"…的下 面’呈現自絕緣性樹脂2〇外露的型態。導電配線層U、 购：14Α2...的露出部分，為與外部進行電性連接，設置 焊錫等的焊材形成外部電極2 1 a··. 2 1 λ 7 „^ 1A7···。此外，在未言5 置導電配線層11、14A1、14Α2···14Α7从， Α7···的外部電極的部 为，則覆蓋有用以保護導電配線層等之阻劑膜23。 第21圖為混合積體電路的重、 里要；分放大圖。晶片電溶 315544 6 1232074 Ή的端子電極17A1、17A2係藉由焊材％固定於形成 在導電配線層14A1、14A2的焊墊15A1、15A2。 [專利文獻] 曰本特開平04-162691號公報 【發明内容】 [發明所欲解決的課題] 形成混合積體電路之晶片電容器1 7的端子電極 17A1、17A2,係利用焊錫等焊材26安裝於形成在導電配 線層 14A1、14A2 之焊墊 15A1、15A2。 如第22圖所示，混合積體電路之外部電極，為了安穿 於印刷基板24的印刷配線25A1、25A2···上而進行加=: 當進行加熱時，該熱會傳導到焊墊15A1、15A2，因安裝 端子電極uahm與焊墊15A1、15A2的焊材26:解、， 而會導致焊墊1SA1、BA2之間產生短路。 更南之焊材，來安 、1 5A2也是一種可 此外以較形成外部電極的焊材熔點 裝端子電極17A1、17A2···與焊墊15A1 行方法。 但，由於施加於端子電極17A1、17A2的鍍覆中含有 錫。當前述的熱能，傳導至端子電極17A1、17A2時^鍍 覆中所含的錫會熔化並熔解至焊材26中，而導致焊材^ 的熔點降低。因此，即使使用高熔點焊材作為焊材％，焊 材26也會炼解，並導致焊墊15A1、15A2間產生短路。 此外，也可嘗試使用導電性接合劑來安裝端子電極 1^、17A2與焊塾15A1、15A2。利用導電性接合劑安裝 315544 7 1232074 端子電極17A1、17A2···與焊墊15A1、15A2時，若導電接 合劑過量時會外流，而導致焊墊15A1、15A2之間發生短 路。此外，為將外部電極安裝於印刷基板24的印刷配線 25A1、25A2而進行加熱時，會導致導電性接合劑的接合 力降低，同時造成端子電極17Α^17Α2與焊墊ΐ5Α^ΐ5Α2 間的接合力不足之問題。 [解決課題之手段] 本發明係提供-種混合積體電路，使晶片元件的端子 電極與形成於導電配線層的焊墊得以進行良好安裝者， 配置有：兩端形成有端子電極之晶片元件；對應前述 端子電極而配設有複數焊墊的導電配線層；覆蓋前述焊塾 以外之前料電配線層的外覆層樹脂；以及與前述導電配 線層電性連接，並露出於下面之外部電極，其巾，前述晶 =件的料係在以焊材安裝之前料墊間的外覆 層樹脂中設有空間部。 ::明又提供一種混合積體電路，配置有：兩端形成 晶片元件；對應前述端子電極而設有複數焊 外覆層樹脂；以及由焊材所構成：之…電配線層的 線層電性連接，並由露出得以與前述導電配 晶片元件的端子電極，係在：:::：電極’其中’前述 絕緣性樹脂。 在4材女裝之前述焊墊間設有 本發明提供一種使用底部填 *、縫Μ月曰做為前述焊塾間的 絕緣性樹脂的混合積體電路。 巧引：坪登間的 315544 8 1232074
本發明係提供—錄、B 有端子電極之晶片積體電路’配置有：兩端形成 洋塾的導電配線層ΓιΓ應前述端子電極而配設有複數 的外覆層樹脂；以及：焊塾：外：前述：電配線層 線層電性連接，並露出 之侍以與刖述導電配 片元件的端子電極進下面之之外部電極，係對前述晶 極盥π故θ 仃不含錫的鍍覆，而黏接前述端子電 之二二料材’係以融點高於形成前述外部電極的焊材 之尚熔點焊材予以安裝。 电位的知材 本發明係提供-種現合積體電路， :端子電極的晶片元件；對應前述端子電極而有 塾的導電配線層；由覆蓋前述焊墊以外之前述導 的:卜覆層樹脂所形成，於前述焊塾上設有導電性接合：： 而2述焊塾間設置絕緣性接合劑，利用前述絕緣性接合 Μ使刚述晶片元件主體接合於前述外覆層樹脂而利用前 述導電性接合劑使前述晶片元件之端子電極接合於前 墊。 Τ 【實施方式】 根據第1圖至第17圖’說明本實施型態之混合積體電 路。 第1圖以及第2圖為本實施型態之混合基體電路的平 面圖以及剖面圖。薄片31’係由接合於絕緣樹脂膜32的 第！導電膜33與第2導電膜34所構成。第”電膜” 與第2導電膜34係藉由多層連接構造42#互連接。將第 1導電膜33蝕刻成所需的圖案以形成第i導電配線層35， 315544 9 1232074 並安裝半導體電路元件37A與晶片元件37b。 片-杜首體電路凡件37A可為LSI或Ic的裸晶片等，晶 '牛37B為晶片電容器或晶片電阻等的電路元件。 :1導電配線層35及半導體電路元件37a與晶片元 係被密封樹脂層43所覆蓋。此外，將第2導電膜 Μ敍刻成所需的圖案形成第2導電配線層％。之後，在第 2導電配線層36的指定部位形成由焊材構成的外部電極 44 〇 半導體電路元件37A安裝於形成在外覆層樹脂38上 的曰曰粒*干墊3 8 A上。$，位於晶片電容器3 7B兩端的電極 3叩料接於形成於導電配線層35之焊塾4G上面。此外， 在本實施型態中，焊墊4〇的表面形成有鍍覆膜52。 接著，半導體電路元件37A的電極39A1與接合焊墊 39B1，係藉由金屬細線41Al相互連接。此外，半導體電 路70件37A的其他電極39A2、39Α3···39Α7與接合焊墊 39Β2、39Β3···39Β7，則藉由金屬細線 41Α2、41Α3···417Α7 進行連接。 根據第3圖至第1 〇圖說明前述混合積體電路之製造方 法。 如第3圖所示，將第1導電膜33與第2導電膜34以 絕緣樹脂層32接合形成薄片31。 接著如第4圖所示，在薄片31的所要位置之第1導電 膜33以及絕緣樹脂膜32形成貫通孔52，選擇性地露出第 2導電膜34。 10 315544 1232074 :第5圖所示，在貫通孔52形成多層連接構造& 、連接弟1導電膜33與第2導電膜34。 _!二1°第6圖以及第7圖所示，將帛1導電膜33 ^所需的圖案’形成第1導電配線層35與焊塾4〇。 以露t ’以外覆層樹脂38覆蓋其他部分，使焊塾40得 =7圖所示’考慮結合性在焊塾4〇上形 銀（Ag)等的鍍覆膜52。 了絕緣’在晶粒焊墊38α、焊墊4。上 兀件37Α與晶片元件37Β。藉由金屬細線41連 料¥體電路元件37Α的各電極焊墊39Α與焊墊40。此 曰曰片兀件37Β的端子電極39Β ’係安裝於焊塾* 面。 如第9圖所示，以密封樹脂層43 35以及半導體電路元件37八等。 ¥電配線層 :第丄〇圖所示’將第2導電膜34姓刻 形成第2導電配绫展以 U未 、、泉層36。之後，以外覆層樹 焊材所形成之外部雷朽, 復盍由 路。 p電極44以外的部分，構成混合積體電 第11圖以及第12圖， 電路特徵的重要部位平面圖 3 7B為晶片電容器或晶片電 施以鍍覆之端子電極39B。 為顯示本實施型態之混合積體 以及剖面圖。前述晶片元件 阻等的電氣零件，其兩端具有 315544 11 1232074 此外，如先前所述，在第1導電配線層3 5，形成有對 應端子電極39B的焊墊40。並在焊墊40間形成有可使焊 材46溢出之空間部47。因此，形成空間部47的周圍被外 覆層樹脂38所包圍。將空間部47設定為寬0.23cm，長 0.10cm的大小，但是其大小會隨安裝晶片元件37而有所 不同。 如第12圖所示，在以封裝樹脂進行封裝前，先將端子 電極39B安裝於焊墊40。在安裝時，事先在焊墊4〇塗抹 焊錫等焊材46 ’再將端子電極39B置於其上進行加熱，此 時因焊材46的熔解而使端子電極39B安裝於焊墊4〇上。 苐2圖所示的混合積體電路，為提供使用者將其組裝 於用於電子機器等的印刷配線基板5G利。為此必須將混 合積體電路的外部電極44置於印刷配線基板Μ的印刷配 線上以進行加熱。由於外部電極44係由焊錫等焊材所形 肖材θ料，而使混合積體電路得以安裝於印刷 配線51。 導電配線層36 Μ由第丨〜1呀，熱會從第 使安裝端子電電配線層35傳達至焊墊4〇。 :^ a所J與嬋墊4〇的焊材“炫解，以致會 士苐22圖所不烊塾4()間發生短路㈣題 施型態中，因焊墊-疋’在本 空間部47,故流出❹ 外覆層樹脂38所包圍 ^ 出的十材46會流入空間部47而得以狀 焊墊40間發生短路。 丨47而侍以防， 第13圖為說明士 ^ 焉轭型怨之混合積體電路其他實施 315544 12 1232074 例之平面圖。 在第1導電配線層35，設有焊墊40，此係與第11圖 以及第12圖相同。但，形成於焊墊4 〇間，用以溢入焊材 46的空間部47，則設置有延伸至較安裝於焊墊4〇的晶片 元件37B側面更外側的延伸部48。此外，與前述相同空間 部47的周圍，係被塗抹於第1導電配線層35表面的外覆 層樹脂3 8所包圍。 空間部47，與前述相同其長度為〇16cm，但其擁有較 焊墊40犬出〇15cm的延伸部48。此外，空間部的長 度雖為0.1〇cm，但與前述相同其設有較焊墊4〇向外侧突 出〇.i5Cm的延伸部48。該空間部47的長度以及延伸部48 的長度會隨安裝晶片元件所不同。 將混合積體電路的外部電極4 4接合於配設於印刷配 冰基板5G的印刷g己線5 i後，進行加熱。藉由加熱由焊材 形成的外部電極44會料，混合積體f路便可安裝於焊墊 如刖述熱會從第2導電配線層36經由第1導電配線層 傳達至焊塾40。而使安襄端子電極39b與焊塾利的 材46溶解，以致導致惶轨 导致烊墊40間可能會發生短路。但， 本實施型態中，因在煜執 墊4〇間設置有由外覆層樹脂3 8 包圍的空間部4 7，因此、、益、、去山 〇。 益，爪出的焊材46會流往該空間部 流進空間部47的焊姑μ a 1 m t 坪材46，會由位於較晶片元件 側面更外側之延伸部48 ^ ^ ^ ^ ^ 一助J：干劑一起被清洗去除。 315544 13 1232074 不會發生流出的焊材46造成焊墊4〇間短路的問題。而且 藉由去除助焊劑可使晶片元件37B更穩固地安裝於焊塾 1 4圖為表示本實施型能 十貝w i忽之汁匕合積體電路其他實施 的剖面圖。與第12圖不同虛為、、/7古/ 口个U慝马，又有形成空間部，而在 40間設置底部填縫樹脂55 如第2圖所示，使混合積體電路的外部電極44接人於 配設於印刷電路基板5G的印職線後，進行加熱。藉:加 熱由焊材形成的外部電極44會溶解，混合積體電路即可安 裝於印刷配線5 1。 如前所述，熱會從第2導電配線層36經由帛ι導電配 線層35傳達至焊墊4G。而使安裝端子電極柳與焊塾利 的焊材46熔解，以致焊墊4〇間可能會發生短路。作，在 本實施型態中，因焊墊4〇間設有底部填縫樹脂Μ，故流 出的焊材46A會被底部填縫樹脂55所阻擋，而不會產^ 焊墊40間的短路問題。 θ 第I5圖為表示本實施型態之混合積體電路其他實施 例的剖面圖。用以將端子電極39Β安裝於焊墊4〇的焊材 46Α，係使用較形成外部電極44之焊材溶點更高的焊材。 實際上，舉例來說，可使用由5%的錫（Sn)，95%的錯㈣ 所組成的，熔點為3〇(TC的高熔點焊材。另一方面，形成 外部電極44的焊材’則可使用由3%的Sn，〇.5%的岣， 96 · 5 %的Pb所組成的，炼點為23 8 °C的焊材。 如第2圖所示，為將混合積體電路的外部電極44接合 315544 14 1232074 於配°又於印刷配線基板5 0的印刷配線必須進行加熱。當以 238度以上的溫度進行加熱時，形成外部電極44的焊材會 熔解，混合積體電路即可安裝於印刷配線5丨。此外，熱會 攸第2導電配線層36經由第1導電配線層35傳達至焊墊 40。此外’當對端子電極卿與焊塾4〇進行加熱時，焊 材似會溶解，而可能導致焊墊4G間發生短路的問題。 但，安裳焊塾40與晶片元件39B的高溶點焊材46B未到 炼點故不會溶解。 以使外部電極44安裝於印刷配線基板50的印刷配 線5 1所進行之加熱的熱纟，會從第2導電配線層％經由 第m線層35傳達至焊墊4G。而且，該熱度會傳達 至端子電極39B’鑛覆於端子電極携上的^會溶解。 ^此溶解的Sn熔人高㈣焊材似_，會降低高炼點焊 的熔點。因此，會有高溶點焊材似的溶 熔出的問題。 * 在本實施型態中，孫U 。 係以不έ Sn的鍍金或是鍍銅來形 成日日片7L件37的端子電極1 , + B。如此一來，用以使外部電 極44安裝於印刷配線基柘 μ板5G的印刷配線51所進行之加熱 的熱度，雖會從第2#雷献# s ,,^ 電配線層36經由第1導電配線層 35傳達至焊墊40，但由於pi% 一 一於鳊子電極39B的鍍覆中沒有含 n。因此H點焊材46㈣點不會降低。 第16圖以及第17圖為矣一丄— 败ία— α為表不本實施型態之混合積體電 路其他貫施例的剖面圖。 在本實施例中，係使用暮雷 尤用V電性接合劑56例如：Ag膏， 315544 15 1232074 來使晶片元件37B的端子 ^ 電極3 9接合於焊墊4 〇。但，者 V電性接合劑5 ό的量太多丨合 一 δ 路。另外用以將外部電極 』扪短 4女凌於印刷配線5丨時 之加熱的熱度，會從第2 斤進仃 a，c & 等電配線層3 6經過第1導電s綠 層35傳達至焊墊40,受埶霧 -己線 1々 熱之V電性接合劑56會產生桩人 力降低的問題。 《 i生接合 因此在本實施型能φ 总士 中係在導電性接合劑56間配置絕 卓。冑57 °此外，該絕緣性接合劑57,係以其上面會 :4接合劑56更高之方式配置。因此，為使晶片元件 37B的端子電極39接合於焊塾4〇，當放置晶片元件仰 時’百先，使絕緣性接合劑57與晶片元件37 此山外，晶片元件37B往下壓時會使導電性=劑 %與端子電極3 9B接觸，而端子電極39B與焊墊4〇會進 ―妾ό此時，導電性接合劑5 6雖會被壓寬，但因絕緣性 接合劑57已先接觸晶片元件37Β，故導電性接合劑56不 會使焊墊40間產生短路。 此外’用以將外部電極44安裝於印刷配線5 1時所進 行之加熱的熱度，會從第2導電配線層36經過第1導電配 線層35傳達至焊墊4〇。但，由於晶片元件37β係藉由絕 緣性接合劑57而與外覆層樹脂38相黏接，因此即使導電 性接合劑56的接合力降低也不會造成任何影響。 [發明之效果] 本發明之混合積體電路，係在形成導電配線層的焊墊 間設置由樹脂所環繞之空間部。此外，用以將該混合積體 315544 16 1232074 電路的外部電極安裝於印刷基板之熱，會傳達至悍墊。此 時’固疋晶片元件的端子電極與焊墊的焊材即使熔化流 出，亦會流往該空間部，而得以防止焊材造成焊墊間的短 路0 此外，本發明之混合積體電路，係在形成於導電配線 層之焊墊間配設絕緣性樹脂。此外，與前述相同，用以將 混合積體電路的外部電極安裝於印刷基板之熱會傳達至焊 墊。此時，m定晶片元件的端子電極與焊墊的焊材即使炼 化流出，亦會被該絕緣性樹脂所阻擋，而得以防止焊材造 成焊塾間的短路。 此外，本發明之混合積體電路，係使用較使外部電極 固定於印刷配線之焊材更高㈣的焊材，來固定晶片元件 的端子電極與焊塾。此外，由於晶片元件的端子電極中係 使用不含錫的鑛覆，因此即使熱傳導至端子電極，鑛覆產 生融化，亦不會降低高熔點焊材的熔點。 此外’本發明之混合積體電路，係使用導電性接合劑 將晶片元件的端子電極安裝於焊墊上。此外，由於在上述 之焊墊間配設有絕緣性接合劑’因此即使因導電性接合劑 的量過多而導致溢流，也會被絕緣性接合劑所阻擋，而得 以阻止焊㈣產生短路。此外，_以將外部電極安装於 印刷基板之熱，導致導電性接合劑的接合力產生劣化時 也會因絕緣性接合劑的接合力而得以俘 、’ 接合力。 保持…件本身的 【圖式簡單說明】 17 χ232〇74 $ 1圖為本發明之混合積體電路的平面圖 第2圖為本發明之混合積體電路的剖面圖 第 面圖 圖為說明本發明之混合積體電路的製造方法之剖 面圖 第 4 、 ' 圖為說明本發明之混合積體電路的製遠方法之剖 第 面圖 圖為說明本發明之混合積體電路的製造方法之剖 面圖 當 、 6圖為說明本發明之混合積體電路的製邊方法之剖 第 面圖 第 面圖 圖為說明本發明之混合積體電路的製遠方去之剖 圖為說明本發明之混合積體電路的製邊方法之剖 面圖 圖為說明本發明之混合積體電路的製造方法之剖 第1 0 剖面圖 圖為說明本發明之混合積體電路的製造方法之 第11 平面圖 圖為顯 示本發明之混合積體電路的重要部分 之 第12 剖面圖 圖為顯 示本發明之混合積體電路的重要部分 之 第13 剖面g 图為顯示本發明之混合積體電路的重要部八 之 18 l232〇74 第1 4圖為顯示本發 剑务圖。 明之混合積體電路的重要部分 之 、第15圖為顯示本發明之混合積體電路的重要部分 圖 之 之 、第16圖為顯示本發明之混合積體電路的重要部分 立 第1 7圖為顯示本發明之混合積體電路的重要部八 例兩一 口丨刀 圖。 之 第1 8圖為顯示先行之混合積體電路之剖面圖。 第19圖為顯示先行之混合積體電路之平面圖。 第20圖為先行之混合積體電路的剖面圖，莖 為鈕 弟20圖（A) ’示製造過程之剖面圖，第20圖（B)為製造完 立 圖。 70风之剖面 面圖 第2 1圖為顯示先行之混合積體電路的重要部分之剖 之剖 第22圖為顯示先行之混合積體電路的重要邻八 面圖。 口刀 [&件符號說明] 薄片 35 第1導電配線層 第2導電配線層 37A 半導體電路元件 晶片元件 38 外覆層樹脂 端子電極 40 焊墊 密封樹脂 44 外部電極 焊材 46A 高熔點焊材 31 3 6 43 315544 19 46 1232074 47 空間部 50 印刷基板 52 鍍覆膜 55 底部填縫樹脂 56 導電性接合劑 57 絕緣性接合劑
20 315544

Claims (1)

  1. 4 l232〇7 拾 i申請專利範圍·· • 7種混合積體電路，係配置有：兩端形成有端子電極之 p片凡件；對應前述端子電極配設有複數焊墊之導電配 j層，覆盍前述焊墊以外之前述導電配線層的外覆層樹 月曰，以及與前述導電配線層電性連接，且: 外部電極， ㈣下面之 2. 其中，前述晶片元件的端子電極，在利用焊材安裝 J it 4墊間的外覆層樹脂中設有空間部。 :種混合積體電路，係配置有··兩端形成有端子電極之 曰曰片7G件，對應前述端子電極配設有複數焊墊的導 =層；覆蓋前述焊墊以外之前述導電配線層的外覆層樹 及由焊材所構成，使之得以與前述導電配線層電 連接且露出於下面之外部電極， A /、 4述θθ片元件的端子電極，係在以焊材安裝 之則述焊墊間設有絕緣性樹脂。 、 4. 申明專利範圍第2項之混合積體電路，其中，係使用 底部填縫樹脂做為前述焊㈣的絕緣性樹脂。 一種^合積體電路，配置有：兩端形成有端子電極之晶 前述端子電極而配設有複數之焊墊的導電 述焊塾以外之前述導電配線層的外覆層 電 卜材所構成’使之得以與前述導電配線層 電連接且露出於下面之外部電極， 舜而、Λ對則述晶片元件的端子電極進行不含錫的鍍 復，而黏接前述端子電極與焊塾的谭材，係融點高於形 315544 21 1232074 $物外部電極的淳材。 _匕口積體電路’係由：在兩端形成有端子電極的晶 片疋件，對應别述端子電極而設有複數焊塾的導電配線 層；以及覆蓋前述焊墊以外部分之前述導電配線層的外 覆層樹脂所形成， Ρ⑴墊上設置導電性接合劑，並在前述 焊塾間設置絕緣性接合劑，制前述絕緣性接合劑使前 述晶片元件，合於前述外覆層樹脂，並利用前述導 電性接合劑“述晶片元件之端子電極接合於前述焊 塾° 6.如申請專利範圍第5項之混合積體電路，其中 絕 =接二=可較前述導電性接合劑更早接觸前述 日日片疋件主體之向度進行配置。 315544 22
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JP2005347353A (ja) * 2004-05-31 2005-12-15 Sanyo Electric Co Ltd 回路装置およびその製造方法
JP2006019361A (ja) * 2004-06-30 2006-01-19 Sanyo Electric Co Ltd 回路装置およびその製造方法
JP2007123539A (ja) * 2005-10-27 2007-05-17 Denso Corp 配線基板
DE102006033711B4 (de) * 2006-07-20 2012-06-14 Epcos Ag Verfahren zur Herstellung einer Widerstandsanordnung
JP2009081279A (ja) * 2007-09-26 2009-04-16 Sanyo Electric Co Ltd 混成集積回路装置
KR20170023310A (ko) * 2015-08-20 2017-03-03 에스케이하이닉스 주식회사 임베디드 회로 패턴을 가지는 패키지 기판, 제조 방법 및 이를 포함하는 반도체 패키지
US11621220B2 (en) * 2021-03-25 2023-04-04 Advanced Semiconductor Engineering, Inc. Assembly structure and method for manufacturing the same

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US5591941A (en) * 1993-10-28 1997-01-07 International Business Machines Corporation Solder ball interconnected assembly
WO1999036957A1 (fr) * 1998-01-19 1999-07-22 Citizen Watch Co., Ltd. Boitier de semiconducteur
JP3677429B2 (ja) * 2000-03-09 2005-08-03 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置の製造方法
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