JP2005277001A - 回路装置およびその製造方法 - Google Patents
回路装置およびその製造方法 Download PDFInfo
- Publication number
- JP2005277001A JP2005277001A JP2004086555A JP2004086555A JP2005277001A JP 2005277001 A JP2005277001 A JP 2005277001A JP 2004086555 A JP2004086555 A JP 2004086555A JP 2004086555 A JP2004086555 A JP 2004086555A JP 2005277001 A JP2005277001 A JP 2005277001A
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- Prior art keywords
- resin film
- conductive pattern
- conductive
- circuit device
- resin
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 239000011347 resin Substances 0.000 claims abstract description 168
- 229920005989 resin Polymers 0.000 claims abstract description 168
- 239000011888 foil Substances 0.000 claims abstract description 60
- 238000000926 separation method Methods 0.000 claims abstract description 34
- 238000007789 sealing Methods 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 20
- 239000000853 adhesive Substances 0.000 claims description 14
- 230000001070 adhesive effect Effects 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 3
- 239000007787 solid Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 description 33
- 238000005219 brazing Methods 0.000 description 18
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000009719 polyimide resin Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000007747 plating Methods 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 3
- 229960003280 cupric chloride Drugs 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005266 casting Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- JYLNVJYYQQXNEK-UHFFFAOYSA-N 3-amino-2-(4-chlorophenyl)-1-propanesulfonic acid Chemical compound OS(=O)(=O)CC(CN)C1=CC=C(Cl)C=C1 JYLNVJYYQQXNEK-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 239000004734 Polyphenylene sulfide Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
- H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
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- H05K1/02—Details
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
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- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
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- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
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- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
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- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
Abstract
【解決手段】 本形態の回路装置の製造方法では、導電箔10を用意する工程と、導電箔10の表面に分離溝12を形成することにより導電パターン13を凸状に形成する工程と、導電箔10の表面を樹脂膜15で被覆して、12分離溝を被覆する樹脂膜15の厚さを導電パターン13の上面を被覆する樹脂膜15よりも厚く形成する工程と、樹脂膜15を除去することにより前記導電パターンの上面を樹脂膜15から露出させる工程と、樹脂膜15から露出する導電パターン13と回路素子とを電気的に接続する工程と、回路素子が封止されるように封止樹脂20を形成する工程と、導電パターン13同士が分離されるまで導電箔10の裏面を除去する工程を具備する。
【選択図】 図4
Description
図1から図5を参照して本形態の回路装置の製造方法を説明する。本形態の回路装置の製造方法では、導電箔10を用意する工程と、導電箔10の表面に分離溝12を形成することにより導電パターン13を凸状に形成する工程と、導電箔10の表面を樹脂膜15で被覆して、分離溝12を被覆する樹脂膜15の厚さを導電パターン13の上面を被覆する樹脂膜15よりも厚く形成する工程と、樹脂膜15を除去することにより前記導電パターンの上面を樹脂膜15から露出させる工程と、樹脂膜15から露出する導電パターン13と回路素子とを電気的に接続する工程と、回路素子が封止されるように封止樹脂20を形成する工程と、導電パターン13同士が分離されるまで導電箔10の裏面を除去する工程を具備する。以下では、上述した回路素子の一例として、半導体素子16とチップ素子17との組み合わせを採用している。このような各工程を以下にて詳述する。
本形態では、図6と図7を参照して、内蔵される回路素子としてフェイスダウンの半導体素子を採用した場合の回路装置の製造方法を説明する。本形態の回路装置の基本的な製造方法は上述した第1の実施の形態と同様であるので、相違点を中心に以下の説明は行う。
本形態では、上述した実施の形態で製造可能な回路装置の一例を説明する。図8(A)は回路装置9の平面図であり、図8(B)はその断面図である。この図に示す回路装置9では、複数個の回路素子が内蔵され、各々が金属細線19または導電パターン13を介して電気的に接続されている。
本実施の形態では、多層の配線構造を有する回路装置の構成および製造方法を説明する。本形態でも、露光マスクを用いた露光の工程を省いて、導電パターンの露出を行っている。各工程の詳細を以下にて説明する。
10 導電箔
11 エッチングレジスト
12 分離溝
13 導電パターン
14 樹脂シート
15 樹脂膜
16 半導体素子
17 チップ素子
18 ロウ材
19 金属細線
20 封止樹脂
Claims (14)
- 導電パターンと、
前記導電パターンと電気的に接続された回路素子と、
前記導電パターン同士の間に形成されて前記導電パターンの側面を被覆する樹脂膜と、
前記導電導電パターンの上面および側面に接触して前記回路素子を前記回路素子と固着させる接着剤と、
前記回路素子を封止する封止樹脂とを具備することを特徴とする回路装置。 - 前記接着剤は、導電性あるいは絶縁性の接着剤であることを特徴とする請求項1記載の回路装置。
- 前記接着剤の側面は、滑らかな曲面を描くことを特徴とする請求項1記載の回路装置。
- 前記導電パターンは、多層の配線構造を有することを特徴とする請求項1記載の回路装置。
- 前記回路素子は、フリップチップで実装される半導体素子であることを特徴とする請求項1記載の回路装置。
- 導電パターンを構成する工程と、
前記導電パターンが被覆されるように樹脂膜を形成する工程と、
前記樹脂膜から前記導電パターンの上面を露出させる工程と、
前記導電パターンに接着剤を介して回路素子を電気的に接続する工程と、
前記回路素子を被覆する工程とを具備することを特徴とする回路装置の製造方法。 - 導電箔を用意する工程と、
前記導電箔の表面に分離溝を形成することにより導電パターンを凸状に形成する工程と、
前記導電箔の表面を樹脂膜で被覆して、前記分離溝を被覆する前記樹脂膜の厚さを前記導電パターンの上面を被覆する前記樹脂膜よりも厚く形成する工程と、
前記樹脂膜を除去することにより前記導電パターンの上面を前記樹脂膜から露出させる工程と、
前記樹脂膜から露出する前記導電パターンと回路素子とを電気的に接続する工程と、
前記回路素子が封止されるように封止樹脂を形成する工程と、
前記導電パターン同士が分離されるまで前記導電箔の裏面を除去する工程とを具備することを特徴とする回路装置の製造方法。 - 前記樹脂膜を均一にエッチングすることで、前記導電パターンの上面を前記樹脂膜から露出させることを特徴とする請求項6または請求項7記載の回路装置の製造方法。
- 前記回路素子は、フェイスダウンで実装される半導体素子を含むことを特徴とする請求項6または請求項7記載の回路装置の製造方法。
- 前記導電パターンの裏面は、外部電極を構成することを特徴とする請求項7記載の回路装置の製造方法。
- 前記樹脂膜の露光を行ってから、前記樹脂膜の除去を行うことを特徴とする請求項6または請求項7記載の回路装置の製造方法。
- 前記樹脂膜の形成は、フィルム状の前記樹脂膜を真空プレスで前記導電箔に積層させることで行うことを特徴とする請求項6または請求項7記載の回路装置の製造方法。
- 前記樹脂膜の形成は、液状あるいは半固形状の樹脂を前記導電箔の表面に塗布することで行うことを特徴とする請求項6または請求項7記載の回路装置の製造方法。
- 前記導電パターンの側面が部分的に露出するまで、前記樹脂膜の除去を行うことを特徴とする請求項6または請求項7記載の回路装置の製造方法。
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TW094104283A TW200536441A (en) | 2004-03-24 | 2005-02-15 | Circuit device and manufacturing method thereof |
CNB2005100558019A CN100356822C (zh) | 2004-03-24 | 2005-03-16 | 电路装置及其制造方法 |
KR1020050022175A KR100613791B1 (ko) | 2004-03-24 | 2005-03-17 | 회로 장치 및 그 제조 방법 |
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US7329957B2 (en) | 2008-02-12 |
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