JP2019057590A - 半導体素子用基板及びその製造方法、半導体装置及びその製造方法 - Google Patents
半導体素子用基板及びその製造方法、半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP2019057590A JP2019057590A JP2017180608A JP2017180608A JP2019057590A JP 2019057590 A JP2019057590 A JP 2019057590A JP 2017180608 A JP2017180608 A JP 2017180608A JP 2017180608 A JP2017180608 A JP 2017180608A JP 2019057590 A JP2019057590 A JP 2019057590A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor element
- substrate
- element mounting
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 217
- 239000000758 substrate Substances 0.000 title claims abstract description 209
- 238000004519 manufacturing process Methods 0.000 title claims description 64
- 239000011347 resin Substances 0.000 claims abstract description 340
- 229920005989 resin Polymers 0.000 claims abstract description 340
- 239000002184 metal Substances 0.000 claims abstract description 130
- 229910052751 metal Inorganic materials 0.000 claims abstract description 130
- 239000000945 filler Substances 0.000 claims abstract description 42
- 239000011888 foil Substances 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 38
- 238000007789 sealing Methods 0.000 claims description 21
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 238000012986 modification Methods 0.000 description 53
- 230000004048 modification Effects 0.000 description 53
- 239000000463 material Substances 0.000 description 24
- 238000010586 diagram Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 12
- 239000010949 copper Substances 0.000 description 11
- 238000005520 cutting process Methods 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000011159 matrix material Substances 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000007864 aqueous solution Substances 0.000 description 5
- 229960003280 cupric chloride Drugs 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 238000005422 blasting Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- -1 for example Substances 0.000 description 3
- 238000007788 roughening Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/16258—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4905—Shape
- H01L2224/49051—Connectors having different shapes
- H01L2224/49052—Different loop heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
[半導体素子用基板の構造]
図1は、第1の実施の形態に係る半導体素子用基板を例示する平面図である。図1を参照するに、半導体素子用基板1は、平面視略矩形状の基板フレーム10に、複数の単位基板群20が離間して配列された構造を有している。
次に、第1の実施の形態に係る半導体素子用基板の製造方法について、単位基板30を図示しながら説明する。図4〜図6は、第1の実施の形態に係る半導体素子用基板の製造工程を例示する図であり、図2(b)に対応する断面を示している。
第1の実施の形態の変形例1では、下面側に金属箔を備えた半導体素子用基板の例を示す。なお、第1の実施の形態の変形例1において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第1の実施の形態の変形例2では、他の樹脂部を備えた半導体素子用基板の例を示す。なお、第1の実施の形態の変形例2において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第1の実施の形態の変形例3では、ダイパッドの上面に多数の金属膜が形成された半導体素子用基板の例を示す。なお、第1の実施の形態の変形例3において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第1の実施の形態の変形例4では、ダイパッドやサポートバーを有していない半導体素子用基板の例を示す。なお、第1の実施の形態の変形例4において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第1の実施の形態の変形例5では、枠部及びサポートバーを有していない半導体素子用基板の例を示す。なお、第1の実施の形態の変形例5において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第1の実施の形態の変形例6では、枠部及びサポートバーを有していない半導体素子用基板の他の例を示す。なお、第1の実施の形態の変形例6において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
2、2A、2B、2C、2D、2E、2F 半導体装置
10 基板フレーム
10A 板材
10x スリット
10y 凹部
20 単位基板群
30、30A、30B、30C、30D、30E、30F 単位基板
31 ダイパッド
32 リード
33、37 樹脂部
34、34A、35、36 金属膜
38 枠部
39 サポートバー
40 半導体素子
41 電極端子
50 接着材
60 金属線
70 封止樹脂
80 はんだバンプ
311、321 切り欠き部
331 第1樹脂
332 第2樹脂
371 第3樹脂
372 第4樹脂
400、450 金属箔
Claims (13)
- 一方の面、他方の面、及び側面を備えた端子部と、
前記端子部の一方の面を露出し、側面を被覆する樹脂部と、を有し、
前記樹脂部は、第1樹脂と第2樹脂を備えた多層構造であり、
前記第1樹脂が、前記端子部の側面に接して設けられ、
前記第1樹脂及び前記第2樹脂はフィラーを含有し、
前記第1樹脂が含有するフィラーの量は、前記第2樹脂が含有するフィラーの量よりも少ない半導体素子用基板。 - 半導体素子を搭載する一方の面及び前記一方の面の反対面である他方の面を備え、外周部の前記他方の面側に第1切り欠き部が設けられた半導体素子搭載部を有し、
前記端子部は、前記半導体素子搭載部と離間して配置され、前記半導体素子搭載部側の端部の前記他方の面側に第2切り欠き部が設けられ、
前記樹脂部は、前記半導体素子搭載部の一方の面及び前記端子部の一方の面を露出した状態で前記半導体素子搭載部及び前記端子部を保持し、前記第1切り欠き部及び前記第2切り欠き部を埋めており、
前記第1樹脂は、前記第1切り欠き部の内壁面及び前記第2切り欠き部の内壁面と接して配置されている請求項1に記載の半導体素子用基板。 - 前記第1樹脂は、前記第1切り欠き部内から前記半導体素子搭載部の側面の一部に延伸して前記半導体素子搭載部の側面の一部を直接被覆すると共に、前記第2切り欠き部内から前記端子部の側面の一部に延伸して前記端子部の側面の一部を直接被覆し、
前記第2樹脂は、前記第1切り欠き部内から前記半導体素子搭載部の側面の一部を直接被覆する前記第1樹脂上に延伸すると共に、前記第2切り欠き部内から前記端子部の側面の一部を直接被覆する前記第1樹脂上に延伸する請求項2に記載の半導体素子用基板。 - 前記半導体素子搭載部の一方の面側及び前記端子部の一方の面側は、前記樹脂部の一方の面から突起し、
前記半導体素子搭載部及び前記端子部が形成されていない領域を埋めるように前記樹脂部の一方の面に設けられた他の樹脂部を有し、
前記他の樹脂部は、第3樹脂と第4樹脂とを備えた多層構造であり、
前記第3樹脂は、前記樹脂部から露出する前記半導体素子搭載部の側面、前記樹脂部から露出する前記端子部の側面、前記樹脂部から露出する前記端子部の前記半導体素子搭載部と対向する端面、及び前記第1樹脂の一方の面と接して配置され、
前記第4樹脂は、前記樹脂部から露出する前記半導体素子搭載部の側面、前記樹脂部から露出する前記端子部の側面、前記樹脂部から露出する前記端子部の前記半導体素子搭載部と対向する端面、及び前記第1樹脂の一方の面との間に前記第3樹脂を挟んで配置され、
前記第3樹脂及び前記第4樹脂はフィラーを含有し、
前記第3樹脂が含有するフィラーの量は、前記第4樹脂が含有するフィラーの量よりも少ない請求項3に記載の半導体素子用基板。 - 前記樹脂部は、前記半導体素子搭載部の他方の面及び前記端子部の他方の面を露出している請求項2乃至4の何れか一項に記載の半導体素子用基板。
- 前記第2樹脂は金属箔又は支持フィルム上に形成され、前記第1樹脂は前記第2樹脂上に形成され、
前記第1樹脂は、前記第1切り欠き部内から前記半導体素子搭載部の他方の面に延伸して前記半導体素子搭載部の他方の面を直接被覆すると共に、前記第2切り欠き部内から前記端子部の他方の面に延伸して前記端子部の他方の面を直接被覆し、
前記第2樹脂は、前記第1切り欠き部内から前記半導体素子搭載部の他方の面を直接被覆する前記第1樹脂上に延伸すると共に、前記第2切り欠き部内から前記端子部の他方の面を直接被覆する前記第1樹脂上に延伸する請求項2乃至4の何れか一項に記載の半導体素子用基板。 - 請求項1乃至6の何れか一項に記載に半導体素子用基板と、
前記半導体素子用基板の一方の面に搭載された半導体素子と、を有し、
前記半導体素子が前記端子部と電気的に接続された半導体装置。 - 一方の面及び前記一方の面の反対面である他方の面を備えた金属板を準備し、前記金属板をハーフエッチングして前記他方の面から前記一方の面側に窪む凹部を形成する工程と、
半硬化状態の第2樹脂及び第1樹脂を備えた多層構造の樹脂部を準備し、前記樹脂部を前記第1樹脂が前記金属板の前記他方の面と対向するように配置し、前記樹脂部を前記金属板の前記他方の面に貼り付けると共に前記凹部を前記樹脂部で埋める工程と、
前記樹脂部を硬化させた後、前記金属板の前記凹部の底部をなす領域を部分的に除去し、一方の面、他方の面、及び側面を備えた端子部を形成する工程と、を有し、
前記端子部を形成する工程では、前記端子部の一方の面は前記樹脂部から露出し、前記端子部の側面は前記樹脂部に被覆され、前記第1樹脂が前記端子部の側面に接して設けられ、
前記第1樹脂及び前記第2樹脂はフィラーを含有し、前記第1樹脂が含有するフィラーの量は、前記第2樹脂が含有するフィラーの量よりも少ない半導体素子用基板の製造方法。 - 前記樹脂部は、金属箔又は支持フィルム上に順次積層された半硬化状態の前記第2樹脂及び前記第1樹脂を備えている請求項8に記載の半導体素子用基板の製造方法。
- 前記端子部を形成する工程では、前記端子部と共に半導体素子搭載部が形成され、
前記半導体素子搭載部の外周部の前記他方の面側に前記凹部が分離された第1切り欠き部が設けられると共に、前記端子部の前記半導体素子搭載部の外周部側の端部の前記他方の面側に前記凹部が分離された第2切り欠き部が設けられる請求項8又は9に記載の半導体素子用基板の製造方法。 - 半硬化状態の第4樹脂及び第3樹脂を備えた多層構造の他の樹脂部を準備し、前記他の樹脂部を前記第3樹脂が前記半導体素子搭載部の一方の面及び前記端子部の一方の面と対向するように配置し、前記他の樹脂部を前記半導体素子搭載部の一方の面及び前記端子部の一方の面に貼り付けると共に前記他の樹脂部で前記樹脂部上の前記半導体素子搭載部及び前記端子部が形成されていない領域を埋める工程と、
前記半導体素子搭載部の一方の面及び前記端子部の一方の面よりも上側に形成された前記他の樹脂部を除去し、前記半導体素子搭載部の一方の面及び前記端子部の一方の面を露出する工程と、を有する請求項10に記載の半導体素子用基板の製造方法。 - 前記半導体素子搭載部及び前記端子部を形成する工程の後に、前記半導体素子搭載部の他方の面及び前記端子部の他方の面よりも下側に形成された前記樹脂部を除去し、前記半導体素子搭載部の他方の面及び前記端子部の他方の面を露出する工程を有する請求項10又は11に記載の半導体素子用基板の製造方法。
- 請求項8乃至12の何れか一項に記載の半導体素子用基板の製造方法により半導体素子用基板を作製する工程と、
前記半導体素子用基板の一方の面に半導体素子を搭載する工程と、
前記半導体素子用基板の一方の面に、前記半導体素子を封止する封止樹脂を形成する工程と、
前記端子部の他方の面よりも下側に形成された前記樹脂部を除去し、前記端子部の他方の面を露出する工程と、を有する半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017180608A JP6964477B2 (ja) | 2017-09-20 | 2017-09-20 | 半導体素子用基板及びその製造方法、半導体装置及びその製造方法 |
US16/051,878 US10943857B2 (en) | 2017-09-20 | 2018-08-01 | Substrate with multi-layer resin structure and semiconductor device including the substrate |
TW107132390A TWI801417B (zh) | 2017-09-20 | 2018-09-14 | 半導體元件用基板及其製造方法、半導體裝置及其製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017180608A JP6964477B2 (ja) | 2017-09-20 | 2017-09-20 | 半導体素子用基板及びその製造方法、半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019057590A true JP2019057590A (ja) | 2019-04-11 |
JP6964477B2 JP6964477B2 (ja) | 2021-11-10 |
Family
ID=65720563
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017180608A Active JP6964477B2 (ja) | 2017-09-20 | 2017-09-20 | 半導体素子用基板及びその製造方法、半導体装置及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10943857B2 (ja) |
JP (1) | JP6964477B2 (ja) |
TW (1) | TWI801417B (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021150462A (ja) * | 2020-03-18 | 2021-09-27 | 大日本印刷株式会社 | リードフレーム、リードフレームの製造方法及び半導体装置の製造方法 |
JP2021158211A (ja) * | 2020-03-26 | 2021-10-07 | 大日本印刷株式会社 | リードフレーム及びその製造方法、並びに半導体装置及びその製造方法 |
JP7548871B2 (ja) | 2021-05-31 | 2024-09-10 | Towa株式会社 | 成形型、樹脂成形装置及び樹脂成形品の製造方法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6709313B1 (ja) * | 2019-05-31 | 2020-06-10 | アオイ電子株式会社 | 半導体装置および半導体装置の製造方法 |
JP7467214B2 (ja) * | 2020-04-22 | 2024-04-15 | 新光電気工業株式会社 | 配線基板、電子装置及び配線基板の製造方法 |
KR102531701B1 (ko) * | 2021-06-21 | 2023-05-12 | 해성디에스 주식회사 | 프리 몰드 기판 및 프리 몰드 기판의 제조 방법 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001203313A (ja) * | 1999-11-09 | 2001-07-27 | Matsushita Electric Ind Co Ltd | 熱伝導基板およびその製造方法 |
JP2003124423A (ja) * | 2001-10-10 | 2003-04-25 | Shinko Electric Ind Co Ltd | リードフレーム及びその製造方法 |
JP2004071801A (ja) * | 2002-08-06 | 2004-03-04 | Shinko Electric Ind Co Ltd | リードフレーム及びその製造方法 |
JP2012164877A (ja) * | 2011-02-08 | 2012-08-30 | Shinko Electric Ind Co Ltd | リードフレーム、リードフレームの製造方法、半導体装置及び半導体装置の製造方法 |
JP2015008261A (ja) * | 2013-05-28 | 2015-01-15 | 京セラサーキットソリューションズ株式会社 | 配線基板およびその製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002026198A (ja) * | 2000-07-04 | 2002-01-25 | Nec Corp | 半導体装置及びその製造方法 |
JP3683179B2 (ja) * | 2000-12-26 | 2005-08-17 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP4390541B2 (ja) * | 2003-02-03 | 2009-12-24 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP5526575B2 (ja) | 2009-03-30 | 2014-06-18 | 凸版印刷株式会社 | 半導体素子用基板の製造方法および半導体装置 |
JP5250524B2 (ja) * | 2009-10-14 | 2013-07-31 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP6392654B2 (ja) * | 2014-02-04 | 2018-09-19 | エイブリック株式会社 | 光センサ装置 |
US10546808B2 (en) * | 2014-03-07 | 2020-01-28 | Bridge Semiconductor Corp. | Methods of making wiring substrate for stackable semiconductor assembly and making stackable semiconductor assembly |
KR101706470B1 (ko) * | 2015-09-08 | 2017-02-14 | 앰코 테크놀로지 코리아 주식회사 | 표면 마감층을 갖는 반도체 디바이스 및 그 제조 방법 |
-
2017
- 2017-09-20 JP JP2017180608A patent/JP6964477B2/ja active Active
-
2018
- 2018-08-01 US US16/051,878 patent/US10943857B2/en active Active
- 2018-09-14 TW TW107132390A patent/TWI801417B/zh active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001203313A (ja) * | 1999-11-09 | 2001-07-27 | Matsushita Electric Ind Co Ltd | 熱伝導基板およびその製造方法 |
JP2003124423A (ja) * | 2001-10-10 | 2003-04-25 | Shinko Electric Ind Co Ltd | リードフレーム及びその製造方法 |
JP2004071801A (ja) * | 2002-08-06 | 2004-03-04 | Shinko Electric Ind Co Ltd | リードフレーム及びその製造方法 |
JP2012164877A (ja) * | 2011-02-08 | 2012-08-30 | Shinko Electric Ind Co Ltd | リードフレーム、リードフレームの製造方法、半導体装置及び半導体装置の製造方法 |
JP2015008261A (ja) * | 2013-05-28 | 2015-01-15 | 京セラサーキットソリューションズ株式会社 | 配線基板およびその製造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021150462A (ja) * | 2020-03-18 | 2021-09-27 | 大日本印刷株式会社 | リードフレーム、リードフレームの製造方法及び半導体装置の製造方法 |
JP7510612B2 (ja) | 2020-03-18 | 2024-07-04 | 大日本印刷株式会社 | リードフレーム、リードフレームの製造方法及び半導体装置の製造方法 |
JP2021158211A (ja) * | 2020-03-26 | 2021-10-07 | 大日本印刷株式会社 | リードフレーム及びその製造方法、並びに半導体装置及びその製造方法 |
JP7468056B2 (ja) | 2020-03-26 | 2024-04-16 | 大日本印刷株式会社 | リードフレーム及びその製造方法、並びに半導体装置及びその製造方法 |
JP7548871B2 (ja) | 2021-05-31 | 2024-09-10 | Towa株式会社 | 成形型、樹脂成形装置及び樹脂成形品の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI801417B (zh) | 2023-05-11 |
US20190088578A1 (en) | 2019-03-21 |
TW201916293A (zh) | 2019-04-16 |
JP6964477B2 (ja) | 2021-11-10 |
US10943857B2 (en) | 2021-03-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6964477B2 (ja) | 半導体素子用基板及びその製造方法、半導体装置及びその製造方法 | |
US9040361B2 (en) | Chip scale package with electronic component received in encapsulant, and fabrication method thereof | |
JP3945483B2 (ja) | 半導体装置の製造方法 | |
US20050206014A1 (en) | Semiconductor device and method of manufacturing the same | |
JPH1154658A (ja) | 半導体装置及びその製造方法並びにフレーム構造体 | |
JP5406572B2 (ja) | 電子部品内蔵配線基板及びその製造方法 | |
TW201405745A (zh) | 晶片封裝基板、晶片封裝結構及其製作方法 | |
US20040101995A1 (en) | Method for manufacturing circuit devices | |
JP2013069807A (ja) | 半導体パッケージ及びその製造方法 | |
US20080174005A1 (en) | Electronic device and method for manufacturing electronic device | |
JP4446772B2 (ja) | 回路装置およびその製造方法 | |
JP2004119727A (ja) | 回路装置の製造方法 | |
JP5734624B2 (ja) | 半導体パッケージの製造方法 | |
JP2009272512A (ja) | 半導体装置の製造方法 | |
CN105304580B (zh) | 半导体装置及其制造方法 | |
JP2004119729A (ja) | 回路装置の製造方法 | |
JP4086607B2 (ja) | 回路装置の製造方法 | |
JP3925503B2 (ja) | 半導体装置 | |
JP2007048911A (ja) | 半導体装置、半導体装置の製造方法およびその製造方法に用いるシート | |
JP2008288481A (ja) | 半導体装置およびその製造方法 | |
JP2009246404A (ja) | 半導体装置の製造方法 | |
KR101324223B1 (ko) | 리드 프레임의 제조방법 | |
JP4663172B2 (ja) | 半導体装置の製造方法 | |
JP4442181B2 (ja) | 半導体装置およびその製造方法 | |
US20090309208A1 (en) | Semiconductor device and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20200521 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20210316 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20210318 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20210428 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20211005 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20211019 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6964477 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |