JP5271949B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5271949B2 JP5271949B2 JP2010072233A JP2010072233A JP5271949B2 JP 5271949 B2 JP5271949 B2 JP 5271949B2 JP 2010072233 A JP2010072233 A JP 2010072233A JP 2010072233 A JP2010072233 A JP 2010072233A JP 5271949 B2 JP5271949 B2 JP 5271949B2
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- semiconductor device
- sealing body
- lead terminals
- semiconductor
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Description
図1は本発明の実施の形態1の半導体装置の構造の一例を示す平面図、図2は図1に示す半導体装置のAから眺めた構造の一例を示す側面図、図3は図1に示す半導体装置のBから眺めた構造の一例を示す側面図、図4は図1に示す半導体装置の裏面側の構造の一例を示す裏面図である。また、図5は図1に示す半導体装置の構造の一例を封止体と半導体チップを透過して示す平面図、図6は図5のA−A線に沿って切断した構造の一例を示す断面図、図7は図5のB−B線に沿って切断した構造の一例を示す断面図、図8は図1に示す半導体装置のリード端子におけるハーフエッチング領域の一例を示す平面図、図9は図1に示す半導体装置のフリップチップ接続部の構造の一例を示す拡大部分断面図である。さらに、図10は図1に示す半導体装置に搭載された半導体チップにおけるピン機能の一例を示す平面図、図11は図1に示す半導体装置に搭載された変形例の半導体チップにおけるピン機能を示す平面図である。
主面4aと、この主面4aとは反対側の裏面4bと、を備えた封止体4とを有している。
子2それぞれの第1下面2cが、本実施の形態1の半導体装置の外部端子となっている。
図12は本発明の実施の形態2の半導体装置の構造の一例を示す平面図、図13は図12に示す半導体装置のAから眺めた構造の一例を示す側面図、図14は図12に示す半導体装置のBから眺めた構造の一例を示す側面図、図15は図12に示す半導体装置の裏面側の構造の一例を示す裏面図、図16は図12に示す半導体装置の構造の一例を封止体と半導体チップを透過して示す平面図である。また、図17は図16のA−A線に沿って切断した構造の一例を示す断面図、図18は図16のB−B線に沿って切断した構造の一例を示す断面図、図19は図12に示す半導体装置のリード端子におけるハーフエッチング領域の一例を示す平面図、図20は図12に示す半導体装置の実装構造の一例を示す側面図、図21は図20に示す半導体装置の実装構造の一例を示す断面図である。
図22は本発明の実施の形態3の半導体装置の組み立て手順の一例を示す製造フロー図、図23は図22の半導体装置の組み立てにおけるスタッドバンプボンディング後の構造の一例を示す平面図、図24は図22の半導体装置の組み立てにおけるウェハダイシング後の構造の一例を示す平面図、図25は図22の半導体装置の組み立てにおけるフレームテープ貼付け後の構造の一例を示す平面図である。また、図26は図25のA−A線に沿って切断した構造の一例を示す断面図、図27は図22の半導体装置の組み立てにおけるフリップチップボンディング後の構造の一例を示す平面図、図28は図27のA−A線に沿って切断した構造の一例を示す断面図、図29は図22の半導体装置の組み立てにおけるレジンモールド後の構造の一例を示す平面図、図30は図29のA−A線に沿って切断した構造の一例を示す断面図である。さらに、図31は図22の半導体装置の組み立てにおけるテープ剥離後の構造の一例を示す平面図、図32は図31のA−A線に沿って切断した構造の一例を示す断面図、図33は図22の半導体装置の組み立てにおけるPKGダイシング時の状態の一例を示す斜視図、図34は図33に示すPKGダイシング時の詳細構造の一例を示す断面図、図35は図34に示すPKGダイシング後の構造の一例を示す平面図である。また、図36は図22の半導体装置の組み立てにおけるテスト及びテーピング後の構造の一例を示す平面図、図37は図36のA−A線に沿って切断した構造の一例を示す断面図である。
)によって形成された一括封止体14をベーク処理し、封止用樹脂の硬化を促進させる。
図43は本発明の実施の形態4の半導体装置の構造の一例を示す平面図、図44は図43に示す半導体装置のAから眺めた構造の一例を示す側面図、図45は図43に示す半導体装置のBから眺めた構造の一例を示す側面図、図46は図43に示す半導体装置の裏面側の構造の一例を示す裏面図である。また、図47は図43に示す半導体装置の構造の一例を封止体と半導体チップを透過して示す平面図、図48は図47のA−A線に沿って切断した構造の一例を示す断面図、図49は図47のB−B線に沿って切断した構造の一例を示す断面図である。
図57は本発明の実施の形態5の半導体装置の裏面側の構造の一例を示す裏面図、図58は図57のA−A線に沿って切断した構造の一例を示す断面図、図59は図57のB−B線に沿って切断した構造の一例を示す断面図である。
端子2それぞれの第1下面2cが本実施の形態5の半導体装置の外部端子となっている。
実施の形態1〜5まで、エッチングフレームを用いて組み立てられる樹脂封止形の小型の半導体装置について説明してきたが、本実施の形態6では電鋳フレームを用いて組み立てられる半導体装置について説明する。
図77は本発明の実施の形態7の半導体装置の構造の一例を示す平面図、図78は図77に示す半導体装置のAから眺めた構造の一例を示す側面図、図79は図77に示す半導体装置のBから眺めた構造の一例を示す側面図、図80は図77に示す半導体装置の裏面側の構造の一例を示す裏面図である。また、図81は図77に示す半導体装置の構造の一例を封止体と半導体チップを透過して示す平面図、図82は図81のA−A線に沿って切断した構造の一例を示す断面図、図83は図81のB−B線に沿って切断した構造の一例を示す断面図、図84は図77に示す半導体装置のリード端子におけるハーフエッチング領域の一例を示す平面図である。
1a 主面
1b 裏面
1c 電極パッド(端子)
2 リード端子
2a 上面
2b 下面
2c 第1下面
2d 第2下面
2e 側面
2f 第1側面
2g 第2側面
2h ハーフエッチング部
2i オーバーハング部
2j 第1辺(側面側第1辺)
2k 第1辺(下面側第1辺)
2m,2n 端部
2p 基部
2q R形状
2r 切り欠き部
2s 第2辺
2t 第2辺
4 封止体
4a 主面
4b 裏面
4c 側面
4d 第1側面
4e 第2側面
5 金バンプ(バンプ、スタッドバンプ)
5a チャンファ部
5b 台座
5c 金ワイヤ部
5d 金ボール(ボール)
6 半導体パッケージ(半導体装置)
7 半導体チップ
7a 主面
7c 電極パッド(端子)
8 半導体パッケージ(半導体装置)
9 半田フィレット
10 実装基板
11 半導体ウェハ
11a チップ領域
12 リードフレーム
13 フレームテープ
14 一括封止体
15 ウェハリング
16 ダイシングテープ
17 ダイシングブレード
18 キャピラリ
18a インサイドチャンファ(ボール保管部)
19 SON(半導体装置)
20 QFN(半導体装置)
21 半導体パッケージ(半導体装置)
22 ワイヤ
51 半導体装置
52 半導体チップ
52a 主面
52b 電極パッド(端子)
53 ダイパッド
54 リード(リード端子)
55 ワイヤ
56 キャピラリ
56a インサイドチャンファ
57 金バンプ
57a チャンファ部
57b 台座
58 SUS
59 レジスト
60 フィルムマスク
61 保護フィルム
62 Auめっき
63 Niめっき
64 Agめっき
65 半導体パッケージ(半導体装置)
66 紫外線
67,68,69 半導体パッケージ(半導体装置)
Claims (10)
- 複数の電極パッドが形成された主面を備えた半導体チップと、
前記半導体チップが搭載された上面と、前記上面とは反対側の下面と、を備え、前記半導体チップの前記複数の電極パッドとそれぞれ電気的に接続された複数のリード端子と、
上面、前記上面とは反対側の下面、前記上面と下面とに連なる第1側面、および前記上面と前記下面とに連なり、前記第1側面と交差する第2側面を備え、前記半導体チップおよび前記複数のリード端子のそれぞれの一部を封止する封止体と、を有し、
前記複数のリード端子のそれぞれの前記下面は、前記封止体の前記下面から露出する第1下面と、前記複数のリード端子のそれぞれの前記上面と前記第1下面との間に位置し、前記封止体内に配置された第2下面と、を有し、
さらに、前記複数のリード端子のそれぞれは、前記上面と前記第1下面とに連なる第1側面と、前記上面と前記第2下面とに連なる第2側面と、を有し、
平面視において、前記複数のリード端子それぞれの前記第1下面間の距離は、前記上面間の距離よりも長く、
前記封止体の前記第1側面および前記下面において、前記複数のリード端子のそれぞれの前記第1側面と前記第1下面とは繋がった状態で露出し、
前記複数のリード端子のそれぞれの前記第2側面の一部は、前記封止体の前記第2側面から露出している半導体装置。 - 請求項1に記載の半導体装置において、
前記封止体の前記第2側面において、前記複数のリード端子のそれぞれの前記第2側面の周囲は、前記封止体により囲まれている半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のリード端子のそれぞれの前記第2下面は、ハーフエッチング加工によって形成されている半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のリード端子のそれぞれの前記第2側面間の距離は、前記上面間の距離と同等以上である半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体チップの前記複数の電極パッドと、前記複数のリード端子の前記上面のそれぞれとが、バンプを介して電気的に接続されている半導体装置。 - 請求項5に記載の半導体装置において、
前記バンプの主材料は金である半導体装置。 - 請求項6に記載の半導体装置において、
前記複数のリード端子のそれぞれの前記上面には、全面パラジウム(Pd)メッキが施されている半導体装置。 - 請求項5に記載の半導体装置において、
前記半導体チップの前記主面と前記複数のリード端子のそれぞれの前記上面との間の距離は20μm以上である半導体装置。 - 請求項8に記載の半導体装置において、
前記半導体チップの前記主面と前記複数のリード端子のそれぞれの前記上面との間に、前記封止体の一部が充填されている半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のリード端子のそれぞれの前記第1下面間の距離、および前記上面間の距離は、前記複数のリード端子の配列方向に沿った方向における距離である半導体装置。
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