JP5946511B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5946511B2 JP5946511B2 JP2014243182A JP2014243182A JP5946511B2 JP 5946511 B2 JP5946511 B2 JP 5946511B2 JP 2014243182 A JP2014243182 A JP 2014243182A JP 2014243182 A JP2014243182 A JP 2014243182A JP 5946511 B2 JP5946511 B2 JP 5946511B2
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Description
図1は本発明の実施の形態1の半導体装置の構造の一例を示す平面図、図2は図1に示す半導体装置のAから眺めた構造の一例を示す側面図、図3は図1に示す半導体装置のBから眺めた構造の一例を示す側面図、図4は図1に示す半導体装置の裏面側の構造の一例を示す裏面図である。また、図5は図1に示す半導体装置の構造の一例を封止体と半導体チップを透過して示す平面図、図6は図5のA−A線に沿って切断した構造の一例を示す断面図、図7は図5のB−B線に沿って切断した構造の一例を示す断面図、図8は図1に示す半導体装置のリード端子におけるハーフエッチング領域の一例を示す平面図、図9は図1に示す半導体装置のフリップチップ接続部の構造の一例を示す拡大部分断面図である。さらに、図10は図1に示す半導体装置に搭載された半導体チップにおけるピン機能の一例を示す平面図、図11は図1に示す半導体装置に搭載された変形例の半導体チップにおけるピン機能を示す平面図である。
主面4aと、この主面4aとは反対側の裏面4bと、を備えた封止体4とを有している。
子2それぞれの第1下面2cが、本実施の形態1の半導体装置の外部端子となっている。
図12は本発明の実施の形態2の半導体装置の構造の一例を示す平面図、図13は図12に示す半導体装置のAから眺めた構造の一例を示す側面図、図14は図12に示す半導体装置のBから眺めた構造の一例を示す側面図、図15は図12に示す半導体装置の裏面側の構造の一例を示す裏面図、図16は図12に示す半導体装置の構造の一例を封止体と半導体チップを透過して示す平面図である。また、図17は図16のA−A線に沿って切断した構造の一例を示す断面図、図18は図16のB−B線に沿って切断した構造の一例を示す断面図、図19は図12に示す半導体装置のリード端子におけるハーフエッチング領域の一例を示す平面図、図20は図12に示す半導体装置の実装構造の一例を示す側面図、図21は図20に示す半導体装置の実装構造の一例を示す断面図である。
図22は本発明の実施の形態3の半導体装置の組み立て手順の一例を示す製造フロー図、図23は図22の半導体装置の組み立てにおけるスタッドバンプボンディング後の構造の一例を示す平面図、図24は図22の半導体装置の組み立てにおけるウェハダイシング後の構造の一例を示す平面図、図25は図22の半導体装置の組み立てにおけるフレームテープ貼付け後の構造の一例を示す平面図である。また、図26は図25のA−A線に沿って切断した構造の一例を示す断面図、図27は図22の半導体装置の組み立てにおけるフリップチップボンディング後の構造の一例を示す平面図、図28は図27のA−A線に沿って切断した構造の一例を示す断面図、図29は図22の半導体装置の組み立てにおけるレジンモールド後の構造の一例を示す平面図、図30は図29のA−A線に沿って切断した構造の一例を示す断面図である。さらに、図31は図22の半導体装置の組み立てにおけるテープ剥離後の構造の一例を示す平面図、図32は図31のA−A線に沿って切断した構造の一例を示す断面図、図33は図22の半導体装置の組み立てにおけるPKGダイシング時の状態の一例を示す斜視図、図34は図33に示すPKGダイシング時の詳細構造の一例を示す断面図、図35は図34に示すPKGダイシング後の構造の一例を示す平面図である。また、図36は図22の半導体装置の組み立てにおけるテスト及びテーピング後の構造の一例を示す平面図、図37は図36のA−A線に沿って切断した構造の一例を示す断面図である。
)によって形成された一括封止体14をベーク処理し、封止用樹脂の硬化を促進させる。
図43は本発明の実施の形態4の半導体装置の構造の一例を示す平面図、図44は図43に示す半導体装置のAから眺めた構造の一例を示す側面図、図45は図43に示す半導体装置のBから眺めた構造の一例を示す側面図、図46は図43に示す半導体装置の裏面側の構造の一例を示す裏面図である。また、図47は図43に示す半導体装置の構造の一例を封止体と半導体チップを透過して示す平面図、図48は図47のA−A線に沿って切断した構造の一例を示す断面図、図49は図47のB−B線に沿って切断した構造の一例を示す断面図である。
図57は本発明の実施の形態5の半導体装置の裏面側の構造の一例を示す裏面図、図58は図57のA−A線に沿って切断した構造の一例を示す断面図、図59は図57のB−B線に沿って切断した構造の一例を示す断面図である。
端子2それぞれの第1下面2cが本実施の形態5の半導体装置の外部端子となっている。
実施の形態1〜5まで、エッチングフレームを用いて組み立てられる樹脂封止形の小型の半導体装置について説明してきたが、本実施の形態6では電鋳フレームを用いて組み立てられる半導体装置について説明する。
図77は本発明の実施の形態7の半導体装置の構造の一例を示す平面図、図78は図77に示す半導体装置のAから眺めた構造の一例を示す側面図、図79は図77に示す半導体装置のBから眺めた構造の一例を示す側面図、図80は図77に示す半導体装置の裏面側の構造の一例を示す裏面図である。また、図81は図77に示す半導体装置の構造の一例を封止体と半導体チップを透過して示す平面図、図82は図81のA−A線に沿って切断した構造の一例を示す断面図、図83は図81のB−B線に沿って切断した構造の一例を示す断面図、図84は図77に示す半導体装置のリード端子におけるハーフエッチング領域の一例を示す平面図である。
1a 主面
1b 裏面
1c 電極パッド(端子)
2 リード端子
2a 上面
2b 下面
2c 第1下面
2d 第2下面
2e 側面
2f 第1側面
2g 第2側面
2h ハーフエッチング部
2i オーバーハング部
2j 第1辺(側面側第1辺)
2k 第1辺(下面側第1辺)
2m,2n 端部
2p 基部
2q R形状
2r 切り欠き部
2s 第2辺
2t 第2辺
4 封止体
4a 主面
4b 裏面
4c 側面
4d 第1側面
4e 第2側面
5 金バンプ(バンプ、スタッドバンプ)
5a チャンファ部
5b 台座
5c 金ワイヤ部
5d 金ボール(ボール)
6 半導体パッケージ(半導体装置)
7 半導体チップ
7a 主面
7c 電極パッド(端子)
8 半導体パッケージ(半導体装置)
9 半田フィレット
10 実装基板
11 半導体ウェハ
11a チップ領域
12 リードフレーム
13 フレームテープ
14 一括封止体
15 ウェハリング
16 ダイシングテープ
17 ダイシングブレード
18 キャピラリ
18a インサイドチャンファ(ボール保管部)
19 SON(半導体装置)
20 QFN(半導体装置)
21 半導体パッケージ(半導体装置)
22 ワイヤ
51 半導体装置
52 半導体チップ
52a 主面
52b 電極パッド(端子)
53 ダイパッド
54 リード(リード端子)
55 ワイヤ
56 キャピラリ
56a インサイドチャンファ
57 金バンプ
57a チャンファ部
57b 台座
58 SUS
59 レジスト
60 フィルムマスク
61 保護フィルム
62 Auめっき
63 Niめっき
64 Agめっき
65 半導体パッケージ(半導体装置)
66 紫外線
67,68,69 半導体パッケージ(半導体装置)
Claims (9)
- (a)電極パッドが形成された主面を有する半導体チップの前記電極パッドの表面上にスタッドバンプを形成する工程と、
(b)上面および前記上面とは反対側の下面を有するリード端子が形成された金属板を準備する工程と、
(c)前記リード端子の前記上面と、前記半導体チップの前記主面とが対向するように前記半導体チップを前記リード端子上に搭載し、前記半導体チップの前記電極パッドと前記リード端子とを前記スタッドバンプを介して電気的に接続する工程と、
(d)前記(c)工程の後、前記半導体チップの前記主面と前記リード端子の前記上面との間をモールドレジンで充填し、前記金属板の一部、前記半導体チップ、および前記リード端子の一部が封止されるように封止体を形成する工程と、
(e)前記(d)工程の後、前記リード端子および前記封止体を前記金属板から分離させて、前記リード端子の前記下面を前記封止体から露出させる工程と、
を有し、
前記(c)工程の後、
前記リード端子の前記上面と前記半導体チップの前記主面との間の距離は、前記リード端子の前記下面から前記リード端子の前記上面へ向かう第1方向において20μm以上になっており、
前記リード端子の前記下面と前記リード端子の前記上面との間の距離は、前記第1方向において前記リード端子の前記上面と前記半導体チップの前記主面の間の距離より大きくなっている、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(a)工程の後、かつ前記(c)工程の前において、前記スタッドバンプは、前記半導体チップの前記電極パッドに接続された台座部と、前記台座部上に形成されたチャンファ部と、を有し、
前記チャンファ部の厚さは、前記台座部の厚さよりも厚い、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記台座部と前記チャンファ部の厚さの合計は25μm以上になっている、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記チャンファ部の厚さは、前記台座部の厚さの1.5倍程度になっている、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記(c)工程の前記スタッドバンプと前記リード端子との接続は、超音波と熱とを併用して行い、
前記(c)工程の後、前記スタッドバンプの前記台座部は、前記電極パッドのパッド内に収まっており、
前記リード端子の前記上面の面積は、平面視において前記電極パッドの面積より大きい、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(b)工程において、前記金属板はステンレス鋼である、半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法において、
前記(e)工程の後、
前記下面の平面積は、前記上面の平面積より小さい、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(d)工程において、前記モールドレジンは、フィラーを含有し、
前記フィラーの径は、20μm未満である、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(d)工程において、前記モールドレジンは、フィラーを含有し、
前記フィラーの径の平均が、実質的に10μmである、半導体装置の製造方法。
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