CN1659698A - 包括半导体器件的四方扁平无引线封装 - Google Patents

包括半导体器件的四方扁平无引线封装 Download PDF

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Publication number
CN1659698A
CN1659698A CN03812887XA CN03812887A CN1659698A CN 1659698 A CN1659698 A CN 1659698A CN 03812887X A CN03812887X A CN 03812887XA CN 03812887 A CN03812887 A CN 03812887A CN 1659698 A CN1659698 A CN 1659698A
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China
Prior art keywords
welding disc
pipe core
core welding
bond pad
lead
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CN03812887XA
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English (en)
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B·罗尔莫泽
T·维斯
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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Publication of CN1659698A publication Critical patent/CN1659698A/zh
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Abstract

提出了一种半导体封装。该半导体封装包括在管芯焊盘上的分立的半导体芯片；位于芯片附近并由多个连接机构形成的多个接合焊盘，以及用于密封芯片和焊盘的密封剂。在优选实施例中，管芯焊盘和/或接合焊盘包括将焊盘垂直地和横向地互锁到密封剂的装置。接合焊盘和管芯焊盘的互锁装置显著地增强了焊盘与密封剂之间的接合强度，用于防止脱层或裂化，由此能够确保包括分立元件的四方扁平无引线半导体封装的质量和可靠性。

Description

包括半导体器件的四方扁平无引线封装
本发明主要涉及一种用于容纳半导体器件的四方扁平无引线的引线框封装结构。更具体地，本发明涉及一种用于容纳分立半导体器件的四方扁平无引线的引线框封装结构。
半导体封装产业中的一个主要趋势是使用表面安装技术(SMT)替代常规的电镀通孔(PTH)技术。SMT提供了优于PTH技术的几个明显的优点，例如更大的封装密度、具有较短的互连长度和更易自动化的更高引线数。由于SMT要求电子器件和元件能安装在印刷线路板的表面上，所以必须重新设计包括电容、电阻和电感的传统引线元件的材料和结构，以满足对短、薄、轻和小型电子器件的当今要求。
实现这些目标的半导体器件的实例包括“四方扁平无引线(QFN)”封装。四方扁平无引线的电子器件具有相对新的封装结构，其中消除了侧向突出于封装之外的耗费空间大的外部引线。代替地，在QFN封装的背面上提供电连接到主板的外部电极焊盘。
在芯片级封装(CSP)的形成中，四方扁平无引线封装，尤其是无引线的引线框封装(LLP)使用了金属引线框型基板结构。在典型的无引线的引线框封装中，通过压印或蚀刻来对铜引线框条或面板进行构图，以限定多个阵列的芯片基板特征。每个芯片基板特征都包括管芯贴附焊盘和设置在其相关管芯粘接焊盘周围的多个接触(接合)。
在装配过程中，将管芯贴附到各自的管芯贴附焊盘，并使用传统的引线接合将每个管芯电连接到引线框条上其相关的接合焊盘接触上。在引线接合工艺之后，在每个引线接合管芯阵列的顶表面上方塑模形成一个合成树脂盖帽。然后使用常规的切割和测试技术切单(singulate)并测试这些管芯。
然后使用常规技术可以将最终的封装芯片表面安装在印刷电路板或其它基板上。
应当理解，在切单过程中，将管芯焊盘和接合焊盘接点固定在适当位置的唯一材料是塑模材料。由于在切单密封剂的过程中缺乏足够的支撑或夹紧力，所以在切单过程中往往使管芯焊盘或引线错位。
US20020027273A1公开了一种半导体封装，其包括半导体芯片；围绕该芯片并用多个连接机构和加固结构形成的多条引线；以及用于密封芯片和引线的密封剂。引线具有与半导体封装相同的高度，并允许将引线的上表面和下表面暴露于密封剂的外部，并且还增强了工作中由芯片产生的热量耗散。引线的加固结构大大地增强了引线与密封剂之间的粘接强度，以防止脱层或裂化，由此能够确保半导体封装的质量和可靠性。
然而，上述无引线的引线框封装具有以下不足。该发明使用具有从引线框的框架向内延伸的多条引线的引线框，其中在其侧面上用加固结构形成引线，且连接机构在引线的内侧表面上。上述引线框结构不适合于例如单独封装的分立半导体器件的商品产品。
因此，本发明的一个目的是提供一种改进的四方扁平无引线的引线框半导体封装，尤其用于单独封装的分立半导体器件。
本发明的另一目的是提供一种四方扁平无引线的引线框半导体封装，用于改善封装时连接可靠性。
本发明的再一个目的是提供一种有助于工艺管理的四方扁平无引线的引线框半导体封装。
根据上述及其它目的，本发明中提出的四方扁平无引线半导体器件包括：
-分立半导体管芯；
-具有第一侧向表面用于支撑分立半导体管芯的管芯焊盘；以及
-垂直于第一侧向表面的多个垂直表面，具有第一侧向表面和垂直于该第一侧向表面的多个垂直表面的至少一个接合焊盘；
-用于将分立半导体管芯连接到接合焊盘的至少一条接合引线；以及
-用于密封管芯、管芯焊盘、接合引线和具有侧向和垂直外表面的接合焊盘的密封剂，其中将管芯焊盘设置在密封剂的周围、并部分地暴露于密封剂的一个垂直外表面。
在本发明的一个实施例中，管芯焊盘的垂直表面提供有互锁装置。
在本发明的优选实施例中，管芯焊盘的垂直表面提供有垂直地和侧向地互锁管芯焊盘的装置。
在本发明的另一优选实施例中，至少一个管芯焊盘的第一和第二垂直表面提供有互锁装置。
在本发明例的另一实施例中，接合焊盘的垂直表面提供有互锁装置。
从下面详细的说明和附图中，本领域的技术人员可以明白本发明的这些和其它特征及优点。
图1显示用于制造包括分立半导体器件的QFN封装而进行的工艺步骤的两种选择。
图2是用于包括1944个分立件的QFN封装的引线框平面图。
图3是根据本发明实施例的管芯焊盘和接合焊盘的平面图。
图4示出了说明根据本发明一个实施例的管芯焊盘和接合焊盘的互锁装置的截面图。
图5是根据本发明一个实施例的QFN封装的透视图。
如图5中所示，四方扁平无引线半导体封装10，包括下列部件：
-半导体芯片11；
-具有基体的管芯焊盘12，其具有用于贴附芯片11的第一侧向表面12a、暴露于密封剂外侧用于外部电连接的第二侧向表面12b和垂直面12c，12d；
-与管芯焊盘12邻近设置并电连接到芯片11的两个接合焊盘13；以及
-用于密封芯片11、管芯焊盘12和接合焊盘13的密封剂19。每个接合焊盘13都具有第一侧向表面13a，暴露于密封剂19的外侧用于外部电连接、并且与管芯焊盘12b的第二侧向表面共平面的第二侧向表面13b。管芯焊盘的第二侧向表面和接合焊盘12b，13b可以用作用于电传输的I/O端，以便将半导体封装10电连接到例如外部印刷电路板(未显示)的基板。
该封装还包括多条接合引线14，每条接合引线连接在分立半导体管芯上的导电接触与接合焊盘的第一表面之间。
该封装还包括形成封装体的密封材料19。
该封装具有外围侧面和边缘的多面体形状。一个侧向外围表面包括管芯焊盘和接合焊盘的第二侧向表面。
该封装具有周界，且分立半导体器件放置在封装的周界处。管芯焊盘的至少一个垂直面至少部分地暴露于封装的外部表面。
图1中显示了制造四方扁平无引线的引线框封装的两种方法。为了制作四方扁平无引线的引线框封装，采用了金属引线框。上述金属框也可以包括覆盖层。多个管芯焊盘和接合焊盘存在于其内并连接到框架。将管芯贴附到各自的管芯贴附焊盘，并使用常规的引线接合将每个管芯电连接到引线框条上的其相关接合焊盘接触。在包括塑模和除去覆盖层的密封步骤之后，可以将管芯焊盘和引线进行电镀。其后，将管芯焊盘和接合焊盘从引线框中切断，并从引线框中锯下完整的封装。可以同时制造多个封装，例如几千个。
用于本发明的分立半导体器件优选是有源或无源的分立电子器件，例如结合在芯片(管芯)中的晶体管、二极管、LED、电阻器、电容器和电感。
管芯焊盘用于支撑存在于其上的分立半导体器件芯片(管芯)，并设置在密封剂的周界区域中。
上述管芯焊盘具有多面体形状的基体。基体的形状通常来自于立方体，并按如下来描述。然而，应当理解，立方体形状可能具有偏离于规则立方体形状的偏差，例如凹槽、沟槽和其它偏差。
管芯焊盘具有大致平坦的第一侧向表面12a，在封装组装过程中将管芯11置于其上。
与第一表面相对的是大致平坦的第二侧向表面12b，其相对于封装表面是处在外围的。管芯焊盘12的第二侧向表面位于与树脂密封剂19的下表面基本相同的平面内，并且没有被树脂密封剂覆盖而暴露出来。
此外，管芯焊盘包括多个垂直面，垂直地延伸到侧向表面。第一侧向表面12d相对于封装的表面是处在外围的。根据用于切单单个封装的切单技术，第一侧向表面12d可以整个地或部分地暴露于封装的外表面。例如，第一垂直侧面整体地面向密封剂的外表面，或者其具有指向密封剂的外表面的盖。
在本发明的优选实施例中，至少一个内部侧向表面提供有互锁装置，尤其是用于侧向地和垂直地互锁装置，用于安全地将管芯焊盘固定在密封剂中。优选地将互锁装置提供到第一侧向表面的背面。
上述互锁装置可以包括突起，该突起提供有在一个方向中具有凹角的表面。在一个方向中具有凹角的上述突起可以包括对于管芯焊盘的所有垂直面成悬臂的圆形盖。
在优选实施例中，上述互锁装置可以包括突起，这些突起提供有在至少两个方向中具有凹角的表面。
在至少两个方向中具有凹角的上述突起可以包括无限制或封闭的梯形、燕尾形、T形突起、锚形突起、号角形突起或者向外指向密封剂的内表面的盖。
突起不必是对称的——例如倒钩形的突起。
上述互锁突起可以具有阶梯式轮廊。
两个侧面上的突起可以一起工作，从而将管芯焊盘横向地和垂直地互锁到密封剂中。
图4和5说明具有形成为燕尾的互锁装置的管芯焊盘。
如上面所示，将管芯焊盘的内部背表面设置成像具有燕尾突起的悬臂边缘。
更具体地，管芯焊盘的突起向内突出，且管芯焊盘的第一侧向表面的面积大于其第二表面。在图4中，阴影区域表示器件区域，交叉影线区域表示管芯焊盘(和接合焊盘)的半蚀刻部分。
除了突起之外，还设计将沟槽作为互锁装置。这种沟槽围绕垂直表面，且可以为圆形、矩形或其它任何复杂的形状。
同样如图4和5中所示，例如，至少可以使用延伸主体周界边缘的全部长度或部分长度的纵向沟槽16。
同样，每个接合焊盘13提供有互锁装置，以缓冲引起脱层的力。
接合焊盘用于将分立半导体芯片器件(管芯)电连接到外部电极。
上述接合焊盘具有多面体形状的基体。基体形状通常源自于立方体，且如下进行描述。然而，应当理解，立方体形状可以具有例如凹槽、沟槽和其它偏离于规则立方体形状的偏差。
接合焊盘具有第一基本平坦的侧向表面13a，在封装组装过程中接合引线14置于其上。
与第一表面相对的是相对于封装表面处于外围的基本平坦的第二侧向表面13b。管芯焊盘12的第二侧向表面位于与树脂密封剂19的下表面基本相同的平面，且没有被树脂密封剂覆盖而暴露出来。
而且，接合焊盘包括垂直延伸到侧向表面的多个垂直面。第一侧向表面13d相对于封装的表面处于外围。根据用于切单单独封装的切单技术，将第一侧向表面13d整个或部分地暴露于封装的外部表面。例如，第一垂直侧面整体地面向密封剂的外部表面，或者其具有向外指向密封剂的外部表面的盖。
在本发明的优选实施例中，每个接合焊盘的至少一个内部侧向表面提供有互锁装置，尤其是用于将接合焊盘安全地固定到密封剂中的横向地和垂直地互锁的装置。优选地，将互锁装置提供到第一侧向表面的背面。
上述互锁装置可以包括突起，这些突起提供有在一个方向中具有凹角的表面。在一个方向中具有凹角的上述突起可以包括悬挂于接合焊盘的所有垂直面的圆形盖。
在优选实施例中，上述互锁装置可以包括突起，这些突起提供有在至少两个方向中具有凹角的表面。
在至少两个方向中具有凹角的上述突起可以包括末端开口或封闭的梯形、燕尾形、T形突起、锚形突起、号角形突起或者向外指向密封剂的内表面的盖。
突起不必是对称的，例如是倒钩形的突起。
上述互锁突起可以具有阶梯式轮廊。
两个侧面上的突起可以一起工作，从而将接合焊盘横向地和垂直地互锁到密封剂中。
图4和5说明具有形成为V角的两个垂直面上具有互锁装置的接合焊盘。
如上面所示，将接合焊盘的内部背表面设置成像具有V形突起的悬臂边缘。
更具体地，接合焊盘的突起向内突出，且每个接合焊盘的第一侧向表面的面积大于其第二表面。在图4中，阴影区域表示器件区域，交叉影线区域表示接合焊盘的半蚀刻部分。
除了突起之外，还设计将沟槽作为互锁装置。这种沟槽围绕垂直表面，且可以为圆形、矩形或其它任何复杂的形状。
同样如图4和5中所示，例如，至少可以使用延伸主体周界边缘的全部长度或部分长度的纵向沟槽16。
图3中所示的引线框20的突起(互锁装置)15的数量、位置和形状仅是示例性的。突起的数量、位置和形状将根据应用而变化。本发明的优点是可以将互锁装置设计为适应特殊分立半导体管芯的管芯焊盘和接合焊盘的数量和位置。
当在用粘合剂将半导体芯片接合并固定在管芯焊盘1的突起部分6之后，用树脂密封剂塑模半导体芯片时，在互锁装置15的底切处接收到树脂密封剂。因此，互锁装置的底切表面与密封剂的相应表面相互作用，用于将元件机械地固定在封装的相关次表面。由此，互锁装置防止了管芯焊盘和接合焊盘从封装体被垂直或横向地牵引，因而防止了对树脂塑模半导体器件可靠性的不利影响。
多个不同尺寸的分立半导体芯片管芯11可以封装在管芯焊盘上，例如通过沟槽来扩大半导体管芯11和管芯焊盘的接触区域，以改善半导体管芯2与管芯焊盘之间的接触，由此防止管芯焊盘和半导体芯片11分离。
可以通过胶粘工艺，将半导体管芯11接合到管芯焊盘的中心部分上。
其后，用极细的金属接合引线14将管芯11电连接到相关的接合焊盘13上。
接合引线通常由金形成。当结合铜基板使用金接合引线时，有利地使用银(或另外的材料)来电镀接触平台(landing)，以改善接合引线与平台的粘附性。
在所有的管芯被引线接合或者电连接到适当接触平台后，在基板面板20上方形成一个或多个塑料盖帽21，如图1中所示。在所述的实施例中，在器件区域23的所有器件上方形成分离的塑料盖帽。即，如图2a的虚线描绘的四个分离的盖帽。然而，应当理解，能够容易地提供单个盖帽或不同数量的盖帽。
在这种情况下，由于管芯焊盘和接合焊盘的底部没有覆盖树脂密封剂15，所以获得“单侧塑模结构”。
将管芯焊盘12、接合焊盘13、半导体芯片11和极细金属线14密封在树脂密封剂19内。然而，围绕封装外围的接合焊盘和管芯焊盘各自的下半部分向下和向侧突出到树脂密封剂19的下表面之外。这些焊盘的下半部分用作电连接到母板的外部电极(或外部端)。
下文中，将描述根据本发明由QFN封装的功能得到的效果。
本发明的封装具有许多优点，并用于包括功率器件的分立电子器件的多个应用中。可以将封装制作得尺寸很小。例如，封装可以接近芯片尺寸。另外，封装可以很薄。可以根据本发明制造具有低至约0.5mm或更小厚度的封装。另外，接合焊盘可以放置在管芯附近，以将接合引线的长度减小到最小，并提高电性能。管芯焊盘和接合焊盘的暴露的第二表面可以通过金属焊料连接到印刷电路板用于封装冷却。
在接合焊盘和管芯焊盘的旁边不存在外部引线。代替地，每条信号引线1的下半部分用作外部电极。因此，在不限制安装的半导体芯片的尺寸的条件下，上述结构有助于使功率QFN封装减小尺寸。而且，由于在外部电极的各个下表面上不存在树脂毛边，所以能够采用更可靠的方式将母板的电极接合到这些外部电极。
而且，由于焊盘的垂直面可以具有将焊盘横向和垂直地锁到密封剂上的互锁装置，所以在密封剂的加工过程中焊盘能够缓冲变形力。因此，能够防止管芯焊盘2和接合焊盘由于加工力而导致变形或移位。
本发明的另一优势是在不需要较大改变的条件下，可以使用为集成电路的四方扁平无引线封装而设计的工具。
下文中，将参照附图描述根据本发明的包括分立半导体器件的QFN封装的制造方法。图1、2和4说明根据第一实施例制造QFN封装的相关工艺。
图2A和2B示出了用于QFN制造的QFN矩阵引线框20的示意性平面图；图2C示出了在QFN矩阵引线框20上构建的一批未切单的封装单元的示意截面图。
首先参照图2，将描述根据本发明的一个实施例适合使用的无引线的引线框20。如这里所见，提具有多个段22的导电面板21，该多个段22每个都具有对于按多个行和多个列形成于其上的单独封装区域的多个器件区域23。在所示的实施例中，导电面板采取具有一维器件段阵列的引线框条的形式。然而，在可选的实施例中，可以提供具有多种不同形状和器件区域布局的导电面板。
如图4中所示，QFN矩阵引线框20预先定义有用于在其上制造一批QFN封装单元的封装位置矩阵23。通过沿封装位置23的边线形成的网格状连接装置24来将这些封装位置23彼此划界，并且每个都包括管芯焊盘12和多个接合焊盘13，其都连接到网格状连接条24，以便在切单之前固定在一起。
因此，能够由一个引线框制造包括分立半导体器件的大量QFN。
已经发现，在组装过程中将粘接带粘接到引线框条或面板101的底表面是有益的。在管芯贴附和引线接合操作过程中，粘接覆层带帮助支撑管芯焊盘和接合焊盘，且还防止了在塑模工艺中溢料(即，多余的塑料)形成在引线框条或面板20的下侧。
在引线框中包括互锁装置15以及锯坑和锯痕25的管芯焊盘和接合焊盘可以用适当的工艺形成。由于蚀刻将要在基板中形成槽而非有完全穿过基板面板20进行蚀刻，所以这有时称为半蚀刻或部分蚀刻工艺。使用各种常规的蚀刻技术将有助于该蚀刻工艺。
众所周知，化学蚀刻(也称化学铣削)是使用光刻、光致抗蚀剂、和溶解金属的液体化学制剂以将图案蚀刻成金属条的工艺。通常，将一层光致抗蚀剂涂覆到该条的一个或两个平坦表面。然后，通过具有所期望图案的掩模对抗蚀剂层进行曝光。接着显影并固化光致抗蚀剂，形成图案化的光致抗蚀剂掩模。接着，将化学制剂喷射或用其它方法涂覆到掩模条的一个或两个平坦表面。将条的暴露部分蚀刻掉，留下金属条中所期望的图案。
使用两步蚀刻工艺来形成图2和4的引线框20。第一蚀刻步骤根据涂覆到条的一个或两个平坦表面的抗蚀剂图案来蚀刻该条的一个或两个平坦表面。第一蚀刻步骤完全穿过金属条部分进行蚀刻，以形成引线框的整个图案，如图2所示。接着，在引线框一侧的部分上形成第二抗蚀剂图案。管芯焊盘、接合焊盘和锯槽的互锁装置没有被第二抗蚀剂图案覆盖，因此容易进一步地蚀刻。第二蚀刻步骤根据第二抗蚀剂图案从一侧部分地穿过引线框进行蚀刻。该第二蚀刻步骤形成引线框20的凹陷表面，例如管芯焊盘和接合焊盘的互锁装置，表示为交叉影线部分。锯槽通常也经历该第二蚀刻步骤。当化学制剂穿过所选择部分的厚度蚀刻了选择的距离时，停止第二蚀刻步骤。换句话说，第二蚀刻步骤部分地穿过管芯焊盘和接合焊盘所选部分的厚度进行蚀刻。根据需求控制第二蚀刻步骤中蚀刻掉的材料的量，以使足够量的密封材料在管芯焊盘和接合焊盘的互锁装置下方流动，从而将管芯焊盘和接合焊盘固定至封装体。典型地，第二蚀刻步骤移除管芯焊盘和接合焊盘大约50％的厚度，但总的移除量为管芯焊盘和接合焊盘大约33％至75％的厚度范围。由于蚀刻工艺中的不完整性，凹角可能不正交，而仅仅是大致正交，且管芯焊盘和接合焊盘的蚀刻侧壁可能不平坦，而是具有圆角。
在对引线框面板20构图之后，可选地，用有助于更好的引线接合的材料对其电镀。在该时间点或在塑模工艺步骤之后，可以用镍(Ni)、钯(Pd)和金(Au)的金属层对引线框20进行电镀。
在所述可选的管芯焊盘电镀之后，使用常规的管芯贴附技术将分立半导体管芯11安装在管芯焊盘12上。
在图1所示的工艺步骤2中，将半导体芯片4安装在引线框20的管芯焊盘的中央部分上，其是用含有环氧树脂的银胶作为粘合剂通过粘合而接合并制备的。该工艺步骤被称为“管芯接合”。
然后，在图1中所示的工艺步骤3中，用极细的金属引线或等效导体14，将分立半导体芯片11的电极焊盘(未示出)电连接到接合焊盘13。该工艺步骤称为“引线接合”。极细的金属引线14可以由适当选择的材料例如铝(Al)或金(Au)制成。
在将所有的管芯引线接合或用其它方法电连接到适当接触平面后，在如图2B中所示的基板面板20上方形成一个或多个塑料盖帽22。在所述的实施例中，在每个器件区域23的所有器件上方形成单独的塑料盖帽。即，如图2a的虚线中描绘的四个单独的盖帽。然而，应理解能够容易地提供单个盖帽或不同数量的盖帽。
在这种情况下，由于管芯焊盘和接合焊盘的底部没有覆盖树脂密封剂15，所以获得了“单侧塑模结构”。
可以使用包括转印塑模和注塑的任何常规塑模工艺形成盖帽22。在描述的实施例中，使用塑模的阵列型转印塑模工艺。
将树脂涂覆到区域22中的引线框的顶侧上方，以嵌入半导体芯片、焊盘和引线。防止了树脂迁移到引线框20的下侧。树脂迁移到凹口25中并在固化工艺中固化。因为凹口25的结构，抑制了固化树脂的排出。结果，凹口25内的固化树脂有效地固定了每个器件。
在形成盖帽22后，移除衬底20的背表面上的覆层，以暴露图1中所示的接合焊盘和管芯焊盘的背侧。在步骤5中引线框所暴露的表面，包括管芯焊盘和引线的暴露的第二表面，一个电镀有金属例如铜、金、铅锡焊料、锡、镍、钯或任何可软焊的金属。根据用于制造引线框的应用和材料，可以省去步骤5。
在步骤6中，从密封的引线框中切割完整的封装。特别地，步骤6从例如管芯焊盘和引线的引线框不可任意处理的元件中，清除引线框的可任意处理的部分和/或切割引线框24的可任意处理的部分，例如矩形框架。根据步骤4中使用的密封方法，步骤6也可以切割密封剂材料以形成封装的外围。
优选使用锯沿锯槽(锯坑)来纵向地切割。
进行正交切割以切单单个的半导体器件。
在切单工艺中，为了将一起构建在QFN矩阵引线框20上的成批结合的QFN封装单元切单成单个的，使用固定宽度W的切割刀片沿横向切单线和纵向切单线，切割成QFN矩阵引线框20和密封体19。如图1中还显示，通过锯刀片切割成QFN矩阵是自始至终进行的。
通过执行该切割工艺步骤，管芯焊盘和接合焊盘的端面基本上与树脂密封剂19的侧面齐平。就是说，该结构不包括通常作为外部端子提供的任何外部引线。代替地，可以为该结构提供焊料球电极，作为在外部电极之下的替换外部端子，其是没有覆盖树脂密封剂19的接合焊盘和管芯焊盘的各个被暴露的下半部分。在个别情况下，有时形成焊接镀层来代替焊料球。

Claims (5)

1、一种四方扁平无引线半导体封装器件，包括：
-  分立的半导体管芯；
-  具有第一侧向表面用于支撑该半导体管芯的管芯焊盘；以及
-  垂直于第一侧向表面的多个垂直表面，至少一个接合焊盘具有第一侧向表面和垂直于该第一侧向表面的多个垂直表面；
-  用于将该分立半导体管芯连接到接合焊盘的至少一个接合引线；以及
-  用于密封管芯、管芯焊盘、接合引线和具有侧向表面和垂直外表面的接合焊盘的密封剂，其中将管芯焊盘设置在密封剂的周围，并部分地暴露于密封剂的一个垂直外表面。
2、根据权利要求1的四方扁平无引线半导体封装器件，其中管芯焊盘的垂直表面提供有互锁装置。
3、根据权利要求1的四方扁平无引线半导体封装器件，其中管芯焊盘的垂直表面提供有垂直地和横向地互锁管芯焊盘的装置。
4、根据权利要求1的四方扁平无引线半导体封装器件，其中至少一个焊盘的第一和第二垂直表面提供有互锁装置。
5、根据权利要求1的四方扁平无引线半导体封装器件，其中接合焊盘的垂直表面提供有互锁装置。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012129819A1 (zh) * 2011-03-25 2012-10-04 锐迪科创微电子（北京）有限公司 采用四方扁平无引脚封装的gsm射频发射前端模块
CN104282635A (zh) * 2013-07-11 2015-01-14 英飞凌科技股份有限公司 具有互锁连接的半导体模块
CN104658919A (zh) * 2010-09-01 2015-05-27 群成科技股份有限公司 四边扁平无接脚封装方法
CN110945649A (zh) * 2018-05-29 2020-03-31 新电元工业株式会社 半导体模块

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY143245A (en) 2004-04-28 2011-04-15 Mitsubishi Tanabe Pharma Corp 4- 2-(cycloalkylamino)pyrimidin-4-yl-(phenyl)-imidazolin-2-one derivatives as p38 map-kinase inhibitors for the treatment of inflammatory diseases
US7078792B2 (en) * 2004-04-30 2006-07-18 Atmel Corporation Universal interconnect die
US7645640B2 (en) * 2004-11-15 2010-01-12 Stats Chippac Ltd. Integrated circuit package system with leadframe substrate
DE102005039165B4 (de) * 2005-08-17 2010-12-02 Infineon Technologies Ag Draht- und streifengebondetes Halbleiterleistungsbauteil und Verfahren zu dessen Herstellung
US7504716B2 (en) * 2005-10-26 2009-03-17 Texas Instruments Incorporated Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
US7943431B2 (en) * 2005-12-02 2011-05-17 Unisem (Mauritius) Holdings Limited Leadless semiconductor package and method of manufacture
US8629537B2 (en) * 2006-01-23 2014-01-14 Stats Chippac Ltd. Padless die support integrated circuit package system
US7449369B2 (en) * 2006-01-23 2008-11-11 Stats Chippac Ltd. Integrated circuit package system with multiple molding
US7439610B2 (en) * 2006-06-16 2008-10-21 M/A-Com, Inc. High power shunt switch with high isolation and ease of assembly
US8174119B2 (en) * 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
WO2008059301A1 (en) * 2006-11-14 2008-05-22 Infineon Technologies Ag An electronic component and method for its production
US7501693B2 (en) * 2006-11-17 2009-03-10 Micrel, Inc. LDO regulator with ground connection through package bottom
US8422243B2 (en) * 2006-12-13 2013-04-16 Stats Chippac Ltd. Integrated circuit package system employing a support structure with a recess
US8937372B2 (en) * 2007-03-21 2015-01-20 Stats Chippac Ltd. Integrated circuit package system with molded strip protrusion
US7932587B2 (en) * 2007-09-07 2011-04-26 Infineon Technologies Ag Singulated semiconductor package
JP2009252778A (ja) * 2008-04-01 2009-10-29 Sharp Corp 半導体パッケージの製造方法
US7968981B2 (en) 2008-04-11 2011-06-28 Stats Chippac Ltd. Inline integrated circuit system
US20110140591A1 (en) * 2009-12-14 2011-06-16 Han-Ming Lee Single multi-facet light source LED bracket
US8415205B2 (en) * 2010-01-12 2013-04-09 Stats Chippac Ltd. Integrated circuit packaging system with lead interlocking mechanisms and method of manufacture thereof
DE102011112659B4 (de) 2011-09-06 2022-01-27 Vishay Semiconductor Gmbh Oberflächenmontierbares elektronisches Bauelement
KR101197092B1 (ko) * 2011-11-24 2012-11-07 삼성전자주식회사 발광소자 패키지 및 상기 발광소자 패키지의 제조 방법
US8698291B2 (en) 2011-12-15 2014-04-15 Freescale Semiconductor, Inc. Packaged leadless semiconductor device
US8803302B2 (en) * 2012-05-31 2014-08-12 Freescale Semiconductor, Inc. System, method and apparatus for leadless surface mounted semiconductor package
US9184149B2 (en) * 2014-02-12 2015-11-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Semiconductor device with an interlocking wire bond
US10431532B2 (en) * 2014-05-12 2019-10-01 Rohm Co., Ltd. Semiconductor device with notched main lead
US9397029B1 (en) * 2015-06-29 2016-07-19 Alpha And Omega Semiconductor Incorporated Power semiconductor package device having locking mechanism, and preparation method thereof
ITUB20155696A1 (it) 2015-11-18 2017-05-18 St Microelectronics Srl Dispositivo a semiconduttore, corrispondenti procedimenti di produzione ed uso e corrispondente apparecchiatura
JP6842246B2 (ja) 2016-05-26 2021-03-17 ローム株式会社 Ｌｅｄモジュール
WO2018096050A1 (en) * 2016-11-23 2018-05-31 Abb Schweiz Ag Manufacturing of a power semiconductor module
JP6809196B2 (ja) * 2016-12-15 2021-01-06 コニカミノルタ株式会社 印刷中継サーバ、印刷指示方法、およびコンピュータプログラム
CN113035721A (zh) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 用于侧壁镀覆导电膜的封装工艺
CN113035722A (zh) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 具有选择性模制的用于镀覆的封装工艺

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US27273A (en) * 1860-02-28 Improvement in seeding-machines
US5977613A (en) 1996-03-07 1999-11-02 Matsushita Electronics Corporation Electronic component, method for making the same, and lead frame and mold assembly for use therein
JP3877401B2 (ja) * 1997-03-10 2007-02-07 三洋電機株式会社 半導体装置の製造方法
US6201292B1 (en) 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
JP3686287B2 (ja) * 1999-07-14 2005-08-24 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3660854B2 (ja) * 2000-04-13 2005-06-15 株式会社ルネサステクノロジ 半導体装置の製造方法
US20020063257A1 (en) * 2000-06-19 2002-05-30 Bily Wang Flat package for semiconductor diodes
US6483178B1 (en) * 2000-07-14 2002-11-19 Siliconware Precision Industries Co., Ltd. Semiconductor device package structure
TW473965B (en) 2000-09-04 2002-01-21 Siliconware Precision Industries Co Ltd Thin type semiconductor device and the manufacturing method thereof
TW473951B (en) * 2001-01-17 2002-01-21 Siliconware Precision Industries Co Ltd Non-leaded quad flat image sensor package

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104658919A (zh) * 2010-09-01 2015-05-27 群成科技股份有限公司 四边扁平无接脚封装方法
WO2012129819A1 (zh) * 2011-03-25 2012-10-04 锐迪科创微电子（北京）有限公司 采用四方扁平无引脚封装的gsm射频发射前端模块
CN104282635A (zh) * 2013-07-11 2015-01-14 英飞凌科技股份有限公司 具有互锁连接的半导体模块
US9627305B2 (en) 2013-07-11 2017-04-18 Infineon Technologies Ag Semiconductor module with interlocked connection
CN104282635B (zh) * 2013-07-11 2018-04-06 英飞凌科技股份有限公司 具有互锁连接的半导体模块
US10090216B2 (en) 2013-07-11 2018-10-02 Infineon Technologies Ag Semiconductor package with interlocked connection
CN110945649A (zh) * 2018-05-29 2020-03-31 新电元工业株式会社 半导体模块
CN110945649B (zh) * 2018-05-29 2023-06-16 新电元工业株式会社 半导体模块

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