CN104282635B - 具有互锁连接的半导体模块 - Google Patents
具有互锁连接的半导体模块 Download PDFInfo
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Abstract
一种半导体封装件,包括:具有相对的第一和第二主表面以及介于第一和第二主表面之间的侧面的支撑基板,半导体裸片,其被附接到支撑基板的主表面中的一个主表面,以及封装材料,其至少部分地覆盖支撑基板和半导体裸片。突出部从支撑基板的侧面向外延伸并终止在封装材料中。突出部形成与封装材料的互锁连接。互锁的连接增加了介于封装材料与具有突出部的支撑基板的侧面之间的界面的抗拉强度。
Description
技术领域
本申请涉及半导体模块,特别是具有不同的热膨胀系数的部件的半导体模块。
背景技术
半导体封装件包括各种部件,诸如半导体裸片(芯片)、用于裸片的支撑基板、引线、电气连接、散热片等。这些部件通常被模塑化合物所覆盖。半导体封装被额定为一定的温度范围,在温度范围的极限处可能在模塑化合物与一个或多个封装件部件之间发生分层。分层的发生是由于在不同的材料的热膨胀系数的差异。例如,包括在封装件中用于支撑裸片或散热片的铜块比起周围的模塑化合物而言具有较高的CTE(热膨胀系数)。重复循环温度降低到大约-40℃导致模塑化合物从铜块沿着模塑化合物与铜块之间的界面开始分离。由分离造成的模塑化合物与铜块之间的间隙提供了对于湿度和其它污染物到达该半导体裸片和其它包括在该封装件中的敏感部件的开放通路,导致灾难性的故障。模塑化合物的分离通常通过粗糙化由模塑化合物围绕的部件表面或使用粘合促进剂而解决。这些和其它常规的解决方案增加了封装件的成本,并且证明增加封装件的操作温度范围特别是对较低温度以一有意义的量是无效的。
发明内容
根据半导体封装件的一个实施例,该封装件包括支持基板,该支撑基板具有相对的第一和第二主表面以及介于第一和第二主表面之间的侧面,被附接到支撑基板的主表面中的一个的半导体裸片,以及至少部分地覆盖支撑基板和半导体裸片的封装材料。突出部从支撑基板的侧面向外延伸并终止在封装材料中。突出部形成与封装材料的互锁连接。互锁的连接增加了介于封装材料与具有突出部的支撑基板的侧面之间的界面的抗拉强度。
根据制造半导体封装件的方法的一个实施例,该方法包括:提供具有相对的第一和第二主表面以及介于第一和第二主表面之间的侧面的支撑基板;形成从支撑基板的侧面向外延伸的突出部;将半导体裸片附接到支撑基板的主表面中的一个主表面;并且利用封装至少部分地覆盖支撑基板和半导体裸片,使得突出部终止在封装材料中,并形成与封装材料的互锁连接。互锁的连接增加了介于封装材料与具有突出部的支撑基板的侧面之间的界面的抗拉强度。
根据半导体封装件的另一实施例,该封装件包括具有相对的第一和第二主表面以及介于第一和第二主表面之间的侧面的块以及至少部分地覆盖该块的封装材料。突出部从该块的侧面向外延伸,并终止在封装材料中。突出部的第一侧面相对于该块的侧面具有负斜率并且突出部的第二侧面相对于该块的侧面具有正斜率。突出部形成与封装材料的互锁连接。互锁的连接增加了介于封装材料与具有突出部的块的侧面之间的界面的抗拉强度。
根据设计半导体封装件的方法的一个实施例,该半导体封装件包括块和至少部分地覆盖该块的封装材料,该方法包括:仿真沿着块与封装材料之间的界面的分层,该仿真识别其中封装材料预期首先在低于0℃的温度从块中分离的界面的位置;增加突出部到封装件设计,该突出部在封装材料预期首先从块分离的界面的位置从块向外延伸。互锁连接被设计为增加介于封装材料与具有突出部的块的侧面之间的界面的抗拉强度。
本领域技术人员将通过阅读以下的详细描述以及观看附图认识到附加特征和优点。
附图说明
附图中的元件不一定相对于彼此按比例绘制。相同的附图标记表示对应的相似部分。示出的各种实施例的特征可以被结合,除非它们互相排斥。实施例被描绘在附图中并详述在下面的描述中。
图1图示了具有互锁连接的半导体封装件的实施例的局部侧透视图。
图2图示了图1的半导体封装件的局部顶视图。
图3图示了设计具有互锁连接的半导体封装件的方法的实施例的示意图。
图4图示了由图3的封装件设计方法评估分层的封装件内的各种界面的局部视图。
图5A至5C图示了在不同温度下在常规的半导体封装件内的各种界面的最大刚度降低轮廓。
图6图示了对于图5A至5C的常规的半导体封装件在添加沿着包括在封装件中的基板的侧面的突出部之后的最大刚度降低轮廓。
图7图示了对于图6的半导体封装件在更低的温度下的最大刚度降低轮廓。
图8图示了对于图6和图7的半导体封装件在添加沿着封装件基板的侧面的另外的突出部之后的最大刚度降低轮廓。
图9图示了具有形成在半导体封装件内的互锁连接的多个突出部的块的实施例的局部截面图。
图10图示了具有形成在半导体封装件内的互锁连接的多个突出部的块的另一实施例的局部截面图。
图11图示了具有形成在半导体封装件内的互锁连接的多个突出部的块的又一实施例的局部截面图。
图12图示了具有形成在半导体封装件内的互锁连接的多个突出部的块的再一个实施例的局部截面图。
图13图示了制造具有互锁连接的半导体封装件的方法的实施例的示意图。
图14图示了具有形成在半导体封装件内的互锁连接的开口的块的实施例的局部截面图。
图15图示了具有形成在半导体封装件内的互锁连接的开口的块的另一实施例的局部截面图。
图16图示了具有形成在半导体封装件内的互锁连接的开口的块的又一实施例的局部截面图。
图17图示了具有形成在半导体封装件内的互锁连接的凹陷区域的块的实施例的局部截面图。
具体实施方式
本文所描述的实施例提供了包括在半导体封装中的一个或多个块与至少部分地覆盖该块的封装材料之间的互锁连接。每个互锁连接利用在互锁连接的区域中的封装材料增加了界面的抗拉强度,使得封装材料更难以从具有互锁连接的块分开或拉开(即分层)。互锁连接可以策略性地设置于封装内的分层薄弱点,从而允许封装在较宽的温度范围内操作而不会产生分层式故障。
根据一个实施例,图1图示了半导体封装件100的一部分的侧面透视图并且图2图示了封装件100的相应的俯视图。封装件100包括支撑基板102,其具有相对的第一和第二主表面104、106和介于第一和第二主表面104、106之间的侧面108。半导体裸片110通过诸如焊锡的接合层112被附接到支撑基板102的主表面104、106中的一个。接合层112可以是单层或包括多个子层。支撑基板102可以是金属块,诸如铜块、间隔件、具有金属化侧面的陶瓷、引线框架的裸片焊盘等。任何类型的半导体裸片110可被连接到诸如晶体管裸片、二极管裸片、无源裸片等的支撑基板102。裸片110可以以任何类型的半导体技术制作,诸如Si、SiC、GaAs、GaN等。多于一个的裸片110可被附接到支撑基板102。在每种情况下,封装材料114至少部分地覆盖支撑基板102和半导体裸片110。可以采用任何合适的封装材料114,诸如环氧树脂、模塑化合物等。
突出部116从支撑基板102的侧面108向外延伸,并终止于封装材料114中。在图1和图2中所示的实施例中,支撑基板102的底表面106的至少部分被暴露,即不被封装材料114所覆盖,以提供外部电连接和/或散热。突出部116的的部分或全部底表面也可被封装材料114所覆盖。
无论哪种情况,突出部116形成与封装材料114的互锁连接,即突出部116被封装材料114锁定在一起,或与封装材料114互连,例如在固化模塑化合物封装材料114后。互锁连接增加了封装材料114与具有突出部115的支撑基板102的侧面108之间的界面的抗拉强度,使封装材料114更难以从在封装件100的该区域中的支撑基板102分层。突出部116可在与支撑基板102的同一平面上从支撑基板102的侧面108向外延伸,如图1所示。可替代地,突出部116可以在不同的平面上延伸,即与其中支撑基板102延伸的平面相交。在一个实施例中,支撑基板102是金属块并且突出部116是金属块的单一连续的部分。
广泛地,突出部116可以是支撑基板102的单一连续部分或通过例如焊接、钎焊、胶合等附连到基板102。多于一个突出部116可以设置在支撑基板102的相同或不同的侧面108。封装件100还包括引线118,其突出穿过封装材料114以提供针对封装件100的外部电连接。一个或多个引线118还可以在引线118的一个或多个侧面120处具有突出部116,其被设计为形成与周围的封装材料114的互锁连接。突出部116在封装件100内的布置可以在封装件设计过程期间确定。
图3图示了设计半导体封装件的方法的流程图,该半导体封装件包括诸如图1和图2中所示的支撑基板102的块和至少部分地覆盖该块的封装材料。该方法包括仿真沿块与封装材料(块200)之间的界面的分层。
作为仿真过程的一部分,各种制造和使用的假设是由仿真模型进行处理的,诸如材料沉积和固化温度,规定的最高和最低使用温度,载荷条件诸如正常负荷和剪切负荷,表面能量,断裂韧性等等。仿真模型基于输入到模型的各种假设确定诸如热循环环境(衰变函数)或针对设计中的封装件的线性化冷却函数之类的函数。设计中的封装件的特性然后根据由仿真模型构建的函数来建模。仿真模型识别其中封装材料预期首先在低于0℃的温度从该块中分离的界面的位置(方框200的结果)。该位置在本文中也被称为分层起始区。
该方法进一步包括增加突出部到封装件设计,其在封装材料预期首先从该块分离的界面的位置从该块向外延伸(方框210)。取决于由仿真模型所识别的分层起始区的数量和严重性,可以添加多于一个突出部到设计。每个突出部被设计成形成与周围的封装材料的互锁连接,其提高介于封装材料与块具有突出部的侧面之间的界面的拉伸强度。
图4图示了根据图3的方法设计的半导体封装件100的一部分。在图4中,示出了所考虑的界面。对在介于封装材料114与半导体裸片110之间的界面300处,在介于封装材料114与裸片接合层112之间的界面302处,以及在介于封装材料114与裸片支撑基板102的侧面108之间的界面304处的分层进行了研究。对于典型的模塑化合物和典型的金属块,诸如散热器、裸片支撑基板、引线等,对于在约-40℃下的低温的分层热膨胀系数(CTE)不匹配可能是显著的。例如,铜金属块具有约16-18的CTE并且典型的模塑化合物具有约9-12的CTE。在大约-40℃的温度,显著的分层可沿着这些界面开始产生。在甚至更低的温度下,分层恶化并导致开放间隙,该间隙提供了对于湿度和其它污染物到达诸如裸片110和互连(未示出)之类的封装件100的关键部件的通路,这可能会导致灾难性的故障。
图5A至5C图示了对于降低的更低的温度在封装材料(为便于说明,未在图5A至5C中示出)与常规的封装的裸片110'、支撑基板和接合层112'之间的界面处的标量刚度降低。图5A示出了在-45.1℃在裸片的下角的最大的刚度降低的区域以及沿着支撑基板的侧面的较少的刚度降低的区域。关注的刚度降低区域在图5A至5C中以梯度图示,其中较深色/更密集的梯度对应于较大的刚度降低并且更轻/密度较低的梯度对应较低的刚度降低。因为刚性降低,界面与封装材料的完整性降低并且分层可能发生。图5B示出了随着温度降低至-47.39℃沿着支撑基板的侧面的刚度的进一步降低。图5C表示微小的温度降低到-47.4℃,这会导致最大的刚度降低的区域从裸片的下角转移到沿着支撑基板的侧面。随着封装材料从支撑基板的侧面分离或拉离,支撑基板与封装材料之间的界面在封装件的该区域变得妥协。
图6显示了在通过本文所描述的包括沿着支撑基板102'的侧面在最大刚度降低的区域处放置的突出部116的封装件设计方法的修改之后,在-47.4℃的如图5C所示的相同的封装的裸片110'、支撑基板102'和接合层112'(即在沿着对于常规封装的支撑基板的侧面失效的界面处的临界温度)。即,仿真模型将突出部116置于支撑基板102'与封装材料之间的界面处,在该处界面预期首先会失效。如图6所示,在这个封装的以前的问题区域中,分层不再预期发生在-47.4℃。仿真结果示出该界面区域即使在更低的温度也保持可靠。
图7示出了图6的封装的裸片110'、支撑基板102'和接合层112'以及一个附加的突出部116,并且在-56.15℃。在封装材料与从支撑基板102'的侧面延伸的突出部116之间的界面在此温度下保持完好。然而,最大的刚度降低的区域从裸片的下角转移到沿着具有突出部116的支撑基板102'的同一侧的另一区域。仿真模型可以再次修改封装设计以包括放置在预期分层的该新的区域的另一个突出部116。
图8示出了图7的封装的裸片110'、支撑基板102'和接合层112'以及沿支撑基板102'的相同侧面如第一突出部116一样策略性地布置的附加的突出部116,以避免封装材料从支撑基板102'的该侧面的显著分层。图8图示了在-65℃的仿真结果。广泛地,本文所描述的仿真方法可以识别沿着包括在半导体封装件中的任何块的各个位置,并布置形成与封装材料的互锁连接的突出部,以增加介于封装件的封装材料与封装件的块之间的界面的抗拉强度。
图9图示了包括在半导体封装件中的块400的另一个实施例的局部截面图。块400可以是金属块,诸如铜块、间隔件、具有金属化侧面的陶瓷,引线框架的裸片焊盘等。块400具有第一主表面402和相对的第二表面,以及介于第一主表面与第二主表面之间的侧面404,该第二表面在图9的视图以外。封装材料114至少部分地覆盖块400。多个突起部116从块400的侧面404向外延伸,并终止于封装材料114。
在块400作为电引线的情况下,引线400可以突出到该封装材料114以外,以提供用于封装的外部电连接。在该情况下,引线400具有被图9中所示的封装材料114覆盖的第一部分,以及不被封装材料114覆盖的第二部分(在图9的视图以外)。突出部116从被封装材料114覆盖的引线400的部分延伸。
在图9所示的实施例中,每个突出部116的第一侧面406相对于具有突出部116的块400的侧面404具有负斜率(s1)。突出部116的第二侧面408相对于块400的相同侧面404具有正斜率(s2)。这是每个突出部116的第一和第二侧406、408从块400的侧面404以小于90°的角度(θ1、θ2)向外延伸。突出部116的一个或多个可以具有圆形的远端。每个突出部116形成与封装材料114的互锁连接,这增加了封装材料114与具有突起116的块400的侧面404之间的界面的抗拉强度。
在一个实施例中,封装材料114与每个突出部116之间的互锁连接是燕尾接头(dovetail joint)。根据本实施方式,突出部116形成燕尾接头的凸榫并且封装材料114与突出部116相邻的区域形成燕尾接头的榫眼。例如,每个突出部116可以从块400的侧面404向外张开,如图9所示,并且被封装材料114包围以形成突出部116与封装材料114之间的互锁接头。突出部116可以具有相同或不同的尺寸,诸如弯曲的半径(R)、宽度(W)和间距(SP)。突出部116可以被均匀地或者非均匀地沿块400的侧面404间隔开。
图10图示了包括在半导体封装件中的块500的另一实施例。在图10中所示的实施例类似于图9中所示的实施例,然而突出部116具有平面或平坦的远端502而不是圆形的远端。
图11图示了包括在半导体封装件中的块600的另一实施例。在图11中所示的实施例类似于在图9中所示的实施例,然而突部116是L形的。
图12图示了包括在半导体封装件中的块700的又一实施例。在图12中所示的实施例类似于在图11中所示的实施例,然而突出部116是T形而不是L形。
图13图示了制造半导体封装件的方法的实施例的流程图。该方法包括:提供具有相对的第一和第二主表面的支撑基板和介于第一和第二主表面(方框800)之间的侧面;形成从支承基板的侧面向外延伸的突出部(方框810);将半导体裸片附接到支撑基板的主表面之一(方框820);并且利用封装至少部分地覆盖支撑基板和半导体基板以使得突出部终止于封装材料并形成与封装材料的互锁连接,其增加了封装材料与具有突出部的支撑基板的侧面之间的界面的抗拉强度(方框830)。突出部可以通过化学蚀刻或支撑基板的冲压而形成,例如使得如本文前面所述突出部的第一侧面具有负斜率并且突出部的第二侧面具有正斜率。在实践中冲压和蚀刻均产生具有一定半径的边缘,考虑到金属引线框架的厚度,对于蚀刻半径是最小的。
上面描述的实施例提供了沿着包括在半导体封装件中的块的一个或多个侧面的(多个)突出部以形成块与至少部分地覆盖该块的封装材料之间的互锁连接。可替代地或另外地,可以提供其它表面特征以形成或加强互锁连接。
图14图示了包括在半导体封装件中的块900的另一实施例的局部截面图。块900可以是金属块,诸如铜块、间隔件、具有金属化侧面的陶瓷、引线框架的裸片焊盘等。块900具有第一主表面902和相对的第二表面,以及介于第一和第二主表面之间的侧面904,该第二表面在图14的视图以外。封装材料114至少部分地覆盖块900。多个开口906穿过块900从一个主表面延伸到另一个主表面。封装材料114填充开口906,形成该块900与封装材料114之间的互锁连接。
图15图示了块900的另一实施例。在图15中所示的实施例类似于在图14中所示的实施例,然而开口906中的至少一个具有椭圆形状而不是圆形形状。
图16图示了块900的又一实施例。在图16中所示的实施例类似于在图15中所示的实施例,然而所有的开口906具有椭圆形而不是圆形。开口906中的一个、一些或所有可以具有其它形状,诸如正方形、矩形、三角形、梯形等。
图17图示了块900的另一实施例。在图17中所示的实施例类似于在图16中所示的实施例,然而块900的主表面的一个或两个具有凹陷区域908,而不是或附加于开口906。该凹陷区域908并不完全穿过块900从一个主表面延伸至另一主表面,如图17中的阴影区域所指示的。封装材料114填充凹槽区域908,形成块900与封装材料114之间的互锁连接。凹陷区域908可以具有任何合适的形状,诸如圆形、椭圆形、正方形、矩形、三角形、梯形等。
空间相对术语,诸如“下”、“以下”、“下方”、“上”、“以上”等被用于便于说明,以解释元件相对的第二元件的定位。这些术语旨在涵盖器件的不同取向,除了那些在附图中描绘的不同定向以外。此外,诸如“第一”、“第二”等术语也可以用来描述各种元件、区域、部分等,并且也并非意在限制。相同的术语在说明书中指代相同的元件。
如本文所用,术语“具有”、“含有”、“包括”、“包含”等是开放式术语,表明所陈述的元件或特征的存在,但并不排除其它要素或特征。冠词“一”、“一个”和“该”意在包括复数以及单数,除非上下文另有明确说明。
认识到变化和应用的以上范围,应当理解的是,本发明并不受上述说明的限制,也不受附图的限制。相反,本发明仅由所附权利要求及其法律等同物限定。
Claims (19)
1.一种半导体封装件,包括:
支撑基板,具有相对的第一主表面和第二主表面以及在所述第一主表面与所述第二主表面之间延伸的侧面;
半导体裸片,被附接到所述支撑基板的所述第一主表面;
导电引线,与所述支撑基板分开并且间隔开;以及
封装材料,至少部分地覆盖所述支撑基板、所述半导体裸片和所述导电引线,所述封装材料包括与所述支撑基板的所述第二主表面共面的底部侧和与所述底部侧竖直间隔开的顶部侧;
其中所述支撑基板包括第一突出部,从所述支撑基板的侧面向外延伸,所述第一突出部形成与所述封装材料的互锁连接并且终止在所述封装材料中;以及
其中所述第一突出部包括较窄部分和较宽部分,所述较窄部分被设置为比所述较宽部分更为靠近所述支撑基板,
所述第一突出部具有完全弯曲的周界,
其中所述导电引线具有由所述封装材料覆盖的第一部分和未被所述封装材料覆盖的第二部分。
2.根据权利要求1所述的半导体封装件,其中所述突出部的第一侧面相对于所述支撑基板的所述侧面具有负斜率并且所述突出部的第二侧面相对于所述支撑基板的所述侧面具有正斜率。
3.根据权利要求1所述的半导体封装件,其中所述突出部在与所述支撑基板相同的平面上从所述支撑基板的所述侧面向外延伸。
4.根据权利要求1所述的半导体封装件,其中所述突出部具有圆形的远端。
5.根据权利要求1所述的半导体封装件,其中所述突出部与所述封装材料之间的所述互锁连接是燕尾接头,使得所述突出部形成所述燕尾接头的凸榫并且所述封装材料与所述突出部相邻的区域形成所述燕尾接头的榫眼。
6.根据权利要求1所述的半导体封装件,其中所述支撑基板是金属块并且所述突出部是所述金属块的单一连续的部分。
7.根据权利要求1所述的半导体封装件,进一步包括从所述支撑基板的侧面向外延伸并终止在所述封装材料中的多个隔开的突出部,所述多个突出部形成与所述封装材料的所述互锁连接。
8.一种制造半导体封装件的方法,所述方法包括:
提供支撑基板,所述支撑基板具有相对的第一主表面和第二主表面以及在所述第一主表面和所述第二主表面之间延伸的侧面;
提供导电引线,所述导电引线与所述支撑基板分开并且间隔开;以及
将半导体裸片附接到所述支撑基板的所述第一主表面;
形成封装材料,所述封装材料至少部分地覆盖所述支撑基板、所述半导体裸片和所述导电引线,所述封装材料包括与所述支撑基板的所述第二主表面共面的底部侧和与所述底部侧竖直间隔开的顶部侧;
其中所述支撑基板包括第一突出部,从所述支撑基板的侧面向外延伸,所述第一突出部形成与所述封装材料的互锁连接并且终止在所述封装材料中;以及
其中所述第一突出部包括较窄部分和较宽部分,所述较窄部分被设置为比所述较宽部分更为靠近所述支撑基板,
所述第一突出部具有完全弯曲的周界,
其中所述导电引线具有由所述封装材料覆盖的第一部分和未被所述封装材料覆盖的第二部分。
9.根据权利要求8所述的方法,其中所述突出部通过所述支撑基板的化学蚀刻而形成。
10.根据权利要求8所述的方法,其中所述突出部通过冲压所述支撑基板而形成。
11.根据权利要求8所述的方法,其中所述突出部被形成为使得所述突出部的第一侧面相对于所述支撑基板的所述侧面具有负斜率并且所述突出部的第二侧面相对于所述支撑基板的所述侧面具有正斜率。
12.根据权利要求8所述的方法,其中所述突出部被形成为使得所述突出部的侧面从所述支撑基板的所述侧面以小于90°的角度向外延伸。
13.一种半导体封装件,包括:
块,具有相对的第一主表面和第二主表面以及在所述第一主表面和所述第二主表面之间延伸的侧面;
导电引线,与所述块分开并且间隔开;以及
封装材料,至少部分地覆盖所述块和所述导电引线,所述封装材料包括与所述块的所述第二主表面共面的底部侧和与所述底部侧竖直间隔开的顶部侧;
其中所述块包括第一突出部,从所述块的侧面向外延伸,所述第一突出部形成与所述封装材料的互锁连接并且终止在所述封装材料中;以及
其中所述第一突出部包括较窄部分和较宽部分,所述较窄部分被设置为比所述较宽部分更为靠近所述块,
所述第一突出部具有完全弯曲的周界,
其中所述导电引线具有由所述封装材料覆盖的第一部分和未被所述封装材料覆盖的第二部分。
14.根据权利要求13所述的半导体封装件,其中所述突出部在与所述块相同的平面上从所述块的所述侧面向外延伸。
15.根据权利要求13所述的半导体封装件,其中所述突出部具有圆形的远端。
16.根据权利要求13所述的半导体封装件,其中介于所述突出部与所述封装材料之间的互锁连接是燕尾接头,使得所述突出部形成所述燕尾接头的凸榫并且所述封装材料与所述突出部相邻的区域形成所述燕尾接头的榫眼。
17.根据权利要求13所述的半导体封装件,其中所述块是支撑基板并且所述半导体封装件进一步包括半导体裸片,所述半导体裸片被附接到所述支撑基板的所述主表面中的一个主表面。
18.根据权利要求13所述的半导体封装件,其中所述块是陶瓷基板。
19.根据权利要求17所述的半导体封装件,进一步包括从所述支撑基板的侧面向外延伸并终止在所述封装材料中的多个隔开的突出部,所述多个突出部形成与所述封装材料的所述互锁连接。
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DE102016208431A1 (de) * | 2016-05-17 | 2017-11-23 | Osram Opto Semiconductors Gmbh | Anordnung mit einem elektrischen Bauteil |
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Publication number | Priority date | Publication date | Assignee | Title |
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US5886397A (en) * | 1996-09-05 | 1999-03-23 | International Rectifier Corporation | Crushable bead on lead finger side surface to improve moldability |
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US6229200B1 (en) * | 1998-06-10 | 2001-05-08 | Asat Limited | Saw-singulated leadless plastic chip carrier |
US6448633B1 (en) * | 1998-11-20 | 2002-09-10 | Amkor Technology, Inc. | Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant |
US7042068B2 (en) * | 2000-04-27 | 2006-05-09 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
US6501158B1 (en) * | 2000-06-22 | 2002-12-31 | Skyworks Solutions, Inc. | Structure and method for securing a molding compound to a leadframe paddle |
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US6847099B1 (en) * | 2003-02-05 | 2005-01-25 | Amkor Technology Inc. | Offset etched corner leads for semiconductor package |
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US8536688B2 (en) * | 2004-05-25 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit leadframe and fabrication method therefor |
US7763958B1 (en) * | 2007-05-25 | 2010-07-27 | National Semiconductor Corporation | Leadframe panel for power packages |
US7838974B2 (en) | 2007-09-13 | 2010-11-23 | National Semiconductor Corporation | Intergrated circuit packaging with improved die bonding |
US7838339B2 (en) * | 2008-04-04 | 2010-11-23 | Gem Services, Inc. | Semiconductor device package having features formed by stamping |
US20120181676A1 (en) * | 2008-04-04 | 2012-07-19 | GEM Service, Inc. | Power semiconductor device packaging |
US8072051B2 (en) * | 2009-09-15 | 2011-12-06 | Fairchild Semiconductor Corporation | Folded lands and vias for multichip semiconductor packages |
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US8742555B2 (en) * | 2011-08-30 | 2014-06-03 | Jian Wen | Lead frame having a flag with in-plane and out-of-plane mold locking features |
US8699232B2 (en) | 2011-09-20 | 2014-04-15 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer and method of manufacture thereof |
US20130181351A1 (en) * | 2012-01-12 | 2013-07-18 | King Dragon International Inc. | Semiconductor Device Package with Slanting Structures |
US9190606B2 (en) * | 2013-03-15 | 2015-11-17 | Allegro Micosystems, LLC | Packaging for an electronic device |
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