CN1758433A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1758433A
CN1758433A CNA2005100716563A CN200510071656A CN1758433A CN 1758433 A CN1758433 A CN 1758433A CN A2005100716563 A CNA2005100716563 A CN A2005100716563A CN 200510071656 A CN200510071656 A CN 200510071656A CN 1758433 A CN1758433 A CN 1758433A
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Prior art keywords
substrate
semiconductor
semiconductor device
constituting body
insulating barrier
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CNA2005100716563A
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CN100418215C (zh
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定别当裕康
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Zhao Tan Jing Co ltd
CMK Corp
Aoi Electronics Co Ltd
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Casio Computer Co Ltd
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Abstract

本发明涉及半导体器件及其制造方法。半导体器件，它包括：被施加接地电位的金属箔(2、2A)；设置在所述金属箔(2、2A)上的至少一个半导体构成体(3)，其具有半导体衬底(6)和设在该半导体衬底(6)上的多个外部连接用电极(9、16)；设置在所述半导体构成体(3)周围的绝缘层(21)，其实质上与所述半导体构成体(3)的厚度相同；在所述半导体构成体(3)和所述绝缘层(21)上设置与所述半导体构成体(3)的外部连接用电极(9，16)连接的至少一层上层布线(25)；和至少贯穿所述绝缘层(21)、连接所述金属箔(2、2A)和所述上层布线(25)的上下导通部分(32)。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件，更具体而言涉及一种内置半导体构成体的半导体器件及其制造方法。
背景技术
近年来，正在开发与以便携电话为代表的这类便携式电子设备的小型化相结合的称为CSP(芯片尺寸封装)的半导体器件。这种CSP是这样一种半导体器件：在形成多个外部连接用连接焊盘(pad)的裸半导体器件的上表面设有钝化膜(中间绝缘膜)，在这种钝化膜中与各连接焊盘相对的部分上形成开口部分，经该开口部分形成与各连接焊盘连接的布线，在各布线的另一端上形成柱状的外部连接用电极，而且在各外部连接用电极之间填充密封材料。
根据这种CSP，通过在各柱状的外部连接用电极上形成焊球，能够在具有连接端子的电路板上以倒装(面朝下)方式来进行焊接，由于可以使安装面积与裸(bare)半导体器件的尺寸大致相同，因而与采用引线接合(wire bonding)法等等以面朝上焊接方式的现有焊接方法相比，可以使电子设备大幅度的小型化。
在日本特开2001-168128号公报中记载的半导体器件示出了这种CSP的一个示例。在这篇现有技术文献中所记载的半导体器件中，在晶片状态的半导体衬底上形成钝化膜、布线、外部连接用电极和密封件，又在未用密封件覆盖而露出的外部连接用电极上表面设置焊球之后，采用了用切割线切断的方法，因此，不但能够使按切割线分割出的精确芯片尺寸变小，而且还可以因可能大幅度减少工序数量而提高生产效率。
然而，在最近，若以便携式电话装置为代表，还要求与产品小型化相结合的半导体器件小型化，则提高了半导体器件的单层集成化进步了。虽然提高了半导体器件的单层集成化，但是外部连接用电极的数目也增加了，随之产生了如下面所述的问题。也就是说，若是如上所述的那样，由于在裸半导体器件的上表面上排列有外部连接用电极，因而通常排列成矩阵状，为此，在半导体器件有多个外部连接用电极的情况下，存在外部连接用电极的尺寸和间距变得极小这样的缺点，这样一来，相对于裸半导体器件尺寸的比例来说，不适用于有多个外部连接用电极。
也就是说，假如外部连接用电极的尺寸和间距变得极小，不但难以使电路板对准其位置，接合强度不够，而且在接合时还会发生电极间的短路，通常，会发生由于用硅衬底制成的半导体衬底和电路板的线膨胀系数不同而产生的应力，使外部连接用电极破损等严重的问题。
此外，在上述现有的半导体器件中，如上所述，可以在电路板上以倒装方式来进行接合，由于可以使安装面积与裸半导体器件的尺寸大致相同，因而与采用引线接合法等等以面朝上方式的现有接合方法相比，能够大幅度地使电子设备小型化，尽管如此也对小型化有限制。
也就是说，由于在电路板上利用倒装方式来进行接合，因此裸半导体器件中与连接焊盘形成面相反的一面成为上表面，在这个面与电路板的接地端相连接的情况下，将这种专用的连接部件配置在CSP的外部，则会限制小型化。此外，当因为该连接部件设置在CSP外部的关系而使布线增长时，产生了电阻抗(杂散电容等)增加等问题，电路特性也会变差。
发明内容
因此，本发明的目的是提供一种新颖的半导体器件及其制造方法，其中即使外部连接用电极的数目增加，也可以使其大小和间距为所必需的尺寸，而且由于可以实现电子设备的单层小型化，因而能够使布线长速最短而抑制电路特性变差。
根据本发明，提供了一种半导体器件，包括：被施加接地电位的金属箔(2、2A)；设在所述金属箔(2、2A)上的至少一个半导体构成体(3)，其具有半导体衬底(6)和设在该半导体衬底(6)上的多个外部连接用电极(9、16)；设在所述半导体构成体(3)周围的绝缘层(21)，其实质上与所述半导体构成体(3)的厚度相同；在所述半导体构成体(3)和所述绝缘层(21)上设置与所述半导体构成体(3)的外部连接用电极(9，16)连接的至少一层上层布线(25)；和至少贯穿所述绝缘层(21)、连接所述金属箔(2、2A)和所述上层布线(25)的上下导通部分(32)。此外，根据本发明，还提供了一种半导体器件的制造方法，包括以下步骤：提供在至少一面具有带导电性的基底部件(1、2A)；在所述基底部件(1、2A)上相互隔开地设置多个半导体构成体(3)，所述半导体构成体分别具有半导体衬底(6)和设置在该半导体衬底(6)上的多个外部连接用电极(9、16)；在所述半导体构成体(3)周围的所述基底部件(1、2A)上形成绝缘层(21)；在所述半导体构成体(3)和所述绝缘层(21)上形成与所述半导体构成体(3)的外部连接用电极(9、16)相连接的至少一层上层布线(25)；至少贯穿所述绝缘层(21)，形成连接所述基底部件(1、2A)的一面和所述上层布线的上下导通部分(32)；切断位于所述半导体构成体(3)之间的所述绝缘层(21)和所述基底部件(1、2A)，制得至少包含一个所述半导体构成体(3)的多个半导体器件。
发明的效果如下
根据本发明，因为在半导体构成体上和设在半导体构成体周围的绝缘层上设置上层布线，所以即使上层布线的连接焊盘(外部连接用电极)的数目增多，也可以使其大小和间距为所比需的尺寸。因为通过在至少设置在绝缘层中的贯通孔中设置的上下导通部分，作为其基底部件的接地层可以连接性能部分和接地用的上层布线，所以可以使电子设备的单层小型化并且使布线长度最短而改进电路特性。
附图说明
图1是作为本发明的第一实施例的半导体器件的截面图。
图2是在图1所示的半导体器件的制造方法的一个示例中、最初制备的截面图。
图3是图2的后续工序的截面图。
图4是图3的后续工序的截面图。
图5是图4的后续工序的截面图。
图6是图5的后续工序的截面图。
图7是图6的后续工序的截面图。
图8是图7的后续工序的截面图。
图9是图8的后续工序的截面图。
图10是图9的后续工序的截面图。
图11是图10的后续工序的截面图。
图12是图11的后续工序的截面图。
图13是图12的后续工序的截面图。
图14是图13的后续工序的截面图。
图15是图14的后续工序的截面图。
图16是作为本发明第二实施例的半导体器件的截面图。
图17是作为本发明第三实施例的半导体器件的截面图。
图18是作为本发明第四实施例的半导体器件的截面图。
图19是作为本发明第五实施例的半导体器件的截面图。
图20是在制造图19所示的半导体器件期间、所规定的工序的截面图。
图21是图20的后续工序的截面图。
图22是作为本发明的第六实施例的半导体器件的截面图。
图23是在制造图22所示的半导体器件期间、所规定的工序的截面图。
图24是作为本发明第七实施例的半导体器件的截面图。
符号说明
1基板；2接地层；3半导体构成体；4粘接层；5SOI衬底
6硅衬底；7氧化硅膜；8SOI集成电路部
9连接焊盘；10绝缘膜；12保护膜；15布线
16柱状电极；17密封膜；21绝缘层；22上层绝缘膜
25上层布线；26上层涂敷膜；28焊球；31通孔
32上下导通部分；34下层布线；36下层涂敷膜
具体实施方式
(第一实施例)
图1是示出作为本发明的第一实施例的半导体器件的截面图。这个半导体器件具有由玻璃布基材环氧树脂等绝缘材料制成的平面矩形形状的基板1。在基板1的上表面上设置有由铜箔制成的完全图形化的接地层(金属箔)2。在这里，基板1及其上部所设置的接地层2构成具有接地层功能的基底部件。
在接地层2的上表面上，通过由芯片接合材料制成的粘接层4粘接着比基板1的尺寸更小的平面矩形形状的半导体构成体3的下表面。在这种情况下，半导体构成体3具有下述的布线、柱状电极、密封膜，通常称为CSP，特别是如下所述，因为在硅单晶片上形成布线、柱状电极、密封膜之后、采用通过切割而获得各种半导体构成体3的方法，所以特别也称为晶片层CSP(W-CSP)。下面，说明半导体构成体3的形成。
半导体构成体3具备SOI(绝缘体上的硅)基板5。SOI衬底5构造成：在硅衬底6的上表面上设置氧化硅膜7，在氧化硅膜7的上表面设置含多个薄膜晶体管的SOI集成电路部8。在这种情况下，SOI集成电路部8中薄膜晶体管的源极一漏极区域通过在氧化膜7的上表面设置的上下导通部(未示出)连接于硅衬底6。
接下来，硅衬底6的下表面通过粘接层4粘接在接地层2的上表面。在此，为了示出电外部噪声密封和电位的稳定化，接地层2电连接于硅衬底6的下表面。换言之，粘接层4可以是由银浆料制成的导电性材料和由芯片接合材料等制成的非导电性材料当中的任一种，在这个实施例的情况下，如上所述，使用芯片接合材料材料，极薄地形成芯片接合材料材料，通过该芯片接合材料，硅衬底6与接地层2电导通，接合后的实施例，与接地层2一同被施加接地电位。这样一来，在SOI衬底5的硅衬底6上，由于通过接地层2施加接地电位，因而能够确实地防止SOI集成电路部8的机体效应。另外，关于SOI衬底的机体效应可以参照特开2002-083975号公报。
在SOI集成电路部8的上表面周围，设置由铝系金属等制成的连接于集成电路的多个连接焊盘9。除连接焊盘9的中心外，在SOI集成电路部8的上表面上设有由氧化硅等制成的绝缘膜10，连接焊盘9的中心部分通过设置在绝缘膜10上的开口部分11露出来。
在绝缘膜10的上表面上，设置由环氧系树脂和聚酰亚胺系树脂等制成的保护膜12。在这种情况下，在保护膜12中与绝缘膜10的开口部分11相对的部分上设置开口部分13。在保护膜12的上表面上，设有由铜等制成的基底金属层14。在基底金属层14的整个上表面上，设置有铜等制成的布线15。含基底金属层14的布线15的一端部分通过两个开口部分11、13与连接焊盘9连接。
在布线15的连接焊盘部上表面上，设置由铜制成的柱状电极(外部连接用电极)16。在含布线15的保护膜12的上表面上，设置由环氧系树脂和聚酰亚胺系树脂等制成的密封膜17，以使该密封膜的上表面与柱状电极16的上表面变成齐平面。这样一来，通过含有SOI衬底5、连接焊盘9、绝缘膜10以及含有保护膜12、布线15、柱状电极16、密封膜17，而构成了称为W-CSP的半导体构成体3。
在半导体构成体3的周围，在含接地层2的基板1的上表面上设置方形框状的绝缘层21，以使该绝缘层的上表面与半导体构成体3的上表面成为大致的齐平面。绝缘层21例如是环氧系树脂和聚酰亚胺系树脂等的热固性树脂，或是在这种热固性树脂中间包含混入由二氧化硅填充物等制成的加固材料而制成的。
在半导体构成体3和绝缘层21的上表面设置上层绝缘膜22，以使该上层绝缘膜平坦.。在加强基板上使用上层绝缘膜22，通常称作加强基板材料的东西，例如在环氧系树脂等的热固性树脂中混入由二氧化硅填充物等构成的加固材料而制成的。
在与柱状电极16的上表面中心部分相对应的部分上，在上层绝缘膜22上设置开口部分23。在上层绝缘膜22的上表面设置由铜等制成的上层基底金属层24。在上层基底金属层24的整个上表面上设置由铜等制成的上层布线25。含上层基底金属层24的上层布线25的一端通过上层绝缘膜22的开口部分23与柱状电极16的上表面连接。
在含上层布线25的上层绝缘膜22的上表面，设置由阻焊剂等制成的上层涂敷膜26。在与上层布线25的连接焊盘部分相对应的部分上，在上层涂敷膜26上设置开口部分27。在开口部分27内部及上方设置焊球28，使得焊球28与上层布线25的连接焊盘部分相连接。多个焊球28呈阵列状设置在上层涂敷膜26上。
在上层绝缘膜22、绝缘层21、接地层2和基板1的规定处设置通孔31。在通孔21的内壁表面上设置与接地层2连接的上下导通部32，该上下导通部32由用铜制成的基底金属层32a和铜层32b组成。在这种情况下，上下导通部分32的上部与接地用的上层布线24连接。
上下导通部分32的下部连接于岛状设置在通孔31周围的基板1的下表面上的下层基底金属层33和下层布线34。在这种情况下，含下层基底金属层33的下层布线34因为是岛状的，所以哪里也不与上下导通部分32的外部相电连接。在上下导通部分32的内部填充由阻焊剂等制成的填充材料35。在含下层布线34的基板1下表面上设置由阻焊剂等制成的下层涂敷膜36。
然而，由于基板1的尺寸比半导体构成体3的尺寸要大，因而相应地增加了SOI衬底5上面连接焊盘9的数目，焊球28的设置区域比半导体构成体3的尺寸要大，这样一来，上层布线25的连接焊盘部分(上层涂敷膜26的开口部分27以内的部分)的尺寸和间距也比柱状电极的尺寸和间距要大。
为此，设置成阵列状的上层布线25的连接焊盘部分不只配置在对应于半导体构成体3的区域上，还设置在与置于半导体构成体3外侧面上的绝缘层21相对应的区域上。换言之，在设置成阵列状的焊球28当中，至少将最外围的焊球28设置在比半导体构成体3更外侧的位置周围。
而且，在半导体器件中，由于在只有SOI衬底5的半导体构成体3下面、在基板1的上表面上设置接地层2，通过设在上层绝缘膜22、绝缘层21、接地层2和基板1中的通孔31内所设置的上下导通部分32，将接地层2连接于接地用的上层布线25，因此在可以使电子设备使更可能实现单层小型化的同时，还能够使布线长度最短而改进电路特性。
接下来，说明这种半导体器件的制造方法的一个示例，首先，说明半导体构成体3的制造方法的一个示例。在这种情况下，首先，如图2所示，在晶片状态的硅衬底6上设置氧化硅膜7、形成薄膜晶体管的SOI集成电路部8、由铝系金属等制成的连接焊盘9、由氧化硅等制成的绝缘膜10以及由环氧系树脂和聚酰亚胺等制成的保护膜12，以用于使连接焊盘9的中心部分通过形成于绝缘膜10和保护膜12上的开口部分11、13露出。
在这种情况下，SOI集成电路部8中薄膜晶体管的源极一漏极区域通过设置在氧化硅膜7上的上下导通部分(未示出)而连接于硅衬底6。而且，连接焊盘9连接于在各个对应区域上形成的SOI集成电路部8的集成电路。
接下来，如图3所示，包含通过两个开口部分11、13露出的连接焊盘9上表面的保护膜12在其整个上表面上形成基底金属层14。在这种情况下，基底金属层14可以仅仅是通过非电解电镀形成的铜层，还可以仅仅是通过喷镀形成的铜层，也可以是在通过喷镀形成的钛等薄膜层上再进行喷镀而形成的铜层。
接下来，在基底金属层14的上表面上构图形成电镀抗蚀剂膜。在这种情况下，与形成布线15的区域相对应的部分中在电镀抗蚀剂膜41上形成开口部分42。接着，通过将基底金属层14作为电镀电流回路并进行铜电解电镀，从而在电镀抗蚀剂膜41开口部分42内的基底金属层14的上表面上形成布线15。接着，剥离电镀抗蚀剂膜41。
接下来，如图4所示，在包含布线15的基底金属层14的上表面上构图形成电镀抗蚀剂膜43。在这种情况下，在与柱状电极16形成区域相对应的部分中在电镀抗蚀剂膜43上形成开口部分44。接着，通过将基底金属层14作为电镀电流回路并进行铜电解电镀，从而在电镀抗蚀剂膜43的开口部分44内的布线15的连接焊盘部分上表面上形成柱状电极16。接着，剥离电镀抗蚀剂膜43，然后，将布线15作为掩模并以蚀刻方式除去基底金属层14中不必要的部分，如图5所示，只在布线15的下面残留有基底金属层14。
接下来，如图6所示，通过丝网印刷法、旋涂法、增粘涂层法等，在包含柱状电极16和布线15的保护膜12的整个上表面上形成由环氧系树脂和聚酰亚胺系树脂等制成的密封膜17，使得密封膜的厚度比柱状电极16的高度还要厚。因此，在这种状态下，柱状电极16的上表面被密封膜17覆盖。
接下来，适当地研磨密封膜17和柱状电极16的上表面外侧，如图7所示，露出柱状电极16的上表面，并且，使得包含该露出的柱状电极16上表面的密封膜17的上表面变平坦。在此，由于通过电解电镀所形成的柱状电极16的高度参差不齐，因此为了消除这种参差不齐，使柱状电极16的高度均匀，适当地研磨柱状电极16的上表面外侧。
接下来，如图8所示，在硅衬底6的整个下表面上粘接有粘接层4。粘接层4是由环氧系树脂、聚酰亚胺系树脂等芯片接合材料制成的，通过加热加压，固着在呈半硬化状态的硅衬底6上。接着，将固着在硅衬底上的粘接层4贴在切割带(未示出)上，经过如9所示的划片工序之后，从切割带上剥去它，如图1所示，制得在硅衬底6的下表面上具有粘接层的多个半导体构成体3。
在这样制得的半导体构成体3中，由于在硅衬底6的下表面上具有粘接层4，因而不需要在划片工序之后分别在各个半导体构成体3的硅衬底6下表面上设置粘接层这样非常费事的操作。另外，如果与在划片工序后分别在各个半导体构成体3的硅衬底6的下表面上设置粘接层的加工相比，在划片之工序后从切割带上剥离的加工就变得非常简单了。
接下来，说明在使用这样制得的半导体构成体3制造图1所示的半导体器件的情况下的一个示例。首先，如图10所示，提供基板1，其面积能形成多个图1所示的已制造出的半导体器件。基板1例如是但不限于平面方形形状。在这种情况下，通过在基板1的上表面上利用光刻法对层叠的铜箔进行构图，从而在基板1的上表面上形成完全图形化的接地层2。
接着，在接地层2上表面规定的多处分别粘接与半导体构成体3的硅衬底6下表面粘接的粘接层4。这里的粘接是通过加热加压而使粘接层4本质硬化。接着，在半导体构成体3的周围，在含接地层2的基板1的上表面上例如通过丝网印刷法和旋涂法等来形成绝缘层形成用层21a。绝缘层形成用层21a例如是环氧系树脂和聚酰亚胺系树脂等的热固性树脂，或是在像这种热固性树脂中混入由二氧化硅填充物等制成的加固材料而形成的树脂。
接着，在半导元件3和绝缘层形成用层21a的上表面上设置上层绝缘膜形成用薄板22a。上层绝缘膜形成用薄板22a最好是但不限于薄板上的加强材料，这种加强材料是通过在环氧系树脂等的热固性树脂中混入二氧化硅填充物、并使热固性树脂半硬化状态而制成的。另外，作为上层绝缘膜形成用薄板22a可以使用在玻璃布中含浸聚酰亚胺等热固性树脂、使热固性树脂为半硬化状态、然后制成薄板状的预浸材料而制成的薄板上的东西用作为上层绝缘膜形成用薄板22a，还可以使用在不混入二氧化硅填充物的情况下仅由半硬化状态的热固性树脂制成的薄板上的物质。
接下来，如图11所示，利用一对加热加压板45、46分别从上下对绝缘层形成用层21a和上层绝缘膜形成用薄板22a进行加热加压。尔后，在半导体构成体3的周围，在含接地层2的基板1的上表面上形成绝缘层21，并在半导体构成体3和绝缘层21的上表面上形成上层绝缘膜22。在这种情况下，上层绝缘膜22的上表面由于被上侧的加热加压板45的下表面压住而变成了平坦表面。因此，不需要为使上层绝缘膜22的上表面平坦化而进行研磨工艺。
接下来，如图12所示，通过照射激光束的激光束加工，在上层绝缘膜22与柱状电极16的上表面中心部分相对应的部分中形成开口部分23。另外，利用机械钻头，在上层绝缘膜22、绝缘层21、接地层2和基板1的规定处形成通孔31。接着，根据需要，通过消尾处理除去出现在开口部分23内和通孔31内等中的环氧涂片等。
接下来，如图13所示，包含通过开口部分23露出的柱状电极16上表面的上层绝缘膜22的整个上表面，在基板1的整个下表面和通孔31的内壁表面上，通过铜的非电解电镀，形成上层基底金属层24、下层基底金属层33、基底金属层32a。接着，在上层基底金属层24的上表面上构图形成上层电镀保护膜47，又在下层基底金属层33的下表面上构图形成下层电镀保护膜48。在这种情况下，在与含通孔31的上层布线25形成区域相对应的部分在上层电镀保护膜47上形成开口部分49。另外，在与含通孔31的下层布线34形成区域相对应的部分的下层电镀保护膜48上形成开口部分50。
接着，通过对作为电镀电流电路的基底金属层24、33、32a进行铜电解电镀，在上层电镀保护膜47开口部分49内的上层基底金属层24的上表面上形成上层布线25，又在下层电镀保护膜48开口部分50内的下层基底金属层33的下表面上形成下层布线34，再在通孔31内的基底金属层32a的表面上形成铜层32b。
接着，剥离两个电镀保护膜47、48，然后将上层布线25和下层布线34作为掩模，蚀刻除去基底金属层24、33中不必要的部分，如图14所示，仅仅在上层布线25的下方残留上层基底金属层24，还仅仅在下层布线34的上方残留下层基底金属层33。在这种状态下，在通孔31的内壁表面上设置与接地层2连接的上下导通部分32，该上下导通部分32由基底金属层32a和铜层32b组成。
接下来，如图15所示，通过丝网印刷法和旋涂法等，在包含上层布线25的上层绝缘膜22上表面上形成由阻焊剂等制成的上层涂敷膜26，又在包含下层布线34的基板1下表面上形成由阻焊剂等制成的下层涂敷膜36，同时，在上下导通部分32内部填充由阻焊剂等制成的填充材料35。在这种情况下，在与上层布线25的连接焊盘部分相对应的部分中在上层涂敷膜26上形成开口部分27。
接着，在开口部分27内部及其上方形成焊球28，使得该焊球28，与上层布线25的连接焊盘部分连接。接着，在相邻的半导体构成体3之间，切断上层保护膜26、上层绝缘膜22、绝缘膜21、基板1和下层保护膜36，从而制得多个图1所示的半导体器件。
如上所述，在上述制造方法中，在基板1上通过粘接层设置多个半导体构成体3，由于对于多个半导体构成体3，特别统一地形成上层布线25、上下导通部分32和焊球28，之后截断而制得多个的半导体器件，因此能够简化制造工艺。另外，在图11所示的制造工艺后，由于能够与基板1一起传送多个半导体构成体3，因而也能够简化制造工艺。
(第二实施例)
图16示出了作为本发明的第二实施例的半导体器件的截面图。对于这种半导体器件而言，与图1所示的半导体器件不同之处在于：接地层2不直接与上下导通部分32连接，在基板1的下面设置与上下导通部分32连接的下层基底金属层33，含有该下层基底金属层33的下层布线34经形成于基板1上的通孔61与接地层2的下表面连接。在这种情况下，穿过由玻璃布基材环氧树脂等制成的基板1的通孔61的形成是通过照射激光束的激光束加工而完成的。
(第三实施例)
图17示出了作为本发明第三实施例的半导体器件的截面图。对于这种半导体器件而言，与图1所示的半导体器件不同之处在于：在基板1的上表面上设置了接地层2的基础上，以及在基板的下表面上以整个形状地设置含下层基底金属层33的下层布线34，使这种由完整图形构成的下层布线34保持作为接地层的功能。
(第四实施例)
图18示出了作为本发明第四实施例的半导体器件的截面图。对于这种半导体器件而言，与图1所示的半导体器件不同之处在于：没有在基板1的上表面设置接地层2，以及在基板的下表面上以整个形状地设置含下层基底金属层33的下层布线34，使这种由完整图形化构成的下层布线34保持作为接地层的功能。
(第五实施例)
图19示出了作为本发明第五实施例的半导体器件的截面图。对于这种半导体器件而言，与图1所示的半导体器件不同之处在于：没有设置由玻璃布基材环氧树脂等绝缘材料制成的基板1，在由铜箔等制成的金属箔(基底部件)2A的上表面上设置半导体构成体3和绝缘层21，在金属箔2A的整个下表面上设置包含下层基底金属层33的下层布线34，在下层布线34的整个下表面上设置下层保护膜36。在这种情况下，包含下层布线34的金属箔2A具备作为接地层的功能。
在制造这种半导体器件的情况下，在图10所示的工艺中，如图20所示，通过粘接层4使位于由层叠的铜等构成的金属箔2A上表面上的半导体构成体3的下表面与在由玻璃布基材环氧树脂和铝等制成的基板1上表面粘接在一起。接着，在半导体构成体3的周围的金属箔2A的上表面上，例如，通过丝网印刷法和旋涂法等，形成绝缘层形成用层21a。接着，在半导体构成体3和绝缘层形成用层21a的上表面上设置上层绝缘膜形成用薄板22a。
接着，利用一对加热加压板(未示出)从上下对绝缘层形成用层21a和上层绝缘膜形成用薄板22a进行加热加压。这样，在半导体构成体3的周围的金属箔2A的上表面上形成绝缘层21，在半导体构成体3和绝缘层21的上表面上形成上层绝缘膜22。接着，从金属箔2A上剥离基板1，如图21所示，露出金属箔2A。
在这种状态下，由于将半导体构成体3和绝缘层21设置由铜箔等制成的金属箔2A上，且在该金属箔2A上设置上层绝缘膜22，因此即便由铜箔等制成的金属箔2A的下半部不结实，也不能支撑任何的强度。在下面的工序中，由于与上述第一实施例的情形大致相同，因此省略其说明。然而，在图19所示的半导体器件中，由于不具备基板1，所以就能使那一部分薄型化。
(第六实施例)
图22示出了作为本发明第六实施例的半导体器件的截面图。对于这种半导体器件而言，与图1所示的半导体器件不同之处在于：作为半导体构成体3，具有柱状电极16和密封膜17，采用使包含基底金属层14的布线15露出来的结构，通过上层绝缘膜22的开口部分23将包含上层基底金属层24的上层布线25的一端与布线15的连接焊盘(外部连接用电极)连接。
在制造这种半导体器件的情况下，在图10所示的工艺中，如图23所示，在半导体构成体3的周围，在包括接地层2的基板1的上表面上，例如通过丝网印刷法和旋涂法等形成绝缘层形成用层21a。接着，在半导体构成体3的布线15的上表面上设置上层绝缘膜形成用薄板22a。然后，在这种状态下，最好利用一对加热加压板(未示出)从上下对绝缘层形成用层21a和上层绝缘膜形成用薄板22a进行加热加压。
(第七实施例)
在上述第一实施例中，如图1所示，说明了在上层绝缘膜22上只形成一层上层布线25的情形，但不作为限制，2层以上的上层布线也是可以的，例如，如图24所示的本发明第七实施例，可以是2层的。即，在上层绝缘膜22和上层保护膜26之间设置上层绝缘膜62，在第2上层绝缘层膜62上表面设置第2上层基底金属层63，包含该第2上层基底金属层63的第2上层布线64的一端通过第2上层绝缘膜62的开口部分65而与上层布线25的连接焊盘部分连接，可以在第2上层布线64的连接焊盘部分上设置焊球28。在这种情况下，接地层2通过上下导通部分32与于接地用的第2上层布线64连接。
(其它实施例)
在上述第一实施例中，切断相邻接的半导体构成体3，但不作为限制，将2个或者2个以上的半导体构成体3切断成一组，从而可以这样制得多片状组件型半导体器件。在这种情况下，以2个为一组的半导体构成体3可以是同类的也可以是不同类的。
另外，在上述第一实施例中，如图1所示，半导体构成体3具有SOI衬底5，但不作为限制，在硅衬底的上表面上形成具有规定功能的集成电路，也可以具有在硅衬底的上表面周边部分设置与集成电路连接的多个连接焊盘这一结构的常规配对芯片。

Claims (13)

1.一种半导体器件，其特征在于包括：
金属箔(2、2A)，被施加接地电位；
至少一个半导体构成体(3)，设置在所述金属箔(2、2A)上，具有半导体衬底(6)和设在该半导体衬底(6)上的多个外部连接用电极(9、16)；
绝缘层(21)，设置在所述半导体构成体(3)的周围，厚度实质上与所述半导体构成体(3)的厚度相同；
至少一层上层布线(25)，在所述半导体构成体(3)和所述绝缘层(21)上与所述半导体构成体(3)的外部连接用电极(9，16)连接而设置；和
上下导通部分(32)，至少贯穿所述绝缘层(21)而连接所述金属箔(2、2A)和所述上层布线(25)。
2.根据权利要求1所述的半导体器件，其特征在于：所述金属箔(2A)具有与所述绝缘层(21)的外形尺寸实质上相同的外形尺寸。
3.根据权利要求2所述的半导体器件，其特征在于：所述金属箔(2A)具有贯穿所述上下导通部分(32)的通孔。
4.根据权利要求1所述的半导体器件，其特征在于：还包括支撑所述金属箔(2)的基板。
5.根据权利要求1所述的半导体器件，其特征在于：通过与所述金属箔(2、2A)电导通的粘接剂将所述半导体构成体(3)固定在所述金属箔(2、2A)上。
6.根据权利要求5所述的半导体器件，其特征在于：所述半导体构成体(3)包括半导体衬底(6)、在所述半导体衬底(6)上形成的绝缘层(7)、和形成于绝缘层(7)上且含多个薄膜晶体管的SOI集成电路部(8)。
7.根据权利要求1所述的半导体器件，其特征在于：还包括覆盖所述半导体构成体(3)和所述绝缘层(21)的上层绝缘层(22)，所述上层布线(25)形成在所述上层绝缘层(22)上。
8.根据权利要求1所述的半导体器件，其特征在于：所述半导体构成体(3)的外部连接用电极(16)是柱状的。
9.根据权利要求8所述的半导体器件，其特征在于：所述半导体构成体(3)包括在所述半导体衬底(6)上的所述柱状电极(16)之间形成的密封膜(17)。
10.一种半导体器件的制造方法，其特征在于包括以下步骤：
提供在至少一面具有导电性的基底部件(1、2A)；
在所述基底部件(1、2A)上相互隔开地设置多个半导体构成体(3)，所述半导体构成体分别具有半导体衬底(6)和设置在该半导体衬底(6)上的多个外部连接用电极(9、16)；
在所述半导体构成体(3)的周围的所述基底部件(1、2A)上形成绝缘层(21)；
在所述半导体构成体(3)和所述绝缘层(21)上形成与所述半导体构成体(3)的外部连接用电极(9、16)相连接的至少一层上层布线(25)；
至少贯穿所述绝缘层(21)，形成连接所述基底部件(1、2A)的一面和所述上层布线的上下导通部分(32)；
切断所述半导体构成体(3)之间的所述绝缘层(21)和所述基底部件(1、2A)，制得多个至少包含一个所述半导体构成体(3)的半导体器件。
11.根据权利要求10所述的半导体器件的制造方法，其特征在于包括：准备所述基底部件(1、2A)是准备具有基板(1)和设置在所述基板(1)的上下表面中至少一面的金属箔(2、2A)的所述基底部件(1、2A)。
12.根据权利要求11所述的半导体器件的制造方法，其特征在于包括以下步骤：在所述半导体构成体(3)的周围的所述基底部件(1、2A)上形成绝缘层(21)之后，从所述金属箔(2A)上剥离所述基板(1)。
13.根据权利要求12所述的半导体器件的制造方法，其特征在于包括以下步骤：从所述金属箔(2A)上剥离所述基板(1)之后，在所述金属箔(2A)的下表面上形成电镀层。
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US7279750B2 (en) 2007-10-09
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