TWI384595B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI384595B
TWI384595B TW097129986A TW97129986A TWI384595B TW I384595 B TWI384595 B TW I384595B TW 097129986 A TW097129986 A TW 097129986A TW 97129986 A TW97129986 A TW 97129986A TW I384595 B TWI384595 B TW I384595B
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Taiwan
Prior art keywords
insulating film
layer
wiring
semiconductor
semiconductor device
Prior art date
Application number
TW097129986A
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English (en)
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TW200915501A (en
Inventor
Hiroyasu Jobetto
Original Assignee
Teramikros Inc
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Publication date
Priority claimed from JP2007206067A external-priority patent/JP2009043858A/ja
Priority claimed from JP2007250952A external-priority patent/JP5042762B2/ja
Application filed by Teramikros Inc filed Critical Teramikros Inc
Publication of TW200915501A publication Critical patent/TW200915501A/zh
Application granted granted Critical
Publication of TWI384595B publication Critical patent/TWI384595B/zh

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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description

半導體裝置及其製造方法
本發明係關於一種半導體裝置及其製造方法，更詳細言之，係關於內建有半導體構成體的半導體裝置及其製造方法。
在先前技術的半導體裝置，例如，如揭示於日本特開2000－223518號公報等被稱為晶片尺寸封裝(CSP)者。揭示於此早先文件之半導體裝置，是在矽基板下設置多個外部接續用之柱狀電極，在此狀態藉由將柱狀電極之間封閉而獲得。在此CSP中，可製得與矽基板相同尺寸的半導體封裝，因此可使半導體裝置小型化且可提高構裝密度。但是，先前技術之此種半導體裝置係在半導體構成體之平面的面積區域內，設置外部接續用電極(Fan－in)之構成，因而無法適用在外部接續用電極之配置數為多而使配置間距比預定之尺寸，例如0.5μm左右更小的情況。
因此，日本特開2005－216935號公報，係採用：將稱為CSP之半導體構成體搭載於平面尺寸比該半導體構成體更大的底板上，以封裝膜包覆搭載於此底板上的半導體構成體，將對應於底板之一面之幾乎所有區域作為半導體構成體之外部接續用電極的配置區域之扇出(Fan－out)構成。在此構成中，可將外部接續用電極的配置區域作成充分地大，因此即使外部接續用電極為極大之情況，亦可使各外部接續用電極的尺寸及間距有充分的間距。
但是，上述先前技術之半導體裝置中，搭載半導體構成體的底板係為必要，此底板使裝置全體變厚係為重大課題。
因而，本發明之目的在提供一種半導體裝置及其製造方法，在將外部接續用電極的配置區域作成比半導體構成體之平面尺寸更大的情況，可達成薄型化。
本發明之半導體裝置，其特徵為具備：半導體構成體(2)，具有半導體基板(4)及設置於該半導體基板下之多個外部接續用電極(13)；下層絕緣膜(1)，設置於上述半導體構成體下及其周圍；下層配線(22,22A)，在上述下層絕緣膜下係設置成接續至上述半導體構成體之外部接續用電極；絕緣層(31)，設置於上述半導體構成體之周圍的上述下層絕緣膜上；上層絕緣膜(32)，設於上述半導體構成體及上述絕緣層上；及上層配線(33,33A)，設於上述上層絕緣膜上， 將搭載上述半導體構成體及上述絕緣層的底板(51)除去。
又，本發明之製造方法，是在底板(51)上形成下層絕緣膜(1)，將具有半導體基板(4)及設置於該半導體基板下之多個外部接續用電極(13)的多個半導體構成體(2)固著在上述下層絕緣膜上，將絕緣層(31a)形成在上述半導體構成體 之周圍的上述下層絕緣膜上，且在上述半導體構成體及上述絕緣層上形成上層絕緣膜(32a)。其次，除去上述底板(51)，其後，在上述下層絕緣膜下，將下層配線(22,22A)形成接續至上述半導體構成體之外部接續用電極，且在上述上層絕緣膜上形成上層配線(33,33A)。其後，將上述半導體構成體之間的上述下層絕緣膜、上述絕緣層、及上述上層絕緣膜加以切斷而獲得多個半導體裝置。
依照本發明時，可將外部接續用電極的配置區域作成比半導體構成體之平面尺寸更大，而且不具備底板，因此可達成薄型化。
 (第1實施形態)
第1圖係顯示本發明之第1實施形態的半導體裝置的剖面圖。此半導體裝置具備由環氧系樹脂、聚亞醯胺系樹脂、玻璃布基材環氧樹脂等形成的平面方形之下層絕緣膜1。半導體構成體2經由環氧系樹脂等形成的黏著層3而搭載於下層絕緣膜1的上面中央部。此時，下層絕緣膜1的平面尺寸係比半導體構成體2之平面尺寸更大。
半導體構成體2具備平面方形之矽基板(半導體基板)4。在矽基板4之下面4a設置預定功能之積體電路(未圖示)，在下面周邊部，由鋁系金屬等形成的多個接續墊5係設置成接續到積體電路。在除去接續墊5的中央部之矽基板4的下面設有由氧化矽等形成的絕緣膜6，接續墊5 的中央部經由設置於絕緣膜6的開口部7而露出。
在絕緣膜6之下面設置由聚亞醯胺系樹脂等形成的保護膜8。在對應於絕緣膜6之開口部7的部分之保護膜8，設置開口部9。在保護膜8之下面設置配線10。配線10係為由設於保護膜8之下面的銅形成的基底金屬層11、及設於基底金屬層11之下面的銅形成的上部金屬層12之2層構造。配線10之一端部經由絕緣膜6及保護膜8之開口部7,9而接續到接續墊5。
在配線10之接續墊部下面設置由銅形成的柱狀電極(外部接續用電極)13。在包含配線10之保護膜8的下面，由環氧系樹脂等形成的封裝膜14係設置成其下面為與柱狀電極13之下面為同一面。其後，半導體構成體2係其柱狀電極13及封裝膜14的下面經由環氧系樹脂等形成之黏著層3而黏著到下層絕緣膜1之上面中央部，藉此而搭載到下層絕緣膜1之上面中央部。
在對應於半導體構成體2之柱狀電極13的下面中央部之部分的下層絕緣膜1及黏著層3，設置開口部21。在下層絕緣膜1的下面設置下層配線22。下層配線22係為由設於下層絕緣膜1之下面的銅形成的基底金屬層23、及設於基底金屬層23之下面的銅形成的上部金屬層24之2層構造。下層配線22之一端部經由下層絕緣膜1、及黏著層3之開口部21而接續到半導體構成體2之柱狀電極13。
在包含下層配線22的下層絕緣膜1之下面，設置由阻銲劑等形成的下層包覆膜25。在對應於下層配線22的接 續墊部之部分的下層包覆膜25設置開口部26。在下層包覆膜25之開口部26內及其下方，銲球27係設置成接續到下層配線22的接續墊部。
在包含黏著層3之半導體構成體2的周圍之下層絕緣膜1的上面，設置絕緣層31。絕緣層31係由環氧系樹脂、聚亞醯胺系樹脂、玻璃布基材環氧樹脂等形成。在半導體構成體2及絕緣層31之上面設置有與下層絕緣膜1同一材料製成的上層絕緣膜32。
在上層絕緣膜32的上面設置上層配線33。上層配線33係為由設於上層絕緣膜32之上面的銅形成的基底金屬層34、及設於基底金屬層34之上面的銅形成的上部金屬層35之2層構造。在包含上層配線33的上層絕緣膜32之上面設置由阻銲劑等形成的上層包覆膜36。在對應於上層配線33的接續墊部之部分的上層包覆膜36設置開口部37。
下層配線22及上層配線33，係經由設置於下層絕緣膜1、絕緣層31、及上層絕緣膜32之預定處的貫穿孔41之內壁面的上下導通部42而接續。上下導通部42係為由設於貫穿孔41之內壁面的銅形成的基底金屬層43、及設於基底金屬層43之內面的銅形成的上部金屬層44之2層構造。在上下導通部42內充填由阻銲劑等形成的充填材45。
其次，將針對此半導體裝置之製造方法的一例進行說明。首先，如第2圖所示，準備：在由銅箔形成的底板51之上面形成由環氧系樹脂、聚亞醯胺系樹脂、玻璃布基材 環氧樹脂等形成的下層絕緣膜1之物件。此時，此已準備的物件之尺寸，係為可形成多個第1圖所示之完成後之半導體裝置的尺寸。又，下層絕緣膜1中由環氧系樹脂形成的熱硬化性樹脂係已經硬化。
又，準備半導體構成體2。此半導體構成體2，係在晶圓狀態的矽基板4下形成：積體電路(未圖示)、由鋁系金屬等所形成的接續墊5、由氧化矽等形成的絕緣膜6、由聚亞醯胺系樹脂等形成的保護膜8、配線10(由銅形成的基底金屬層11及由銅形成的上部金屬層12)、由銅形成的柱狀電極13及環氧系樹脂等形成的封裝膜14之後，利用切割加以個片化而獲得。
其次，藉由使半導體構成體2之柱狀電極13及封裝膜14之下面經由環氧系樹脂所成之黏著層3而黏著，而將半導體構成體2搭載於下層絕緣膜1之上面的半導體構成體搭載區域。此時，在下層絕緣膜1之上面的半導體構成體搭載區域，係使用印刷法或分配器等預先供給NCP(非導電性糊膏)之糊狀的黏著材、或NCF(非導電性薄膜)之薄片狀黏接材，利用加熱壓著而將半導體構成體2固著在下層絕緣膜1。
其次，如第3圖所示，使用真空吸附器等吸附格子狀之絕緣層形成用薄板31a，並以XY台移動而定位、固定在包含黏著層3之半導體構成體2的周圍之下層絕緣膜1的上面。固定例如係藉由使用銷等在絕緣層形成用薄板31a的緣部，貫穿絕緣層形成用薄板31a而突刺到下層絕緣膜 1的方法而進行。絕緣層形成用薄板31a，係在玻璃布等形成的基材上含浸環氧系樹脂等形成的熱硬化性樹脂，將熱硬化性樹脂作成半硬化狀態而形成薄片狀，利用衝孔而形成多個方形之開口部52者。絕緣層形成用薄板31a之開口部52的尺寸係稍大於半導體構成體2之尺寸。因此，在絕緣層形成用薄板31a與半導體構成體2之間形成間隙53。
其次，在絕緣層形成用薄板31a之上面，配置有在由銅箔形成的子底板54之下面形成上層絕緣膜形成用層32a者。上層絕緣膜形成用層32a係由與下層絕緣膜1同樣的材料製成，其中由環氧系樹脂等形成的熱硬化性樹脂被作成半硬化狀態。
其次，如第4圖所示，使用一對加熱加壓板55,56從上下對絕緣層形成用薄板31a及上層絕緣膜形成用層32a進行加熱加壓。藉由此加熱加壓，絕緣層形成用薄板31a被壓縮，該絕緣層形成用薄板31a及上層絕緣膜形成用層32a中之熱硬化性樹脂會流動而充填於第3圖所示之間隙53，藉由其後之冷卻而固化，而在包含黏著層3的半導體構成體2之周圍的下層絕緣膜1之上面形成絕緣層31，且在半導體構成體2及絕緣層31之上面形成上層絕緣膜32。
此時，下層絕緣膜1係其中之熱硬化性樹脂預先被硬化，因此即使被加熱加壓亦不變形。又，藉由子底板54，可防止上層絕緣膜形成用層32a中之熱硬化性樹脂非所要地附著於上側之加熱加壓板55之下面。結果，可使上側之加熱加壓板55保持原狀再使用。
其次，當使用腐蝕液將底板51及子底板54加以除去時，如第5圖所示，下層絕緣膜1之下面被露出，且上層絕緣膜32之上面亦露出。在此狀態，即使底板51及子底板54被除去，藉由下層絕緣膜1、絕緣層31、及上層絕緣膜32之存在，亦可充分地確保強度。
其次，如第6圖所示，藉由將雷射光束照射在對應於半導體構成體2之柱狀電極13的下面中央部之部分的下層絕緣膜1及黏著層3之雷射加工，而形成開口部21。又，在下層絕緣膜1、絕緣層31、及上層絕緣膜32之預定處，使用機械鑽頭形成貫穿孔41。
其次，如第7圖所示，在經由下層絕緣膜1及黏著層3之開口部21而露出的半導體構成體2之柱狀電極13的下面及下層絕緣膜1之下面全體、上層絕緣膜32之上面全體及貫穿孔41之內壁面，藉由銅之無電解電鍍而形成基底金屬層23,34,43。其次，進行將基底金屬層23,34,43作為電鍍電流路徑之銅的電解電鍍，藉以在基底金屬層23,34,43之表面形成上部金屬層24,35,44。
其次，利用微影蝕刻法，將上部金屬層24,35及基底金屬層23,34進行圖案化時，成為如第8圖所示的樣子。即，在下層絕緣膜1的下面，形成由基底金屬層23及上部金屬層24形成的2層構造之下層配線22。又，在上層絕緣膜32之上面，形成由基底金屬層34及上部金屬層35形成的2層構造之上層配線33。更在貫穿孔41之內壁面，形成由基底金屬層43及上部金屬層44形成的2層構造之 上下導通部42。
其次，如第9圖所示，在包含下層配線22的下層絕緣膜1之下面，藉由篩網印刷法、旋塗法等形成由阻銲劑等形成的下層包覆膜25。又，在包含上層配線33的上層絕緣膜32之上面，藉由篩網印刷法、旋塗法等形成由阻銲劑等形成的上層包覆膜36。在此狀態，由阻銲劑等形成的充填材45被充填在上下導通部42內。
其次，在對應於下層配線22的接續墊部之部分的下層包覆膜25，藉由照射雷射光束的雷射加工形成開口部26。又，在對應於上層配線33的接續墊部之部分的上層包覆膜36，藉由照射雷射光束的雷射加工形成開口部37。
其次，在下層包覆膜25之開口部26內及其下方，銲球(銲劑層)27係形成接續到下層配線22的接續墊部。其次，在互相鄰接的半導體構成體2之間，將下層包覆膜25、下層絕緣膜1、絕緣層31、上層絕緣膜32、及上層包覆膜36切斷時，可獲得多個第1圖所示之半導體裝置。
在如此獲得的半導體裝置中，因係在設於半導體構成體2下及其周圍的下層絕緣膜1下，將下層配線22設成接續於半導體構成體2之柱狀電極13，可將銲球(外部接續用電極)27之配置區域作成比半導體構成體2之平面尺寸更大，而且不具備底板51，因此可作成薄型化。此外，底板51亦可由鋁等之其他金屬而形成。
(第1實施形態之變形例)
但是，在第7圖顯示的步驟中，在形成基底金屬層23, 34,43之後，亦可作成如第10圖所示。即，在基底金屬層23之下面及基底金屬層34之上面圖案化形成抗電鍍膜57,58。此時，在對應於包含貫穿孔41之上部金屬層24形成區域的部分之抗電鍍膜57，形成開口部59。又，在對應於包含貫穿孔41之上部金屬層35形成區域的部分之抗電鍍膜58，形成開口部60。
其次，進行將基底金屬層23,34,43作為電鍍電流路徑之銅的電解電鍍，藉以在抗電鍍膜57之開口部59內的基底金屬層23之下面形成上部金屬層24，又在抗電鍍膜58之開口部60內的基底金屬層34之上面形成上部金屬層35，更在貫穿孔41內的基底金屬層43之內面形成上部金屬層44。
其次，將抗電鍍膜57,58剝離，接著，將上部金屬層24,35作為遮罩將基底金屬層23,34不要的部分加以腐蝕而除去時，如第8圖所示，僅在上部金屬層24上殘留基底金屬層23，又僅在上部金屬層35下殘留基底金屬層34。又，在此狀態，在貫穿孔41之內壁面形成基底金屬層43及上部金屬層44形成的2層構造之上下導通部42。
(第2實施形態)
第11圖係顯示本發明之第2實施形態的半導體裝置之剖面圖。在此半導體裝置中，與第1圖所示之半導體裝置相異之點，係將下層配線22作成由銅形成的第1基底金屬層(下層基底金屬層)23a、銅形成的第2基底金屬層(另外之下層基底金屬層)23b、及銅形成的上部金屬層(下層上部金 屬層)24之3層構造；將上層配線33作成由銅形成的第1基底金屬層(上層基底金屬層)34a、銅形成的第2基底金屬層(另外之上層基底金屬層)34b、及銅形成的上部金屬層(上層上部金屬層)35之3層構造的點。此時，在對應於半導體構成體2之柱狀電極13的下面中央部之部分的第1基底金屬層23a、下層絕緣膜1及黏著層3，設置開口部21。
其次，將說明此半導體裝置之製造方法的一例。首先，如第12圖所示，準備：在由銅箔形成的底板51之上面，形成由無電解鎳電鍍形成的保護金屬層(下層保護金屬層)61、無電解銅電鍍形成的第1基底金屬層23a及由環氧系樹脂、聚亞醯胺系樹脂、玻璃布基材環氧樹脂等形成的下層絕緣膜1之物件。
此時，此已準備的物件之尺寸，係為可形成多個第11圖所示之完成後之半導體裝置的尺寸。又，下層絕緣膜1中由環氧系樹脂形成的熱硬化性樹脂係已經硬化。在此，第1基底金屬層23a之上面，為了使與包含形成於該上面的樹脂之材料所形成的下層絕緣膜1之密接性作成良好，藉由預先實施表面粗化處理而成為粗面化。此點係與上述第1實施形態之情況大不相同之點。在此，表面粗化處理之一例，是舉將第1基底金屬層23a之上面浸泡在適宜的腐蝕液之方法為例。表面粗化處理造成的表面粗度，可由腐蝕液之材料而調整。但是，表面粗化處理並不限定於此方法，亦可為利用乾式腐蝕等之其他方法者。
其次，藉由使半導體構成體2之柱狀電極13及封裝膜 14之下面經由環氧系樹脂形成之黏著層3而黏著，而將半導體構成體2搭載於下層絕緣膜1之上面的半導體構成體搭載區域。此時，亦使用印刷法或分配器等預先供給被稱為NCP(非導電性糊膏)之糊膏狀的黏著材、或被稱為NCF(非導電性薄膜)之薄片狀黏接材，利用加熱壓著而將半導體構成體2固著在下層絕緣膜1。
其次，如第13圖所示，在包含有黏著層3之半導體構成體2的周圍之形成有第1基底金屬層23a的下層絕緣膜1上面，將格子狀之絕緣層形成用薄板31a定位，且使用銷加以固定。此時，絕緣層形成用薄板31a，亦係在玻璃布等形成的基材上含浸環氧系樹脂等形成的熱硬化性樹脂，將熱硬化性樹脂作成半硬化狀態而形成薄片狀，利用衝孔而形成多個方形之開口部52者。絕緣層形成用薄板31a之開口部52的尺寸係稍大於半導體構成體2之尺寸。因此，在絕緣層形成用薄板31a與半導體構成體2之間形成間隙53。
其次，在絕緣層形成用薄板31a之上面，配置有在銅箔形成的子底板54之下面形成由無電解鎳電鍍形成的保護金屬層(上層保護金屬層)62、無電解銅電鍍形成的第1基底金屬層34a及上層絕緣膜形成用層32a者。此情況，上層絕緣膜形成用層32a亦係由與下層絕緣膜1同樣的材料製成，其中由環氧系樹脂等形成的熱硬化性樹脂被作成半硬化狀態。在此，第1基底金屬層34a之下面，為了使與包含形成於該下面的樹脂之材料所形成的上層絕緣膜32之密接性作成良好，藉由預先實施表面粗化處理而成為粗 面化。此點係與上述第1實施形態之情況大幅相異之點。
其次，如第14圖所示，使用一對加熱加壓板55,56從上下對絕緣層形成用薄板31a及上層絕緣膜形成用層32a進行加熱加壓。藉由此加熱加壓，絕緣層形成用薄板31a及上層絕緣膜形成用層32a中之熱硬化性樹脂會流動而充填於第13圖所示之間隙53，藉由其後之冷卻而固化，而在包含黏著層3的半導體構成體2之周圍的下層絕緣膜1之上面形成絕緣層31，且在半導體構成體2及絕緣層31之上面形成上層絕緣膜32。
其次，當使用腐蝕液連續地將底板51、保護金屬層61、子底板54、及保護金屬層62加以除去時，如第15圖所示，第1基底金屬層23a之下面被露出，且第1基底金屬層34a之上面亦露出。在此狀態，鎳形成的保護金屬層61,62，在利用銅之腐蝕液將銅形成的底板51及子底板54除去時，係用於保護同樣的銅形成的第1基底金屬層23a,34a不被腐蝕者。雖然保護金屬層61,62係在將底板51及子底板54除去之後，使用Ni之腐蝕液而除去，但是此時，銅形成的第1基底金屬層23a,34a係不被腐蝕。其後，在此狀態，由於將半導體構成體2密封的絕緣層31、上層絕緣膜32及下層絕緣膜1被硬化，故即使底板51、保護金屬層61、子底板54、及保護金屬層62被除去時，亦可充分地確保強度。
其次，如第16圖所示，藉由將雷射光束照射在對應於半導體構成體2之柱狀電極13的下面中央部之部分的第1 基底金屬層23a、下層絕緣膜1及黏著層3之雷射加工，而形成開口部21。又，在第1基底金屬層23a、下層絕緣膜1、絕緣層31、上層絕緣膜32及第1基底金屬層34a之預定處，使用機械鑽頭形成貫穿孔41。
其次，如第17圖所示，在包含經由第1基底金屬層23a、下層絕緣膜1及黏著層3之開口部21而露出的半導體構成體2之柱狀電極13的下面之第1基底金屬層23a之下面全體、第1基底金屬層34a之上面全體及貫穿孔41之內壁面，藉由銅之無電解電鍍而形成基底金屬層23b,34b,43。其次，進行將基底金屬層23b,34b,43作為電鍍電流路徑之銅的電解電鍍，藉以在基底金屬層23b,34b,43之表面形成上部金屬層24,35,44。
其次，利用微影蝕刻法，將上部金屬層24,35及第1、第2基底金屬層23a,34a,23b,34b進行圖案化時，成為如第18圖所示的樣子。即，在下層絕緣膜1的下面，形成由第1、第2基底金屬層23a,23b及上部金屬層24形成的3層構造之下層配線22。又，在上層絕緣膜32之上面，形成由第1、第2基底金屬層34a,34b及上部金屬層35形成的3層構造之上層配線33。更在貫穿孔41之內壁面，形成由基底金屬層43及上部金屬層44形成的2層構造之上下導通部42。以下，當通過與上述第1實施形態同樣的步驟時，可獲得第11圖所示之多個半導體裝置。
(第3實施形態)
第19圖係顯示本發明之第3實施形態的半導體裝置之 剖面圖。在此半導體裝置中，與第1圖所示之半導體裝置大幅相異之點，係將下層配線及上層配線作成多層(2層)配線構造之點。即，設置於第1下層絕緣膜1A之下面的第1下層配線22A之一端部，係經由設於第1下層絕緣膜1A及黏著層3的開口部21A而接續到半導體構成體2之柱狀電極13。在包含第1下層配線22A之第1下層絕緣膜1A的下面，設置與第1下層絕緣膜1A同一材料形成的第2下層絕緣膜1B。
設置於第2下層絕緣膜1B之下面的第2下層配線22B之一端部，係經由設於第2下層絕緣膜1B的開口部21B而接續到第1下層配線22A之接續墊部。在包含第2下層配線22B之第2下層絕緣膜1B的下面，設置下層包覆膜25。在下層包覆膜25之開口部26內及其下方，銲球27設置成接續到第2下層配線22B的接續墊部。
設置於第1上層絕緣膜32A之上面的第1上層配線33A，係經由上下導通部42而接續到第1下層配線22A。在包含第1上層配線33A之第1上層絕緣膜32A之上面，設置與第1上層絕緣膜32A同一材料製成的第2上層絕緣膜32B。
設置於第2上層絕緣膜32B之上面的第2上層配線33B之一端部，係經由設於第2上層絕緣膜32B的開口部71而接續到第1上層配線33A之接續墊部。在包含第2上層配線33B之第2上層絕緣膜32B的上面，設置上層包覆膜36。在對應於第2上層絕緣膜33B之接續墊部的部分之上 層包覆膜36設置開口部37。此外，下層配線及上層配線亦可作成3層以上之多層配線構造。
(第4實施形態)
第20圖係顯示本發明之第4實施形態的半導體裝置之剖面圖。在此半導體裝置中，與第1圖之半導體裝置大幅相異之點，係在半導體構成體2之周圍的下層絕緣膜1之上面設置第2下層配線22B，在上層絕緣膜32之下面設置第2上層配線33B之點。
其後，設置於下層絕緣膜1之下面的第1下層配線22A，係經由設於下層絕緣膜1的開口部72而接續到第2下層配線22B之接續墊部。設置於上層絕緣膜32之上面的第1上層配線33A，係經由設置於上層絕緣膜32之開口部73而接續到第2上層配線33B之接續墊部。此外，在此情況，半導體構成體2之矽基板4的上面，係經由黏著層74而黏著到包含第2上層配線33B之上層絕緣膜32的下面中央部。
其次，關於此半導體裝置之製造方法的一例之最初的步驟，將參照第21圖說明。此情況，在形成於底板51之上面的下層絕緣膜1之上面，形成由無電解銅電鍍形成的基底金屬層及由無電解銅電鍍形成的上部金屬層所形成的2層構造之第2下層配線22B。形成於子底板54之下面的上層絕緣膜32中由環氧系樹脂等形成的熱硬化性樹脂已經被硬化。其後，在上層絕緣膜32之下面，形成由無電解銅電鍍形成的基底金屬層及由無電解銅電鍍形成的上部金 屬層所形成的2層構造之第2上層配線33B。
而，在最初之步驟中，首先，藉由使半導體構成體2之柱狀電極13及封裝膜14之下面經由黏著層3而黏著，而將半導體構成體2搭載於下層絕緣膜1之上面的半導體構成體搭載區域。其次，在包括含有黏著層3之半導體構成體2的周圍之第2下層配線22B的下層絕緣膜1之上面，固定有格子狀之絕緣層形成用薄板31a。
其次，在半導體構成體2的矽基板4之上面，使用分配器等塗布由環氧系樹脂等形成的液狀之黏著材74a。其次，在絕緣層形成用薄板31a之上面，配置在子底板54之下面形成有上層絕緣膜32及第2上層配線33B者。其次，使用一對加熱加壓板從上下進行加熱加壓，以下，當通過與上述第1實施形態同樣的步驟時，可獲得第20圖所示之多個半導體裝置。
在依此方式獲得的半導體裝置，與第19圖顯示的半導體裝置比較，即使將下層配線及上層配線作成2層配線構造之時，下層絕緣膜及上層絕緣膜亦為1層，故此部分，可作成薄型化。此外，在使用一對加熱加壓板的加熱加壓步驟中，只要絕緣層形成用薄板31a中變成流動的熱硬化性樹脂充分地迴繞於半導體構成體2的矽基板4之上面的話，亦可將黏著層74省略。
(第5實施形態)
第22圖係顯示本發明之第5實施形態的半導體裝置之剖面圖。在此半導體裝置中，與第1圖顯示之半導體裝置 相異之點，係半導體構成體2未具備封裝膜14之點。因而，包含半導體構成體2之配線10及柱狀電極13的保護膜8之下面，經由黏著層3而黏著到下層絕緣膜1之上面中央部。其後，下層配線22之一端部經由下層絕緣膜1及黏著層3之開口部21而接續到半導體構成體2之柱狀電極13。
(第6實施形態)
第23圖係顯示本發明之第6實施形態的半導體裝置之剖面圖。在此半導體裝置中，與第22圖顯示之半導體裝置相異之點，係半導體構成體2更未具備柱狀電極13之點。因而，包含半導體構成體2之配線10的保護膜8之下面，經由黏著層3而黏著到下層絕緣膜1之上面中央部。其後，下層配線22之一端部經由下層絕緣膜1及黏著層3之開口部21而接續到半導體構成體2之配線10的接續墊部(外部接續用電極)。
(第7實施形態)
第24圖係顯示本發明之第7實施形的半導體裝置之剖面圖。在此半導體裝置中，與第23圖顯示之半導體裝置相異之點，係在包含半導體構成體2之配線10的保護膜8之下面，設置由聚亞醯胺樹脂、環氧系樹脂等之絕緣材形成的靜電防止用之保護膜86之點。因而，在此情況，半導體構成體2之靜電防止用之保護膜86的下面經由黏著層3而黏著到下層絕緣膜1之上面中央部。其後，下層配線22之一端部經由下層絕緣膜1、黏著層3及保護膜86之開口部21而接續到半導體構成體2之配線10的接續墊部。
但是，在將半導體構成體2搭載於下層絕緣膜1上之前，在保護膜86並未形成開口部21。其後，未有開口部21之保護膜86，其本身從形成於晶圓狀態的矽基板4下之時點到半導體構成體2搭載於下層絕緣膜1上之時點為止，係為保護形成於矽基板4下之積體電路免受到靜電者。
(第8實施形態)
第25圖係顯示本發明之第8實施形態的半導體裝置之剖面圖。在此半導體裝置中，與第1圖之半導體裝置大幅相異之點，係未具有上下導通部42之點。在此實施形態中，兩面配線構造之電路基板81係以方形框狀配置在半導體構成體2之周圍，上下之配線係經由設置於此電路基板的導電層而導通。
即，電路基板81具備由玻璃布基材環氧樹脂等形成的方形框狀之基板82。在基板82之下面，設置由銅箔形成的第2下層配線(中間配線)22C，在上面設置由銅箔形成的第2上層配線(中間配線)33C。第2下層配線22C及第2上層配線33C，係經由設置於基板82之內部的導電性糊膏等所形成的上下導通部83而接續。
其後，電路基板81係在隱入於絕緣層31之上部側的狀態，在半導體構成體2之周圍隔著間隔而配置，在電路基板81與下層絕緣膜1之間及在電路基板81與半導體構成體2之間設置絕緣層31。在半導體構成體2、電路基板81及絕緣層31之上面設置有上層絕緣膜32。
設置於下層絕緣膜1之下面的第1下層配線22A，係 經由設置於下層絕緣膜1及絕緣層31之開口部84而接續到第2下層配線22C之接續墊部。設置於上層絕緣膜32之上面的第1上層配線33A，係經由設置於上層絕緣膜32之開口部85而接續到第2上層配線33C之接續墊部。
其次，關於此半導體裝置之製造方法的一例之最初的步驟，將參照第26圖說明。首先，藉由使半導體構成體2之柱狀電極13及封裝膜14之下面經由黏著層3而黏著，而將半導體構成體2搭載於下層絕緣膜1之上面的半導體構成體搭載區域。其次，在包括含有黏著層3之半導體構成體2的周圍之第2下層配線22C的下層絕緣膜1之上面，配置格子狀之絕緣層形成用薄板31a。
其次，在絕緣層形成用薄板31a之上面，配置格子狀之電路基板81。接著，在電路基板81之上面配置有在子底板54之下面形成有上層絕緣膜形成用層32a者。其次，使用一對加熱加壓板從上下進行加熱加壓，以下，當通過與上述第1實施形態同樣的步驟時(其中，除了上下導通部41形成步驟以外，又在切斷步驟將電路基板81切斷)，可獲得第25圖所示之多個半導體裝置。
(第9實施形態)
第27圖係顯示本發明之第9實施形態的半導體裝置之剖面圖。在此半導體裝置中，與第25圖之半導體裝置大幅相異之點，係將電路基板81埋入絕緣層31之中央部，使半導體裝置全體之絕緣層數量相對於電路基板81之厚度方向的中心為對稱之點。
即，絕緣層31係厚度由同一之下側絕緣層31A及上側絕緣層31B構成，電路基板81係其厚度方向的中心與下側絕緣層31A及上側絕緣層31B之境界面一致。又，半導體構成體2之矽基板4的上面，係藉由黏著層74而黏著在上層絕緣膜32。依此方式，為了獲得半導體裝置，如第28圖所示，在下層絕緣膜1的上面配置下側絕緣層形成用薄板31A，接著將格子狀之電路基板81配置在下側絕緣層形成用薄板31A上。其次，在電路基板81之上面配置格子狀之上側絕緣層形成用薄板31B，又，在半導體構成體2之矽基板4之上面，使用分配器塗布由環氧系樹脂形成的液狀之黏著材74a。其次，當在上側絕緣層形成用薄板31B之上面，配置在由銅箔形成的子底板54的下面形成上層絕緣膜32者之時，成為第28圖的狀態。此後，與其他實施形態一樣地，使用一對加熱加壓板55,56從上下對下側絕緣層形成用薄板31A、上側絕緣層形成用薄板31B及黏著材74a進行加熱加壓的話即可。此外。在上述中，雖然係以2片絕緣層形成用薄板形成絕緣層31之情況來說明，但是並不限定於2片，可將多片絕緣層形成用薄板加以堆疊而形成。即使絕緣層形成用薄板為多片之情況時，賦予電路基板81之位置為使得其厚度方向之中心與絕緣層31之厚度方向的中心一致為較佳。又，半導體裝置全體相對於電路基板81之厚度方向的中心，不僅將絕緣層之數量作成同數而已，而且對應的各絕緣層之厚度也作成同一為較佳。
(其他之變形例)
將電路基板81埋入於第8實施形態、第9實施形態所示的絕緣層31中之構造，亦可適用於第2~7實施形態。又，本發明之半導體裝置及其製造方法，根據其宗旨可作各種變形而適用。
1‧‧‧下層絕緣膜
2‧‧‧半導體構成體
3‧‧‧黏著層
4‧‧‧矽基板
5‧‧‧接續墊
6‧‧‧絕緣膜
8‧‧‧保護膜
10‧‧‧配線
13‧‧‧柱狀電極
14‧‧‧封裝膜
22,22A,22B,22C‧‧‧下層配線
25‧‧‧下層包覆膜
27‧‧‧銲球
31‧‧‧絕緣層
31A‧‧‧下側絕緣層
31B‧‧‧上側絕緣層
31a‧‧‧下側絕緣層形成用薄板
31b‧‧‧上側絕緣層形成用薄板
32‧‧‧上層絕緣膜
33,33A,33B,33C‧‧‧上層配線
36‧‧‧上層包覆膜
41‧‧‧貫穿孔
42‧‧‧上下導通部
51‧‧‧底板
54‧‧‧子底板
81‧‧‧電路基板
82‧‧‧基板
83‧‧‧上下導通部
第1圖係本發明之第1實施形態的半導體裝置的剖面圖。
第2圖係第1圖顯示之半導體裝置之製造方法的一例之最初步驟的剖面圖。
第3圖係接著第2圖之步驟的剖面圖。
第4圖係接著第3圖之步驟的剖面圖。
第5圖係接著第4圖之步驟的剖面圖。
第6圖係接著第5圖之步驟的剖面圖。
第7圖係接著第6圖之步驟的剖面圖。
第8圖係接著第7圖之步驟的剖面圖。
第9圖係接著第8圖之步驟的剖面圖。
第10圖係顯示用於說明第1圖顯示之半導體裝置之製造方法其它例子的預定之步驟的剖面圖。
第11圖係本發明之第2實施形態的半導體裝置的剖面圖。
第12圖係第11圖顯示之半導體裝置之製造方法的一例之最初步驟的剖面圖。
第13圖係接著第12圖之步驟的剖面圖。
第14圖係接著第13圖之步驟的剖面圖。
第15圖係接著第14圖之步驟的剖面圖。
第16圖係接著第15圖之步驟的剖面圖。
第17圖係接著第16圖之步驟的剖面圖。
第18圖係接著第17圖之步驟的剖面圖。
第19圖係本發明之第3實施形態的半導體裝置的剖面圖。
第20圖係本發明之第4實施形態的半導體裝置的剖面圖。
第21圖係第20圖顯示之半導體裝置之製造方法的一例之最初步驟的剖面圖。
第22圖係本發明之第5實施形態的半導體裝置的剖面圖。
第23圖係本發明之第6實施形態的半導體裝置的剖面圖。
第24圖係本發明之第7實施形態的半導體裝置的剖面圖。
第25圖係本發明之第8實施形態的半導體裝置的剖面圖。
第26圖係第25圖顯示之半導體裝置之製造方法的一例之最初步驟的剖面圖。
第27圖係本發明之第9實施形態的半導體裝置的剖面圖。
第28圖係用於說明第27圖所顯示之半導體裝置之製造方法的剖面圖。
1‧‧‧下層絕緣膜
2‧‧‧半導體構成體
3‧‧‧黏著層
31a‧‧‧下側絕緣層形成用薄板
32a‧‧‧上層絕緣膜
51‧‧‧底板
52‧‧‧開口部
53‧‧‧間隙
54‧‧‧子底板

Claims (26)

  1. 一種半導體裝置，其特徵為具備：半導體構成體(2)，具有半導體基板(4)及設置於該半導體基板下之多個外部接續用電極(13)；下層絕緣膜(1)，設置於上述半導體構成體下及其周圍；下層配線(22,22A)，在上述下層絕緣膜下設置成接續至上述半導體構成體之外部接續用電極；絕緣層(31)，設置於上述半導體構成體之周圍的上述下層絕緣膜上；上層絕緣膜(32)，設於上述半導體構成體及上述絕緣層上；及上層配線(33,33A)，設於上述上層絕緣膜上，搭載上述下層絕緣膜的一底板(51)係被除去，在上述半導體構成體之周圍的上述絕緣層(31)之上部設置有電路基板(81)，其具有另外的下層配線(22C)、另外的上層配線(33C)及接續此等的上下導通部(83)，上述下層配線(22A)係接續到上述另外的下層配線(22C)，而上述上層配線(33A)係接續到上述另外的上層配線(33C)。
  2. 如申請專利範圍第1項之半導體裝置，其中上述半導體構成體係透過黏著層(3)而黏著在上述下層絕緣膜上。
  3. 如申請專利範圍第1項之半導體裝置，其中上述電路基板之上面係與上述絕緣層(31)之上面為同一面。
  4. 如申請專利範圍第1項之半導體裝置，其中在包含上述下層配線的上述下層絕緣膜下設置下層包覆膜(25)，其在 對應於上述下層配線的接續墊部之部分具有開口部(26)。
  5. 如申請專利範圍第4項之半導體裝置，其中在上述下層包覆膜的開口部內及其下方，銲劑層(27)係設置成接續到上述下層配線的接續墊部。
  6. 如申請專利範圍第1項之半導體裝置，其中上述半導體構成體具有封裝膜(14)，其設置於上述半導體基板下之上述外部接續用電極之間。
  7. 如申請專利範圍第1項之半導體裝置，其中上述半導體構成體具有黏著層(3)，其設置於上述半導體基板下之上述外部接續用電極之間。
  8. 一種半導體裝置，其特徵為具備：半導體構成體(2)，具有半導體基板(4)及設置於該半導體基板下之多個外部接續用電極(13)；下層絕緣膜(1)，設置於上述半導體構成體下及其周圍；下層配線(22,22A)，在上述下層絕緣膜下設置成接續至上述半導體構成體之外部接續用電極；絕緣層(31)，設置於上述半導體構成體之周圍的上述下層絕緣膜上；上層絕緣膜(32)，設於上述半導體構成體及上述絕緣層上；及上層配線(33,33A)，設於上述上層絕緣膜上，搭載上述下層絕緣膜的底板(51)係被除去，在上述半導體構成體之周圍的上述絕緣層(31)內設置有電路基板(81)，其具有另外的下層配線(22C)、另外的上層配線(33C)及接續此等的上下導通部(83)，上述下層配線(22A)係接續到上述另外的下層配線(22C)，而上述 上層配線(33A)係接續到上述另外的上層配線(33C)。
  9. 如申請專利範圍第8項之半導體裝置，其中上述絕緣層(31)係將多片薄板加以堆疊而構成，上述電路基板(81)被定位成其厚度方向之中心與上述絕緣層(31)之厚度方向的中心一致。
  10. 如申請專利範圍第8項之半導體裝置，其中上述絕緣層(31)係將上側絕緣層薄板(31B)及下側絕緣層薄板(31A)加以堆疊而形成，上述電路基板(81)係埋入上述上側絕緣層薄板內及上述下側絕緣層薄板內。
  11. 一種半導體裝置，其特徵為：具備：半導體構成體(2)，具有半導體基板(4)及設置於該半導體基板下之多個外部接續用電極(13)；下層絕緣膜(1)，設置於上述半導體構成體下及其周圍；下層絕緣層(31A)及上層絕緣層(31B)，設置於上述半導體構成體之周圍的上述下層絕緣膜上；電路基板(81)，設置於上述下層絕緣層及上述上層絕緣層之間且具有中間配線(22C,33C)；下層配線(22A)，在上述下層絕緣膜下，設置成接續至上述半導體構成體之外部接續用電極及上述電路基板之中間配線；上層絕緣膜(32)，設於上述半導體構成體及上述上層絕緣層上；及上層配線(33A)，在上述上層絕緣膜上設置成接續到上述電路基板之中間配線，搭載上述下層絕緣膜的一底板(51)係被除去。
  12. 如申請專利範圍第11項之半導體裝置，其中上述電路基板(81)的中間配線(22B,33B)係形成於上述電路基板的 上面及下面，上述電路基板更具有接續到形成於上述上面及下面的中間配線之上下導通部(83)。
  13. 一種半導體裝置之製造方法，其特徵為具有：在底板(51)上形成下層絕緣膜(1)的步驟；將具有半導體基板(4)及設置於該半導體基板下之多個外部接續用電極(13)的多個半導體構成體(2)固著在上述下層絕緣膜上的步驟；將絕緣層(31a)形成在上述半導體構成體之周圍的上述下層絕緣膜上，且在上述半導體構成體及上述絕緣層上形成上層絕緣膜(32a)的步驟；除去上述底板(51)的步驟；在上述下層絕緣膜下，將下層配線(22,22A)形成接續至上述半導體構成體之外部接續用電極，且在上述上層絕緣膜上形成上層配線(33,33A)的步驟；及將上述半導體構成體之間的上述下層絕緣膜、上述絕緣層、及上述上層絕緣膜加以切斷而獲得多個半導體裝置的步驟，形成上述絕緣層及上述上層配線的步驟，係包含在上述半導體構成體的周圍的上述上層配線下之上述絕緣層上，配置具有另外的下層配線(22C)、另外的上層配線(33C)及接續此等之上下導通部的電路基板(81)之步驟，將上述下層配線形成接續到上述另外的下層配線，且在上述上層絕緣膜上將上述上層配線形成接續到上述另外的上層配線。
  14. 如申請專利範圍第13項之半導體裝置之製造方法，其中將上述半導體構成體固著在上述下層絕緣膜上的步驟包含：預先供給液狀之黏著材(3)到上述下層絕緣膜上，將上述半導體構成體在上述下層絕緣膜上進行加熱加壓的步驟。
  15. 如申請專利範圍第13項之半導體裝置之製造方法，其中將上述半導體構成體固著在上述下層絕緣膜上的步驟，係包含：預先供給薄板狀之黏著材(3)到上述下層絕緣膜上，將上述半導體構成體在上述下層絕緣膜上進行加熱加壓的步驟。
  16. 如申請專利範圍第13項之半導體裝置之製造方法，其中形成上述下層配線及上述上層配線的步驟，包含：在上述下層絕緣膜、上述絕緣層及上述上層絕緣膜形成貫穿孔(21)，在上述貫穿孔內，將上下貫通部形成接續至上述下層配線及上述上層配線。
  17. 如申請專利範圍第13項之半導體裝置之製造方法，其中上述上層絕緣膜係最初形成在子底板(54)下，除去上述底板的步驟係包含除去上述子底板的步驟。
  18. 一種半導體裝置之製造方法，其特徵為具有：在底板(51)上形成下層絕緣膜(1)的步驟；將具有半導體基板(4)及設置於該半導體基板下之多個外部接續用電極(13)的多個半導體構成體(2)固著在上述下層絕緣膜上的步驟；將絕緣層(31a)形成在上述半導體構成體之周圍的上 述下層絕緣膜上，且在上述半導體構成體及上述絕緣層上形成上層絕緣膜(32a)的步驟；除去上述底板(51)的步驟；在上述下層絕緣膜下，將下層配線(22,22A)形成接續至上述半導體構成體之外部接續用電極，且在上述上層絕緣膜上形成上層配線(33,33A)的步驟；及將上述半導體構成體之間的上述下層絕緣膜、上述絕緣層、及上述上層絕緣膜加以切斷而獲得多個半導體裝置的步驟，在上述底板上形成下層絕緣膜的步驟，係包含在底板上形成下層保護金屬層(61)及下層基底金屬層(23a)，在上述下層基底金屬層(23a)上形成下層絕緣膜的步驟。
  19. 如申請專利範圍第18項之半導體裝置之製造方法，其中在上述半導體構成體及上述絕緣層上形成上層絕緣膜(32a)的步驟，係包含在子底板(54)下形成上層保護金屬層(62)及上層基底金屬層(34a)，在上層基底金屬層(34a)下形成上述上層絕緣膜的步驟。
  20. 如申請專利範圍第19項之半導體裝置之製造方法，其中除去上述底板及上述子底板的步驟，係包含除去上述下層保護金屬層及上述上層保護金屬層的步驟。
  21. 如申請專利範圍第19項之半導體裝置之製造方法，其中在上述下層基底金屬層(23a)上形成下層絕緣膜的步驟，包含在上述下層基底金屬層之上面預先實施表面粗化處理的步驟；在上述上層基底金屬層(34a)下形成上述上層 絕緣膜的步驟，包含在上述上層基底金屬層之下面預先實施表面粗化處理的步驟。
  22. 如申請專利範圍第18項之半導體裝置之製造方法，其中形成上述下層配線(22)的步驟包含：將上述下層基底金屬層(23a)、另外的下層基底金屬層(23b)、及藉電解電鍍形成的下層上部金屬層(24)，依此順序形成在上述下層絕緣膜(1)下的步驟。
  23. 如申請專利範圍第22項之半導體裝置之製造方法，其中形成上層配線(33)的步驟包含：將上層基底金屬層(34a)、另外的上層基底金屬層(34b)、及藉電解電鍍形成的上層上部金屬層(35)，依此順序形成在上述上層絕緣膜(32)上的步驟。
  24. 如申請專利範圍第19項之半導體裝置之製造方法，其中上述底板、上述下層基底金屬層、上述另外的下層基底金屬層、上述下層上部金屬層、上述子底板、上述上層基底金屬層、上述另外的上層基底金屬層、及上述上層上部金屬層係由銅製成，而上述下層保護金屬層及上述上層保護金屬層係由鎳製成。
  25. 一種半導體裝置之製造方法，其特徵為具有：在底板(51)上形成下層絕緣膜(1)的步驟；將具有半導體基板(4)及設置於該半導體基板下之多個外部接續用電極(13)的多個半導體構成體(2)固著在上述下層絕緣膜上的步驟；將下側絕緣層(31A)及上側絕緣層(31B)形成在上述 半導體構成體之周圍的上述下層絕緣膜上，同時將具有中間配線(22C,33C)的電路基板(81)埋入於上述下側絕緣層及上述上側絕緣層之間，且在上述半導體構成體及上述上側絕緣層上形成上層絕緣膜(32)的步驟；除去上述底板的步驟；在上述下層絕緣膜下，將下層配線(22A)形成接續至上述半導體構成體之外部接續用電極及上述電路基板的中間配線(22C)，且在上述上層絕緣膜上將上層配線(33A)形成接續在上述電路基板的中間配線(33C)的步驟；及將上述半導體構成體之間的上述下層絕緣膜、上述下側絕緣層、上述電路基板、上述上側絕緣層、及上述上層絕緣膜加以切斷而獲得多個半導體裝置的步驟。
  26. 如申請專利範圍第25項之半導體裝置之製造方法，其中上述電路基板之上述中間配線，係形成在上述電路基板的上面及下面，上述電路基板具有接續到形成於上述之上面及下面的上述中間配線之上下導通部(83)。
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